ILC5061 IMPALA | Alldatasheet

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SOT-23 Power Supply reset Monitor Impala Linear Corporation Impala Linear Corporation 1(408) 574-3939 www.impalalinear.com June 1999 ILC5061 1.7 All-CMOS Monitor circuits in a 3-lead SOT-23 package offer the best performance in power consumption and accuracy. The ILC5061 comes in a series of ±1% accurate trip voltages to fit most microprocessor applications. Even though its output can sink 2mA, the device draws only 1µA in normal operation. Additionally, a built-in hysteresis of 5% of detect voltage simplifies system design.

  • All-CMOS design in SOT-23 and SOT-89 package
  • ±1% precision in Reset Detection
  • Only 1µA of Iq
  • 2mA of sink current capability
  • Built-in hysteresis of 5% of detection voltage supervisory applications
  • Microprocessor reset circuits
  • Memory battery back-up circuitry
  • Power-on reset circuits
  • Portable and battery powered electronics VIN VSS VREF VOUT Ordering Information* ILC5061AM-26 2.6V+1% Monitor in SOT-23 ILC5061AM-27 2.7V+1% Monitor in SOT-23 ILC5061AM-28 2.8V+1% Monitor in SOT-23 ILC5061AM-29 2.9V+1% Monitor in SOT-23 ILC5061AM-31 3.1V+1% Monitor in SOT-23 ILC5061AM-44 4.4V+1% Monitor in SOT-23 ILC5061AM-46 4.6V+1% Monitor in SOT-23 ILC5061M-26 2.6V+2% Monitor in SOT-23 ILC5061M-27 2.7V+2% Monitor in SOT-23 ILC5061M-28 2.8V+2% Monitor in SOT-23 ILC5061M-29 2.9V+2% Monitor in SOT-23 ILC5061M-31 3.1V+2% Monitor in SOT-23 ILC5061M-44 4.4V+2% Monitor in SOT-23 ILC5061M-46 4.6V+2% Monitor in SOT-23 * Standard product offering comes in tape and reel, quantity 3000 per reel orientation right VOUT VSS VIN SOT -23 (TOP VI EW) N-Channel Open Drain Output General Description Features

Applications

Pin Package Configurations

Impala Linear Corporation 2(408) 574-3939 www.impalalinear.com June 1999 ILC5061 1.7 Parameter Symbol Conditions Min Type Max Units Detect Fail Voltage VDF A grade VDF X 0.99 VDF VDF X 1.01 V Detect Fail Voltage VDF Standard grade VDF X 0.99 VDF VDF X 1.02 V Hysteresis Range VHYS VDF X 0.02 VDF X 0.05 VDF X 0.08 V Supply Current ISS VIN = 1.5V VIN = 2.0V VIN = 3.0V VIN = 4.0V VIN = 5.0V 0.9 1.0 1.3 1.6 2.0 2.6 3.0 3.4 3.8 4.2 Operating Voltage VIN VDF = 2.1~ 6.0V 1.5 10.0 V Output Current IOUT N-ch VDS = 0.5V VIN = 1.0V VIN = 2.0V VIN = 3.0V VIN = 4.0V VIN = 5.0V P-ch VDS = 2.1V VIN = 8V 2.2 7.7 10.1 11.5 13.0 -10 mA Temperature Characteristics #VDF/(#Topr!VDF) 30oC <Topr <80oC +100 Ppm/ oC Delay Time Release Voltage Output Inversion) TDLY (VDR VOUT inversion) 0.2 ms Note: 1. An additional resistor between the VIN pin and supply voltage may cause deterioration of the characteristics due to increasing VDR. Parameter Symbol Ratings Units Input Voltages VIN 12 V Output Current IOUT 50 mA Output Voltages VOUT VSS-0.3~+VIN+03 V Continuous Total SOT-23 Power Dissipation Pd 150 mW Operation Ambient temperature Topr -30~+80 oC Storage Temperature Tstg -40~+125 oC SOT-23 Power Supply reset Monitor Absolute Maximum Ratings (TA=25οοC) Electrical Characteristics (TA=25οοC)

Impala Linear Corporation 3(408) 574-3939 www.impalalinear.com June 1999 ILC5061 1.7 The following designators 1~6 refer to the timing diagram below. 1. While the input voltage (VIN) is higher than the detect volt- age (VDF), the VOUT output pin is at high impedance state. 2. When the input VIN voltage falls lower than V DF, VOUT drops near to ground voltage 3. If the input voltage further decreases below the mini- mum operating voltage (VMIN), the VOUT output becomes unstable. In this condition, if the V OUT pin is pulled up, VOUT indicates the VIN voltage. 4. During an increase of the input voltage from the V SS voltage, VOUT is not stable in the voltage below the V MIN. Exceeding that level, the output stays at the ground level SS) between the minimum operating voltage (V MIN) and the detect release voltage (VDR). 5. If the input voltage increases more than V DR, then the VOUT output pin is at high impedance state. 6. The difference between VDR and VDF is the hysteresis in the system. 5431 2 INPUT VOLTAGE (VIN) DETECT RELEASE VOLTAGE (VDR) DETECT FAIL VOLTAGE (VDF) MINIMUM OPERATING VOLTAGE (VMIN) GROUND VOLTAGE (VSS) OUTPUT VOLTAGE (VOUT) GROUND VOLTAGE (VSS) SOT-23 Power Supply reset Monitor Functional Description Timing Diagram

Impala Linear Corporation 4(408) 574-3939 www.impalalinear.com June 1999 ILC5061 1.7 OUTPUT VOLT AGE VOU T (V) OUTPUT CUR RENT IOU T (mA) VIN =4 .0V OUTPUT VOL TAGE vs OUTPUT CU RRENT ILC5061 OUTPUT VOLT AGE VOU T (V) 0. 0 40 0OUTPUT CUR RENT IOU T (µA)80 0 1. 0 10 00 60 0 20 0 0.0 0. 6 OUTP UT V OLTA GE vs OUTPUT CURRENT IL C5061 3 4 3. 5V VIN =0 .8V INPUT VOLTAGE VIN (V) 2. 0 IDD (µA) 4. 0 3. 0 1. 0 IDD vs INPUT VOLTAGE * IL C5 06 1 Topr =8 0° C 25 °C 3.0 V 2.5 V 2. 0 V 1. 5 V 0. 2 0. 4 0. 8 VIN =0 .7V INPUT VOLTAGE VIN (V) OU TPU T C URREN T IOU T (mA)20 VDS =0. 5V OUTPUT CURRENT vs INPUT VOL TAGE ILC5061 Topr =30 °C 25 °C 12 34 6 7 8 9 -3 0° C 12 4 80 °C * A spike of ½ to 1 µA may appear as Vin crosses VDR or VDF VDS = 0.5V SOT-23 Power Supply reset Monitor Typical Performance Characteristics - general conditions for all curves