ILA1068 ETC | Alldatasheet

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Technical content

Versatile Telephone Transmission Circuit with Dialler Interface The ILA1068 is a bipolar integrated circuit performing all speech and line interface functions required in fully electronic telephone sets. It performs electronic switching between dialling and speech .

  • Voltage regulator with adjustable static resistance
  • Provides supply for external circuitry
  • Symmetrical high -impedance inputs (6 4 KΩ ) for dynamic, magnetic or piezoelectric microphones
  • Asymmetrical high -impedance input (32 KΩ ) for electret microphone
  • Dual-Tone Multi -Frequency (DTMF) signal input with confidence tone
  • Mute input for pulse or DTMF dialling
  • Power down input for pulse d ial or register recall
  • Receiving amplifier for magnetic, dynamic or piezoelectric earpieces
  • Large gain setting range on microphone and earpiece amplifiers
  • Line current -dependent line loss compensation facility for microphone and earpiece amplifiers
  • Gain control adaptable to exchange supply
  • DC line voltage adjustment facility ILA1068

ORDERING INFORMATION

TA = -25° to 75° C for package BLOCK DIAGRAM

Pin No Designation Description

1 LN positive line terminal

2 GAS1 gain adjustment transmitting amplifier

3 GAS2 gain adjustment transmitting amplifier

4 QR- inverting output receiving amplifier

5 QR+ non-inverting output receiving amplifier

6 GAR gain adjustment receiving amplifier

7 MIC- inverting microphone input

8 MIC+ non-inverting microphone input

9 STAB current stabilizer

10 VEE negative line terminal

11 IR receiving amplifier input

12 PD power-down input

13 DTMF dual-tone multi-frequency input

14 MUTE mute input

15 VCC positive supply decoupling

16 REG voltage regulator decoupling

17 AGC automatic gain control input

18 SLPE slope (DC resistance) adjustment

V EE

3.6 KΩ between the current stabilizer pin STAB and

Figure 1. Supply arrangement external resistor connected between SLPE and V EE. characteristics (especially at lower voltages).

4.2 V regulator diode with an internal resistance

Figure 2. Equivalent impedance circuit the value of R7 connected between GAS1 and GAS2.

A HIGH level at MUTE enables the DTMF input and inhibits the microphone and the receiving amplifier inputs. A LOW level or an open circuit has the revers e effect. MUTE switching causes only negligible clicks at the earpiece outputs and on the line. Dial-tone multi-frequency input DTMF When the DTMF input is enabled dialling tones may be sent on to the line. The voltage gain from DTMF to LN is typically 2 5.5 dB (when R7 = 68 KΩ ) and varies with R7 in the same way as the microphone amplifier. The signalling tones can be heard in the earpiece at a low level (confidence tone). Receiving amplifier IR, QR-, QR+ and GAR The receiving amplifier has one input (IR ) and two complementary outputs, a non -inverting output QR+ and an inverting output QR -. These outputs may be used for single -ended or for differential drive depending on the sensitivity and type of earpiece used. Gain from IR to QR+ is typically 25 dB (when R4 = 100 KΩ ). This is sufficient for low -impedance magnetic or dynamic microphones, which are suited for single -ended drive. By using both outputs (differential drive), the gain is increased by 6 dB. This feature can be used when the earpiece impedance exceeds 450 Ω , (high-impedance dynamic or piezoelectric types). The output voltage of the receiving amplifier is specified for continuous -wave drive. The maximum output voltage will be higher under speech conditions where the ratio of peak to RMS value is higher. The receiving amplifier gain can be adjusted between 17 dB and 33 dB with single -ended drive and between 26 dB and 39 dB with differential drive to suit the sensitivity of the transducer used. The gain is set by the external resistor R4 connected b etween GAR and QR+. Overall receive gain between LN and QR+ is calculated by subtracting the anti -side-tone network attenuation (32 dB) from the amplifier gain. Two external capacitors, C4 = 100 pF and C7 = 10 x C4 = 1 nF, are necessary to ensure stability . A larger value of C4 may be chosen to obtain a first - order, low -pass filter. The ‘cut -off’ frequency corresponds with the time constant R4 x C4. Automatic gain control input AGC Automatic line loss compensation is achieved by connecting a resistor (R6) between AGC and VEE. The automatic gain control varies the gain of the microphone amplifier and the receiving amplifier in accordance with the DC line current. The control range is 5.8 dB which corresponds to a line length of 5 km for a 0.5 mm diameter twisted-pair copper cable with a DC resistance of 176 Ω /km and average attenuation of 1.2 dB/km. Resistor R6 should be chosen in accordance with the exchange supply voltage and its feeding bridge resistance (see Table 1). Different values of R6 give the same ratio of line currents for start and end of the control range. If automatic line loss compensation is not required, AGC may be left open. The amplifiers then all give their maximum gain as specified. Table 1 Values of resistor R6 for optimum line -loss compensation, for various usual values of exchange supply voltage (V exch) and exchange feeding bridge resistance (Rexch); R9 = 20 Ω . Vexch(V) 400 Rexch(Ω ) 600 Rexch(Ω ) 800 Rexch(Ω ) 1000 Rexch(Ω ) R6(KΩ ) 24 61.9 48.7 - - 36 100 78.8 68 60.4 48 140 110 93.1 82 60 - - 120 102 Power-Down input (PD) During pulse dialling or register recall (timed loop break), the telephone line is interrupted. During these interruptions, the telephone line provides no power for the transmission circuit or circuits supplied by VCC. The charge held on C1 will bridge these gaps. This bridging is made easier by a HIGH level on the PD input, which reduces the typical supply current from 1mA to 55 mA and switches off the voltage regulator, thus preventing discharge through LN. When PD is HIGH, the capacitor at REG is disconnected with the effect that the voltage stabilizer will have no switch -on delay after line interruptions. This minimizes the contribution of the IC to the current waveform during pulse dialling or register recall . When this facility is not required, PD may be left open-circuit. Side-tone suppression The anti -side-tone network, R1//Z line, R2, R3, R8, R9 and Z bal (see Fig.5) suppress the transmitted signal in the earpiece. Maximum compensation is obtained when the following conditions are fulfilled:

  • compatibility with a standard capacitor from the E6 or E12 range for Zbal
  •  Zbal // R8 <<R3 fulfilling condition (1) and thus ensuring correct anti -side-tone bridge operation
  •  Zbal + R8 >>R9 to avoid influencing the transmit gain. In practise Z line varies considerably with the line type and length. The value chosen for Z bal should therefore be for an average line length thus giving optimum setting for short or long lines.

Figure 3. Equivalent circuit of ILA1068 anti-side-tone bridge

Figure 4. Equivalent circuit of an anti-side-tone network in a Wheatstone bridge configuration.

  • Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

ELECTRICAL CHARACTERISTICS

Symbol Parameter Test Conditions 25°C -25°C to 70°C 25°C -25°C to 70°C Unit min max min max min max min max VLN1 Voltage Drop Over Circuit between LN and VEE V(12,14) = 0 V, Iline (01) = 5 mA Iline (01) = 15 mA Iline (01) = 100 mA Iline (01) = 140 mA 3.95 4.2 5.4 4.55 4.7 6.7 7.5 2.96 3.15 4.05 5.69 5.87 8.37 9.37 3.6 3.6 4.5 5.5 5.55 6.3 7.7 9.0 2.96 3.15 4.05 5.69 5.87 8.37 9.37 V ICC1 Supply Current V(15) = 2.8 V, V(12,14) = 0 V ICC2 Supply Current V(12,15) = 2.8 V, V(14) = 0 V - 82 - 84 - 82 - 84 µA Iline (01) = 15 mA, V(14,15) = 2.2 V for the peripheral circuits Iline (01) = 15 mA, V(14,15) = 3.0 V AU1 Voltage Gain MIC+ or MIC- to LN Iline (01) = 15 mA, V(12,14) = 0 V AU2 Voltage Gain from DTMF to LN Iline (01) = 15 mA, V(12,14) = 0 V AU3 Voltage Gain from IR to QR+ or QR- Iline (01) = 15 mA, V(12,14) = 0 V 24 26 18 32.5 18 32 18 32.5 dB VLN2 Voltage Drop Over Circuit between LN and VEE with External Resistor RVA Iline (01) = 15 mA, V(12,14) = 0 V, RVA (REG to SLPE)=39 KΩ RVA (LN to REG)=68 KΩ 4.65 3.45 5.35 4.1 3.5 2.6 6.7 5.0 4.25 3.15 5.65 4.4 3.5 2.6 6.7 5.0 V RI1 Input Impedance differential between MIC- and MIC+ Iline (01) = 15 mA 51 77 38 96 51 77 38 96 KΩ

Iline (01) = 15 mA 8.0 8.0 KΩ (continued)

Symbol Parameter Test Conditions 25°C -25°C to 70°C 25°C -25°C to 70°C Unit min max min max min max min max RI4 Input Impedance (DTMF input) RI5 Input Impedance (Receiving Amplifier Input IR) Iline (01) = 15 mA 17 25 12.75 31.25 17 25 12.75 31.25 KΩ VO1 Output Voltage Iline (01) = 15 mA THD = 2% THD = 10% 1.9 2.1 1.43 1.58 1.9 2.1 1.43 1.58 V VO2 Output Voltage Iline (01) = 15 mA THD = 2% KU Voltage Gain Iline (01) = 15 mA, V(12) = 3.5 V IPD Input Current Iline (01) = 15 mA, V(14) = 3.5 V 0 10 0 12.5 0 10 0 12.5 µA IMUTE Input Current Iline (01) = 15 mA, V(14) = 3.5 V - 15 - 18.75 - 15 - 18.75 µA Δ AU Voltage Gain Reduction Between MIC+ and MIC- to LN Iline (01) = 15 mA, V(14) = 2.8 V

Location of marking (mm): left lower corner x=0.180, y=2.555. Chip thickness: 0.46 ± 0.02 mm. Location (left lower corner), mm Pad No Symbol X Y Pad size, mm 01 LN 0.268 1.133 0.140 x 0.140 02 GAS1 0.268 0.784 0.140 x 0.140 03 GAS2 0.268 0.284 0.140 x 0.140 04 QR- 0.804 0.284 0.140 x 0.140 05 QR+ 1.068 0.284 0.140 x 0.140 06 GAR 1.708 0.284 0.140 x 0.140 07 MIC- 2.807 0.284 0.140 x 0.140 08 - 2.807 0.554 0.140 x 0.140 09 MIC+ 2.807 0.738 0.140 x 0.140 10 - 2.807 1.075 0.140 x 0.140 11 STAB 2.807 1.293 0.140 x 0.140 12 VEE 2.807 1.619 0.140 x 0.140 13 IR 2.807 1.911 0.140 x 0.140 14 PD 2.807 2.350 0.140 x 0.140 15 DTMF 1.825 2.350 0.140 x 0.140 16 MUTE 1.584 2.350 0.140 x 0.140 17 VCC 1.086 2.350 0.140 x 0.140 18 REG 0.320 2.350 0.140 x 0.140 19 AGC 0.268 1.936 0.140 x 0.140 20 SLPE 0.268 1.686 0.140 x 0.140 01 10 X Y (0,0) 3.2+ 0.03 2.8 + 0.02 Chip marking 14152