ISL6336 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Intel VR11.1 Compliant
  • Proprietary Active Pulse Positioning and Pin Adaptive Phase Alignment Modulation Scheme
  • Proprietary Active Phase Adding and Dropping with Diode Emulation for High Efficiency at Light Load
  • Precision Multiphase Core Voltage Regulation - Differential Remote Voltage Sensing - ±0.5% System Accuracy Over Life, Load, Line and Temperature - Bi-directional Adjustable Reference-Voltage Offset
  • Precision Resistor or DCR Current Sensing - Accurate Load-Line Programming - Accurate Channel-Current Balancing - Accurate Current Monito ring Output Pin (IMON)
  • Microprocessor Voltage Identification Input - Dynamic VID™ Technology - 8-Bit VID Input With VR11 Code
  • Thermal Monitor and OV Protection with OVP Output
  • Average Overcurrent Protection and Channel Current Limit
  • Precision Overcurrent Protection on IMON pin
  • Integrated Open Se nse Line Protection
  • Integrated Programmable Temperature Compensation
  • 1- to 6-Phase Operation; Coupled Inductor Compatible
  • Adjustable Switching Frequency up to 1MHz Per Phase
  • Package Option - QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline
  • Pb-Free (RoHS Compliant) Data Sheet May 28, 2009

2 FN6504.1 May 28, 2009 Pinout ISL6336, ISL6336A (48 LD QFN) TOP VIEW

Ordering Information

TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL6336CRZ* ISL6336 CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7 ISL6336IRZ* ISL6336 IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7 ISL6336ACRZ* ISL6336A CRZ 0 to+70 48 Ld 7x7 QFN L48.7x7 ISL6336AIRZ * ISL6336A IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7 *Add “-T” for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. VID6 VID5 VID4 VID3 VID2 VID0 OFS VID1 TM VR_RDY VR_FAN VR_HOT FS EN_VTT EN_PWR PSI# VID7 VCC ISEN2- PWM2 PWM3 ISEN3- ISEN3+ ISEN1+ ISEN1- PWM1 PWM4 ISEN4- TCOMP VSEN RGND COMP APA PWM5 FB IMON DAC ISEN2+ ISEN4+ ISEN5- VDIFF OVP ISEN6+ ISEN6- PWM6 REF ISEN5+ SS 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 GND ISL6336, ISL6336A

3 FN6504.1 May 28, 2009 Controller and Driver Recommendations CONTROLLER COMMENTS ISL6336 When PSI# is asserted (LOW), the controller generates a 3- level PWM pattern on the phases that are active in PSI# mode. The active phases in PSI# mode must use VR11.1 drivers, ISL6622, ISL6620 for diode emulation. ISL6336A When PSI# is asserted (LOW), the PWM pattern has only high a nd low states except for fault modes. The controller can be used with any Intersil driver such as ISL6612, ISL6614, ISL6609, ISL6610. ISL6622, ISL6620 can also be used. DRIVER GATE DRIVE VOLTAGE # OF GATE DRIVES DIODE EMULATION (DE) GATE DRIVE OPTIMIZATION (GVOT) COMMENTS ISL6622 12V Dual Output (Single Phase) Yes Yes Use for phases that are active in PSI# mode and its coupled channel in coupled inductor applications. Can also be used on all channels. ISL6620 5V Dual Output (Single Phase) Yes No Use for phases that are active in PSI# mode and its coupled channel in coupled inductor applications. Can also be used on all channels. ISL6612, ISL6612A 12V Dual Output (Single Phase) No No Can be used with phases that are inactive in PSI# mode or with all channels when using the ISL6336A ISL6596 5V Dual Output (Single Phase) No No Can be used with phases that are inactive in PSI# mode or with all channels when using the ISL6336A ISL6614, ISL6614A 12V Quad Output (Two Phase) No No Can be used with phases that are inactive in PSI# mode or with all channels when using the ISL6336A ISL6610 5V Quad Output (Two Phase) No No Can be used with phases that are inactive in PSI# mode or with all channels when using the ISL6336A NOTE: Intersil 5V and 12V drivers are mostly pin-to-pin compatible and allow dual footprint layout to optimize MOSFET selection and efficiency. Dual = One Synchronous Channel; Quad = Two Synchronous channels. ISL6336, ISL6336A

4 FN6504.1 May 28, 2009 ISL6336, ISL6336A Block Diagram I_TRIP OVP DRIVE POWER-ON RESET (POR) PWM1 PWM2 PWM3 PWM6 GND VCC FB FS S CLOCK, VID5 VID4 VID3 VID2 COMP VSEN GENERATOR,RAMP ISEN3- ISEN4+ VID1 RGND VDIFF VR_RDY OVP EN_PWR 0.875V I_TOT DYNAMIC VID DAC TEMPERATURE CHANNEL DETECT OFS TRI-STATE ISEN1+ ISEN2-CHANNEL CURRENT SENSE OVP VID0 SOFT-START AND FAULT LOGIC OFFSET REF +175mV R E/A OC1 Q EN_VTT DAC ISEN4- ISEN3+ ISEN2+ ISEN1- IMON 0.875V VID6 VID7 PWM4 PWM5 ISEN5+ ISEN5- ISEN6+ ISEN6- TEMPERATURE COMPENSATION TCOMP TM VR_HOTVR_FAN THERMAL MONITORING SS 1.12V OC2 N GAIN COMPENSATION APP AND APA CHANNEL CURRENT BALANCE AND CURRENT LIMIT MODULATOR APP AND APA MODULATOR APP AND APA MODULATOR APP AND APA MODULATOR APP AND APA MODULATOR APP AND APA MODULATOR PSI# APA 1.12V APA CONTROL ISL6336, ISL6336A

5 FN6504.1 May 28, 2009 Typical Application - 5-Phase Buck Converter with DCR Sensing and Integrated TCOMP +5V +5V VIN VSEN VDIFF FB COMP VCC GND RGND EN_PWR PWM1 ISEN1- PWM4 ISEN4+ PWM2 ISEN2+ PWM5 ISEN5+ ISL6336 µP LOAD ISEN1+ ISEN4- ISEN2- ISEN5- TCOMP REF DAC FSOFS EN_VTTVTT VIN RT VR_FAN VR_HOT TM +5V NTC ROFS PWM VCC BOOT UGATE PHASE LGATE GND +5V VIN ISL6620 +5V VIN +5V VIN +5V VIN ISEN3- PWM6 PWM3 ISEN3+ ISEN6- ISEN6+ SS +5V VID6 VID7 VR_RDY VID5 VID4 VID3 VID2 VID1 VID0 PSI# OVP IMON RSS APA EN PWM VCC BOOT UGATE PHASE LGATE GND EN ISL6596 PWM VCC BOOT UGATE PHASE LGATE GND EN ISL6596 PWM VCC BOOT UGATE PHASE LGATE GND EN ISL6596 PWM VCC BOOT UGATE PHASE LGATE GND EN ISL6596+5V ISL6336, ISL6336A

6 FN6504.1 May 28, 2009 Typical Application - 4-Phase Buck Converter with coupled inductors +5V +5V VIN VSEN VDIFF FB COMP VCC GND RGND EN_PWR PWM1 ISEN1- PWM3 ISEN3+ PWM2 ISEN2+ PWM4 ISEN4+ ISL6336 µP LOAD ISEN1+ ISEN3- ISEN2- ISEN4- TCOMP REF DAC FSOFS EN_VTTVTT VIN RT VR_FAN VR_HOT TM +5V NTC ROFS PWM VCC BOOT UGATE PHASE LGATE GND +5V VIN ISL6620 ISEN5- PWM6 PWM5 ISEN5+ ISEN6- ISEN6+ SS +5V VID6 VID7 VR_RDY VID5 VID4 VID3 VID2 VID1 VID0 PSI# OVP IMON RSS APA EN PWM VCC BOOT UGATE PHASE LGATE GND EN ISL6620 +5V +5V +5V +5V VIN PWM VCC BOOT UGATE PHASE LGATE GND +5V VIN ISL6596 EN PWM VCC BOOT UGATE PHASE LGATE GND EN ISL6596 ISL6336, ISL6336A

7 FN6504.1 May 28, 2009 Absolute Maximum Ratings Operating Conditions Ambient Temperature Thermal Information Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W) http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VCC SUPPLY CURRENT Nominal Supply VCC = 5VDC; EN_PWR = 5VDC; R T = 100kΩ, ISEN1 = ISEN2 = ISEN3 = ISEN4 = ISEN5 = ISEN6 = 80µA -1 6 2 0 m A Shutdown Supply VCC = 5VDC; EN_PWR = 0VDC; R T = 100kΩ -1 4 1 7 m A POWER-ON RESET AND ENABLE POR Threshold VCC Rising 4.3 4.4 4.5 V VCC Falling 3.75 3.88 4.0 V EN_PWR Threshold Rising 0.875 0.897 0.920 V Falling 0.735 0.752 0.770 V EN_VTT Threshold Rising 0.875 0.897 0.920 V Falling 0.735 0.752 0.770 V REFERENCE VOLTAGE AND DAC System Accuracy of ISL6336ACRZ, ISL6336CRZ (VID = 1V to 1.6V), T J = 0°C to +70°C (Note 3) -0.5 - 0.5 %VID System Accuracy of ISL6336ACRZ, ISL6336CRZ (VID = 0.5V to 1V), TJ = 0°C to +70°C (Note 3) -5 - 5 mV System Accuracy of ISL6336AIRZ, ISL6336IRZ (VID = 1V to1.6V), TJ = -40°C to +85°C (Note 3) -0.6 - 0.6 %VID System Accuracy of ISL6336AIRZ, ISL6336IRZ (VID = 0.8V to 1V), TJ = -40°C to +85°C (Note 3) -0.7 - 0.7 %VID System Accuracy of ISL6336AIRZ, ISL6336IRZ (VID = 0.5V to 0.8V), TJ = -40°C to +85°C (Note 3) -1 - 1 %VID VID Pull-up After t D3 (see “Soft-Start” on page 19) 30 40 50 µA VID Input Low Level -- 0 . 4 V VID Input High Level 0.8 - - V Maximum DAC Source Current 3.5 - - mA Maximum DAC Sink Current 100 - - µA Maximum REF Source/Sink Current (Note 4) 50 - - µA ISL6336, ISL6336A

8 FN6504.1 May 28, 2009 PIN-ADJUSTABLE OFFSET Voltage at OFS Pin Offset resistor connected to ground 390 400 415 mV Voltage below VCC, offset resistor connected to VCC 1.574 1.60 1.635 V OSCILLATORS Accuracy of Switching Frequency Setting R T = 100kΩ 225 250 275 kHz Adjustment Range of Switching Frequency (Note 4) 0.08 - 1.0 MHz Soft-Start Ramp Rate R SS = 100kΩ (Notes 4, 5 , 6) - 1.563 - mV/µs Adjustment Range of Soft-Start Ramp Rate (Note 4) 0.625 - 6.25 mV/µs PWM GENERATOR Sawtooth Amplitude (Note 4) - 1.5 - V ERROR AMPLIFIER Open-Loop Gain R L = 10kΩ to ground (Note 4) - 96 - dB Open-Loop Bandwidth C L = 100pF, RL = 10kΩ to ground (Note 4) - 80 - MHz Slew Rate C L = 100pF (Note 4) - 25 - V/µs Maximum Output Voltage 3.8 4.4 4.9 V Output High Voltage @ 2mA 3.6 - - V Output Low Voltage @ 2mA -- 1 . 6 V REMOTE-SENSE AMPLIFIER Bandwidth (Note 4) - 20 - MHz Output High Current VSEN - RGND = 2.5V -500 - 500 µA Output High Current VSEN - RGND = 0.6V -500 - 500 µA APA INPUT APA Sink Current -5 0- µ A PWM OUTPUT Sink Impedance PWM = LOW with 1mA load 100 220 300 Ω Source Impedance PWM = HIGH, forced to 3.7V 200 320 400 Ω PSI# INPUT Threshold HIGH -- 0 . 8 V Threshold LOW 0.4 - - V CURRENT SENSE AND OVERCURRENT PROTECTION Sensed Current Tolerance ISEN1 = ISEN2 = ISEN3 = ISEN4 = ISEN5 = ISEN6 = 40µA; Offset and Mirror Error Included, RISENx = 200Ω 36.5 - 42 µA ISEN1 = ISEN2 = ISEN3 = ISEN4 = ISEN5 = ISEN6 = 80µA; Offset and Mirror Error Included, RISENx = 200Ω 74 - 83 µA Overcurrent Trip Level for Average Current (PSI# = 1) Offset and Mirror Error Included, RISENx = 200Ω 96 105 117 µA Overcurrent Trip Level for Average Current (PSI# = 0) Number of Phases = 6, Drop to 1-Phase - 135 - µA Peak Current Limit for Individual Channel 115 129 146 µA IMON Voltage Clamp and OCP Trip Level 1.085 1.11 1.14 V Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ISL6336, ISL6336A

9 FN6504.1 May 28, 2009 THERMAL MONITORING AND FAN CONTROL TM Input Voltage for VR_FAN Trip 38.7 39.1 39.6 %VCC TM Input Voltage for VR_FAN Reset 44.6 45.1 45.5 %VCC TM Input Voltage for VR_HOT Trip 32.9 33.3 33.7 %VCC TM Input Voltage for VR_HOT Reset 38.7 39.1 39.6 %VCC Leakage Current of VR_FAN With external pull-up resistor connected to VCC - - 5 µA VR_FAN Low Voltage With 1.24k Ω resistor pull-up to VCC, I VR_FAN = 4mA - - 0.3 V Leakage Current of VR_HOT With external pull-up resistor connected to VCC - - 5 µA VR_HOT Low Voltage With 1.24k Ω resistor pull-up to VCC, I VR_HOT = 4mA - - 0.3 V VR READY AND PROTECTION MONITORS Leakage Current of VR_RDY With external pull-up resistor connected to VCC - - 5 µA VR_RDY Low Voltage I VR_RDY = 4mA - - 0.3 V Undervoltage Threshold VDIFF Falling 48 50 52 %VID VR_RDY Reset Voltage VDIFF Rising 57 59.6 62 %VID Overvoltage Protection Threshold Before valid VID 1.250 1.273 1.300 V After valid VID, the voltage above VID 138 170 195 mV Overvoltage Protection Reset Hysteresis - 100 - mV OVP Output Low Voltage IOVP = 4mA - 0.106 0.16 V NOTES: 3. These parts are designed and adjusted for accura cy with all errors in the voltage loop included. 4. Limits should be considered ty pical and are not production tested. 5. During soft-start, VDAC rises from 0 to 1.1V first and then ramp to VID voltage after receiving valid VID input. 6. Soft-start ramp rate is determined by the adjustable soft -start oscillator frequency at the speed of 6.25mV per cycle. Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ISL6336, ISL6336A

10 FN6504.1 May 28, 2009 Functional Pin Description VCC - Supplies the power necessary to operate the chip. The controller starts to operate when the voltage on this pin exceeds the rising POR threshold and shuts down when the voltage on this pin drops below the falling POR threshold. Connect this pin directly to a +5V supply. Place a R/C filter right next to this pin for noise decoupling. The resistor and capacitor should be placed right next to the VCC pin to GND. GND - Bias and reference ground for the IC. The exposed metal pad on the bottom of the package of the ISL6336, ISL6336A is GND. EN_PWR - This pin is a threshold-sensitive enable input for the controller. Connecting the 12V supply to EN_PWR through an appropriate resistor divider provides a means to synchronize power-up of the controller and the MOSFET driver ICs. When EN_PWR is driven above 0.875V, the ISL6336, ISL6336A is active depending on status of the EN_VTT, the internal POR, and pending fault states. Driving EN_PWR below 0.745V will clear all fault states and prime the ISL6336, ISL6336A to soft-start when re-enabled. EN_VTT - This pin is another threshold-sensitive enable input for the controller. It’s typically connected to VTT output of VTT voltage regulator in the computer mother board. When EN_VTT is driven above 0.875V, the ISL6336, ISL6336A is active depending on status of ENLL, the internal POR, and pending fault states. Driving EN_VTT below 0.745V will clear all fault states and prime the ISL6336, ISL6336A to soft-start when re-enabled. FS - Use this pin to set up the desired switching frequency. A resistor, placed from FS to GND or VCC will set the switching frequency. The relationship between the value of the resistor and the switching frequency is shown in Equation 3. This pin is also used in combination with SS and PSI# to determine phase dropping operation. See Table 1. SS - Use this pin to set up the desired start-up oscillator frequency. A resistor, placed from SS to GND or VCC will set up the soft-start ramp rate. The relationship between the value of the resistor and the soft-start ramp up time is described in Equations 15 and 16. This pin is also used with FS and PSI# pins to determine phase dropping operation. See Table 1. VID[7:0] - These are the inputs to the internal DAC that generates the reference voltage for output regulation. The pins have a minimum 30µA pull-up to about 1V after t D3. There is no internal pull-up before tD3. Connect these pins to open-drain outputs with external pull-up resistors or to active pull-up outputs. The VID pins can be pulled as high as VCC plus 0.3V. VDIFF, VSEN, and RGND - VSEN and RGND form the precision differential remote-sense amplifier. This amplifier converts the differential voltage of the remote output to a single- ended voltage referenced to local ground. VDIFF is the amplifier’s output and the input to the regulation and protection circuitry. Connect VSEN and RGND to the sense pins of the remote load. VDIFF is connected to FB through a resistor. FB and COMP - The inverting input and the output of the error amplifier respectively. FB can be connected to VDIFF through a resistor. A properly chosen resistor between VDIFF and FB can set the load line (droop). The droop scale factor is set by the ratio of the ISEN resistors and the inductor DCR or the dedicated current sense resistor. COMP is tied back to FB through an external R-C network to compensate the regulator. DAC and REF - The DAC pin is the output of the precision internal DAC reference. The REF pin is the positive input of the Error Amplifier. In typical applications, a 1kΩ, 1% resistor is used between DAC and REF to generate a precision offset voltage. This voltage is proportional to the offset current determined by the offset resistor from OFS to ground or VCC. A capacitor is used between REF and ground to smooth the voltage transition during Dynamic VID™ operations. PWM[6:1] - Pulse width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels is determined by the state of PWM3, PWM4, PWM5, and PWM6. Tie PWM3 to VCC to configure for 2-phase operation. Tie PWM4 to VCC to configure for 3-phase operation. Tie PWM5 to VCC to configure for 4-phase operation. Tie PWM6 to VCC to configure for 5-phase operation. PWM firing order is sequential from 1 to n with n being the number of active phases. ISEN[6:1]+, ISEN[6:1]- - The ISEN+ and ISEN- pins are current sense inputs to individual differential amplifiers. The sensed current is used for channel current balancing, overcurrent protection, and droop regulation. Inactive channels should have their respective current sense inputs left open (for example, open ISEN6+ and ISEN6- for 5-phase operation). For DCR sensing, connect each ISEN- pin to the node between the RC sense elements. Tie the ISEN+ pin to the other end of the sense capacitor through a resistor, R ISEN. The voltage across the sense capacitor is proportional to the inductor current. Therefore, the sense current is proportional to the inductor current, and scaled by the DCR of the inductor and R ISEN. To match the time delay of the internal circuit, a capacitor is needed between each ISEN+ pin and GND as described in “Current Sensing” on page 14. VR_RDY - VR_RDY indicates that the soft-start is completed and the output voltage is within the regulated range around VID setting. It is an open-drain logic output. When OCP or OVP occurs, VR_RDY will be pulled to low. It will also be pulled low if the output voltage is below the undervoltage threshold. ISL6336, ISL6336A

11 FN6504.1 May 28, 2009 OFS - The OFS pin provides a means to program a DC offset current for generating a DC offset voltage at the REF input. The offset current is generated via an external resistor and precision internal voltage references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no offset, the OFS pin should be left unterminated. TCOMP - Temperature compensation scaling input. The voltage sensed on the TM pin is utilized as the temperature input to adjust I DROOP and the overcurrent protection limit to effectively compensate for the temperature coefficient of the current sense element. To implement the integrated temperature compensation, a resistor divider circuit is needed with one resistor being connected from TCOMP to VCC of the controller and another resistor being connected from TCOMP to GND. Changing the ratio of the resistor values will set the gain of the integrated thermal compensation. When integrated temperature compensation function is not used, connect TCOMP to GND. OVP - The overvoltage protection output indication pin. This pin can be pulled to VCC and is latched when an overvoltage condition is detected. When the OVP indication is not used, keep this pin open. IMON - IMON is a current output of the average of the sum of each phase’s sensed current. A resistor connected from IMON to GND will produce a voltage that is proportional to the regulator current. The voltage at this pin is internally clamped to 1.12V. If the voltage reaches 1.12V the clamp is activated an overcurrent shutdown will be initiated. Place a resistor from this pin to GND. A capacitor in parallel with this resistor is required. The capacitor should be sized for a minimum time constant of 300µs. TM - TM is an input pin for VR temperature measurement. Connect this pin through NTC thermistor to GND and a resistor to VCC of the controller. The voltage at this pin is reverse proportional to the VR temperature. ISL6336, ISL6336A monitors the VR temperature based on the voltage at the TM pin and the output signals at VR_HOT and VR_FAN. VR_HOT - VR_HOT is used as an indication of high VR temperature. It is an open-drain logic output. It will be open when the measured VR temperature reaches a certain level. VR_FAN - VR_FAN is an output pin with open-drain logic output. It will be open when the measured VR temperature reaches a certain level. PSI# - The PSI# pin is used to change the state of the controller. When PSI# is asserted the controller will change the operating state to improve light load efficiency. The controller drops the number of active phases to 1-phase or 2-phase operation with diode emulation according to the logic shown in Table 1. The FS and SS pins are used to optimize light load efficiency for non-coupled inductor, 2-phase coupled inductor, and (n-x)-phase coupled inductor applications. The controller resumes normal operation when this pin is pulled HIGH. This pin has a 40µA internal pull-up to about 1V. APA - The APA pin is used to adjust the Adaptive Phase Alignment trip level. A 50µA current source flows into this pin. A resistor connected from this pin to COMP sets the voltage trip level. A small decoupling capacitor should be placed in parallel with the resistor for high frequency decoupling. Operation Multiphase Power Conversion Microprocessor load current profiles have changed to the point that the advantages of multiphase power conversion are impossible to ignore. The technical challenges associated with producing a single-phase converter which is both cost-effective and thermally viable, have forced a change to the cost-saving approach of multiphase. The ISL6336, ISL6336A controller helps reduce the complexity of implementation by integrating vital functions and requiring minimal output components. The block diagrams on page 5 and 6 provide top level views of multiphase power conversion using the ISL6336, ISL6336A controller. Interleaving The switching of each channel in a multiphase converter is timed to be symmetrically out of phase with each of the other channels. In a 3-phase converter for example, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. As a result, the three-phase converter has a combined ripple frequency 3x greater than the ripple frequency of any one phase. In addition, the peak-to-peak amplitude of the combined inductor current is reduced in proportion to the number of phases (see Equations 1 and 2). The increased ripple frequency and the lower ripple amplitude mean that the designer can use less per-channel inductance and lower total output capacitance for any performance specification. Figure 1 illustrates the multiplicative effect on output ripple frequency. The three channel currents (IL1, IL2, and IL3) combine to form the AC ripple current and the DC load current. The ripple component has 3x the ripple frequency of each individual channel current. Each PWM pulse is triggered 1/3 of a cycle after the start of the PWM pulse of the previous phase. The DC components of the inductor currents combine to feed the load. To understand the reduction of the ripple current amplitude in the multiphase circuit, examine Equation 1, which represents an individual channel’s peak-to-peak inductor current. In Equation 1, V IN and VOUT are the input and the output voltages respectively, L is the single-channel inductor value, and f S is the switching frequency. IPP VIN VOUT–() VOUT⋅ ISL6336, ISL6336A

regulation, and the overcurrent protection. voltage, as shown in Figure 4. proportional to the channel current IL; see Equation 5. voltage VC is replicated across the sense resistor RISEN. constant of RISEN and CT (RISEN x CT) close to 27ns. resistor and the DCR of the inductor. FIGURE 4. DCR SENSING CONFIGURATION

TABLE 3. VR11 VID 8-BIT (Continued) TABLE 3. VR11 VID 8-BIT (Continued)

TABLE 3. VR11 VID 8-BIT (Continued) TABLE 3. VR11 VID 8-BIT (Continued)

cost-effective solution can be achieved by adding droop. results from the fast changes of the load-current demand. crossing the upper specification limit. depending on the sensing method. product (IOFS x ROFS) is equal to the desired offset voltage. These functions are shown in Figure 7.

11111110 O F F

11111111 O F F

TABLE 3. VR11 VID 8-BIT (Continued)

1.6 R REF⋅

0.4 R REF⋅

FIGURE 7. OUTPUT VOLTAGE OFFSET PROGRAMMING

above in “Output-Voltage Offset Programming” on page 18. VID change and the allowable delay time. of RREF and CREF network and tVID is given by Equation 13. PSI# pin will control operation. ISL6336A is released from shutdown mode.

  1. The bias voltage applied at VCC must reach the internal

“Electrical Specifications” table beginning on page 7).

  1. The ISL6336, ISL6336A features an enable input
  2. The voltage on EN_VTT must be higher than 0.875V to

output of the VTT voltage regulator. begins soft-start and ramps the output voltage to 1.1V first. FIGURE 8. POWER SEQUENCING USING THRESHOLD

1.1V, the minimum time to validate the VID input is 500ns. second soft-start ramp time tD4 will be 256µs. and RX is the DC resistance of the current sense element. described in “Overcurrent Protection” on page 21. based on the RIMON value to set the desired time constant. is the voltage at IMON at the maximum load current. connected to GND near the load to increase accuracy. FIGURE 9. SOFT-START WAVEFORMS

1.1 R⋅ SS

FIGURE 10. IMON VOLTAGE vs OUTPUT CURRENT

25 FN6504.1 May 28, 2009 General Design Guide This design guide is intended to provide a high-level explanation of the steps necessary to create a multiphase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications. Power Stages The first step in designing a multiphase converter is to determine the number of phases. This determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. Principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board; whether through-hole components are permitted; and the total board space available for power-supply circuitry. Generally speaking, the most economical solutions are those in which each phase handles generally between 20A and 25A. All surface-mount designs will tend toward the lower end of this current range. If through-hole MOSFETs and inductors can be used, higher per-phase currents are possible. In cases where board space is the limiting constraint, current can be pushed as high as 40A per phase, but these designs require heat sinks and forced air to cool the MOSFETs, inductors, and heat-dissipating surfaces. MOSFETS The choice of MOSFETs depends on the current each MOSFET will be required to conduct; the switching frequency; the capability of the MOSFETs to dissipate heat; and the availability and nature of heat sinking and air flow. LOWER MOSFET POWER CALCULATION The calculation for heat dissipated in the lower MOSFET is simple, since virtually all of the heat loss in the lower MOSFET is due to current conducted through the channel resistance (r DS(ON)). In Equation 26, IM is the maximum continuous output current; IP-P is the peak-to-peak inductor current (see Equation 1); d is the duty cycle (VOUT/VIN); and L is the per-channel inductance. An additional term can be added to Equation 26 to account for additional loss accrued during the dead time when inductor current is flowing through the lower-MOSFET body diode. This term is dependent on the diode forward voltage at I M, VD(ON); the switching frequency, fS; and the length of dead times, tD1 and tD2, at the beginning and the end of the lower-MOSFET conduction interval respectively. Thus, the total maximum power dissipated in each lower MOSFET is approximated by the summation of PLOW,1 and PLOW,2. UPPER MOSFET POWER CALCULATION In addition to rDS(ON) losses, a large portion of the upper MOSFET losses are due to currents conducted across the input voltage (V IN) during switching. Since a substantially higher portion of the upper-MOSFET losses are dependent on switching frequency, the power calculation is more complex. Upper MOSFET losses can be divided into separate components involving the upper-MOSFET switching times; the lower-MOSFET body-diode reverse recovery charge, Q rr; and the upper MOSFET rDS(ON) conduction loss. When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET ramps up to assume the full inductor current. In Equation 28, the required time for this commutation is t 1 and the approximated associated power loss is PUP,1. At turn-on, the upper MOSFET begins to conduct and this transition occurs over a time t2. In Equation 29, the approximate power loss is PUP,2. A third component involves the lower MOSFET’s reverse recovery charge, Qrr. Since the inductor current has fully commutated to the upper MOSFET before the lower MOSFET’s body diode can draw all of Q rr, it is conducted through the upper MOSFET across VIN. The power dissipated as a result is P UP,3 and is approximated in Equation 30 : Finally, the resistive part of the upper MOSFET’s is given in Equation 31 as PUP,4. The total power dissipated by the upper MOSFET at full load can now be approximated as the summation of the results from Equations 28, 29, 30 and 31. Since the power equations depend on MOSFET parameters, choosing the correct MOSFETs can be an iterative process involving repetitive solutions to the loss equations for different MOSFETs and different switching frequencies. PLOW 1, rDS ON() IM ⎛⎞ 2 1d–() ILP - P, 21d–() PLOW 2, VDO N() fS IM ⎛⎞ td1 IM IP-P ⎛⎞ t d2+= (EQ. 27) PUP 1, VIN IM IP-P ⎛⎞ t1 2---- ⎛⎞ fS≈ (EQ. 28) PUP 2, VIN IM IP-P ⎛⎞ t2 2---- ⎛⎞ fS≈ (EQ. 29) PUP 3, VIN Qrr fS= (EQ. 30) PUP 4, rDS ON() IM d IP-P ISL6336, ISL6336A

26 FN6504.1 May 28, 2009 Current Sensing Resistor The resistors connected to the ISEN+ pins determine the gains in the load-line regulation loop and the channel-current balance loop as well as setting the overcurrent trip point. Select values for these resistors by the Equation 32. where R ISEN is the sense resistor connected to the ISEN+ pin, N is the active channel number, RX is the resistance of the current sense element, either the DCR of the inductor or R SENSE depending on the sensing method, and IOCP is the desired overcurrent trip point. Typically, IOCP can be chosen to be 1.2x the maximum load current of the specific application. With integrated temperature compensation, the sensed current signal is independent on the operational temperature of the power stage, i.e. the temperature effect on the current sense element R X is cancelled by the integrated temperature compensation function. RX in Equation 32 should be the resistance of the current sense element at the room temperature. When the integrated temperature compensation function is disabled by pulling the TCOMP pin to GND, the sensed current will be dependent on the operational temperature of the power stage, since the DC resistance of the current sense element may be changed according to the operational temperature. R X in Equation 32 should be the maximum DC resistance of the current sense element at all the operational temperature. In certain circumstances, it may be necessary to adjust the value of one or more ISEN resistors. When the components of one or more channels are inhibited from effectively dissipating their heat so that the affected channels run hotter than desired, choose new, smaller values of R ISEN for the affected phases (see the section titled “Channel-Current Balance” on page 15). Choose R ISEN,2 in proportion to the desired decrease in temperature rise in order to cause proportionally less current to flow in the hotter phase. In Equation 33, make sure that ΔT 2 is the desired temperature rise above the ambient temperature, and ΔT1 is the measured temperature rise above the ambient temperature. While a single adjustment according to Equation 33 is usually sufficient, it may occasionally be necessary to adjust R ISEN two or more times to achieve optimal thermal balance between all channels. Load-Line Regulation Resistor The load-line regulation resistor is labelled RFB in Figure 6. Its value depends on the desired loadline requirement of the application. The desired loadline can be calculated by Equation 34: where IFL is the full load current of the specific application, and VRDROOP is the desired voltage droop under the full load condition. Based on the desired loadline RLL, the loadline regulation resistor can be calculated by Equation 35: where N is the active channel number, RISEN is the sense resistor connected to the ISEN+ pin, and RX is the resistance of the current sense element, either the DCR of the inductor or RSENSE depending on the sensing method. If one or more of the current sense resistors are adjusted for thermal balance, as in Equation 35, the load-line regulation resistor should be selected based on the average value of the current sensing resistors, as given in Equation 36: where R ISEN(n) is the current sensing resistor connected to the nth ISEN+ pin. Compensation The two opposing goals of compensating the voltage regulator are stability and speed. Depending on whether the regulator employs the optional load-line regulation as described in Load-Line Regulation, there are two distinct methods for achieving these goals. COMPENSATING LOAD-LINE REGULATED CONVERTER The load-line regulated converter behaves in a similar manner to a peak-current mode controller because the two poles at the output-filter L-C resonant frequency split with the introduction of current information into the control loop. The final location of these poles is determined by the system function, the gain of the current signal, and the value of the compensation components, R C and CC. Since the system poles and zero are affected by the values of the components that are meant to compensate them, the solution to the system equation becomes fairly complicated. Fortunately there is a simple approximation that comes very close to an optimal solution. Treating the system as though it were a voltage-mode regulator by compensating the L-C poles and the ESR zero of the voltage-mode approximation yields a solution that is always stable with very close to ideal transient performance. RISEN RX 105 10 6–× IOCP RISEN 2, RISEN ΔT2 ΔT1 RLL VDROOP IFL RFB NRISEN RLL RX RFB RLL RX n ∑= (EQ. 36) ISL6336, ISL6336A

outlined in “Load-Line Regulation Resistor” on page 26. set of equations for the compensation components. “Electrical Specifications” table beginning on page 7. Equation 37 unless some performance issue is noted. performance per the type III compensation discussion below. shift below the system bandwidth. FIGURE 19. COMPENSATION CONFIGURATION FOR

0.75 VIN

2 VPP RFB LC

FIGURE 20. COMPENSATION CIRCUIT FOR ISL6336, ISL6336A

28 FN6504.1 May 28, 2009 In Equation 38, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent-series resistance of the bulk output-filter capacitance; and V PP is the peak- to-peak sawtooth signal amplitude as described in the “Electrical Specifications” table beginning on page 7. Output Filter Design The output inductors and the output capacitor bank together form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. The output filter also must provide the transient energy until the regulator can respond. Because it has a low bandwidth compared to the switching frequency, the output filter necessarily limits the system transient response. The output capacitor must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output capacitors are the maximum size of the load step, ΔI; the load-current slew rate, di/dt; and the maximum allowable output-voltage deviation under transient loading, ΔV MAX. Capacitors are characterized according to their capacitance, ESR, and ESL (equivalent series inductance). At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total output voltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount, as shown in Equation 39: The filter capacitor must have sufficiently low ESL and ESR so that ΔV < ΔV MAX. Most capacitor solutions rely on a mixture of high-frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. Minimizing the ESL of the high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation. The ESR of the bulk capacitors also creates the majority of the output-voltage ripple. As the bulk capacitors sink and source the inductor ac ripple current (see “Interleaving” on page 11 and Equation 2), a voltage develops across the bulk-capacitor ESR equal to I C,PP (ESR). Thus, once the output capacitors are selected, the maximum allowable ripple voltage, V PP(MAX), determines the lower limit on the inductance, as shown in Equation 40. Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output voltage decreases more than ΔV MAX. This places an upper limit on inductance. Equation 41 gives the upper limit on L for the cases when the trailing edge of the current transient causes a greater output- voltage deviation than the leading edge. Equation 42 addresses the leading edge. Normally, the trailing edge dictates the selection of L because duty cycles are usually much less than 50%. Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. In each equation, L is the per-channel inductance, C is the total output capacitance, and N is the number of active channels. Switching Frequency There are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper-MOSFET loss calculation. These effects are outlined in “MOSFETs” on page 25, and they establish the upper limit for the switching frequency. The lower limit is established by the requirement for fast transient response CC 0.75VIN 2πfHF LC 1–⎝⎠ 2π() 2f0fHF LCR FB VP-P RC VPP 2π⎝⎠ ⎛⎞ 2f0fHF LCR FB

0.75 VIN 2πfHF LC 1–⎝⎠

C ESR() LC C ESR()– LC C ESR()– RFB 0.75VIN 2π() 2f0fHF LCR FB VP-P ΔV ESL() di dt-----⋅ ESR() Δ I⋅+≈ (EQ. 39) LE S R() VIN NV⋅ OUT–⎝⎠ ⎛⎞ VOUT⋅ L 2NCV O⋅⋅⋅ L 1.25 N C⋅⋅ ⎛⎞⋅≤ (EQ. 42) ISL6336, ISL6336A

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. same placement of these components for each phase. them in close proximity to the microprocessor socket. resistor, feedback resistor, and compensation components. common voltage. Use the remaining layers for signal wiring. reduce the associated parasitic impedances. distribution data of the related components and parameters. FIGURE 24. NORMALIZED INPUT-CAPACITOR RMS

31 FN6504.1 May 28, 2009 ISL6336, ISL6336A Package Outline Drawing L48.7x7

48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 4, 10/06 located within the zone indicated. The pin #1 indentifier may be Unless otherwise specified, tolerance : Decimal ± 0.05 Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. Dimension b applies to the metallized terminal and is measured Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. either a mold or mark feature. Dimensions are in millimeters.1. NOTES: 7.00 B A 7.00 (4X) 0.15 INDEX AREA PIN 1 TOP VIEW PIN #1 INDEX AREA 44X 0.50 4X 5.5 4837 4. 30 ± 0 . 15 136 48X 0 . 40± 0 . 1 M0.10 C AB 1324 BOTTOM VIEW 50 . 2 REF 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" C 0 . 90 ± 0 . 1 BASE PLANE SEE DETAIL "X" C C0.08 SEATING PLANE C0.10 SIDE VIEW TYPICAL RECOMMENDED LAND PATTERN ( 6 . 80 TYP ) ( 4 . 30 ) ( 48X 0 . 60 ) ( 44X 0 . 5 ) ( 48X 0 . 23 ) 0.23 +0.07 / -0.05