IGLR65R200D2 INFINEON | Alldatasheet
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Fully qualified according to JEDEC for Industrial Applications Please note: Target Datasheet to change without further notice Table 1 Key Performance Parameters Parameter Value Unit V 650 V R 240 mΩ Q 1.8 nC I 16 A Q @ 400 V 9.7 nC Q 0 nC PG‑TSON‑8 Type/Ordering Code Package Marking Related Links IGLR65R200D2 PG‑TSON‑8 65R200D see Appendix A Enhancement mode transistor ‑ Normally OFF switch• Ultra fast switching• No reverse‑recovery charge• Capable of reverse conduction• Low gate charge, low output charge• Superior commutation ruggedness• ESD (HBM/CDM) JEDEC standards• Improves system efficiency• Improves power density• Enables highest operating frequency• System cost reduction savings• Reduces EMI• Industrial, telecom, datacenter SMPS, charger and adapter based on half‑bridge topologies (half‑bridge topologies for hard and soft switching such as Totem pole PFC, high frequency LLC). DS,max DS(on),max g,typ D,pulse oss rr Public IGLR65R200D2 Target datasheet G SK S S Source D Drain Pin 5 Gate Pin 4 Source Pin 1-2 *1: Internal gate diode Kelvin Source Pin 3
650 V CoolGaN™ enhancement‑mode Power Transistor
Datasheet 2 Revision 0.1 https://www.infineon.com 2024‑04‑15 Table of Contents
Datasheet 3 Revision 0.1 https://www.infineon.com 2024‑04‑15
1 Maximum ratings
at = 25 °C, unless otherwise specified. Stresses beyond max ratings may cause permanent damage to T the device. For optimum lifetime and reliability, Infineon recommends operating conditions that do not continuously exceed 80 % of the maximum ratings stated (unless otherwise explicitly stated). For further information, contact your local Infineon sales office. Table 2 Maximum ratings Parameter Symbol Values Unit Note/ Test Condition Min. Typ. Max. Drain source voltage, continuous V ‑ ‑ 650 V V = 0 V, derating recomendation acc. JEDEC JEP198 Leakage current at drain source transient voltage I ‑ ‑ 3.3 mA V = 0 V, V = 900 V Drain source voltage transient V ‑ ‑ 900 V <1 % duty cycle, <1 μs, 1 M pulses Drain source voltage, pulsed V V ‑ ‑ 750 650 V T = 25 °C; V ≤ 0 V; cumulated stress time ≤ 1 h T = 125 °C; V ≤ 0 V; cumulated stress time ≤ 1 h Switching surge voltage, pulsed V ‑ ‑ 750 V DC bus voltage = 700 V; turn off V = 750 V; turn on I =7.3 A; T = 105 °C; f ≤ 100 kHz, t ≤100 sec. (10 million pulses) Continuous current, drain source 1) I ‑ ‑ 9.2 A T =25 °C; T = T Pulsed current, drain source I ‑16 ‑9.5 ‑ 16 9.5 A T=25 °C; I =7.1 mA; See Diagram 3, 5 T=125 °C; I =7.1 mA; See Diagram 4, Gate current, continuous 2) I ‑ ‑ 5.3 mA T=‑55 °C to T=150 °C; See Table 9 Gate current, pulsed 2) I ‑0.53 ‑ 0.53 A T=‑55 °C to T=150 °C; t = 50 ns, f = 100 kHz; See Table 9 Gate source voltage, continuous 2) V ‑10 ‑ ‑ V T=‑55 °C to T=150 °C; See Diagram Gate source voltage, pulsed 2) V ‑25 ‑ ‑ V T=‑55 °C to T=150 °C; t = 50 ns, f = 100 kHz; open drain Power dissipation P ‑ ‑ 33 W T =25 °C Operating junction temperature T ‑55 ‑ 150 °C ‑ Storage temperature T ‑55 ‑ 150 °C Max shelf life depends on storage conditions Drain‑source voltage slew‑rate dv/dt ‑ ‑ 200 V/ns ‑ Limited by T . Maximum Duty Cycle D = 0.751) We recommend using an advanced driving technique to optimize the device performance. Please see gate drive application 2) note for more details. j DS,max GS DS,trans GS DS,trans DS,trans DS,pulse DS,pulsed j GS j GS DS,surge DS,pulse D,pulse j D C j j,max D,pulse j G j G G,avg j j G,pulsed j j PULSE GS j j GS,pulse j j PULSE tot C j stg j,max
Datasheet 4 Revision 0.1 https://www.infineon.com 2024‑04‑15
2 Thermal characteristics
Table 3 Thermal characteristics Parameter Symbol Values Unit Note/ Test Condition Min. Typ. Max. Thermal resistance, junction ‑ case R ‑ ‑ 3.8 °C/W ‑ Thermal resistance, junction ‑ ambient R ‑ ‑ 150 °C/W Device on PCB, minimum footprint Thermal resistance, junction ‑ ambient for SMD version R ‑ ‑ 74 °C/W Device on 40 mm*40 mm*1.5 mm epoxy PCB FR4 with 6 cm² (one layer, 70 μm thickness) copper area for tab (source) connection and cooling. PCB is vertical without air stream cooling. Reflow soldering temperature T ‑ ‑ 260 °C reflow MSL3 thJC thJA thJA sold
Datasheet 5 Revision 0.1 https://www.infineon.com 2024‑04‑15
3 Electrical characteristics
at =25 °C, unless specified otherwiseT Table 4 Static characteristics Parameter Symbol Values Unit Note/ Test Condition Min. Typ. Max. Gate threshold voltage V 0.9 1.2 1.6 ‑ V I =0.71 mA; =10 V; =25 °C V T =0.71 mA; =10 V; =150 °CI V T Gate‑Source reverse clamping voltage V ‑ ‑ ‑8 V I =‑1 mA Drain‑Source leakage current I ‑ 0.27 5.4 ‑ μA V =650 V, =0 V, =25 °C V T =650 V, =0 V, =150 °CV V T Drain‑Source on‑state resistance R ‑ 0.200 0.430 0.240 Gate resistance R ‑ tbd ‑ Ω LCR impedance measurement; =f f , open drain; Table 5 Dynamic characteristics Parameter Symbol Values Unit Note/ Test Condition Min. Typ. Max. Input capacitance C ‑ 90 ‑ pF V =0 V; =400 V, =1 MHzV f Output capacitance C ‑ 15 ‑ pF V =0 V, =400 V, =1 MHzV f Reverse Transfer capacitance C ‑ 0.18 ‑ pF V =0 V, =400 V, =1 MHzV f Effective output capacitance, energy related 3) C ‑ tbd ‑ pF V =0 to 400 V Effective output capacitance, time related 4) C ‑ tbd ‑ pF V =0 V; =0 to 400 V; =constV I Output charge Q ‑ 10 ‑ nC =0 to 400 VV Turn‑on delay time t ‑ tbd ‑ ns I = 2.1 A; =18 Ohm; =18 Ohm; R R =1200 Ohm; =0.82 nF; =12 R C V V; see Table 8 Turn‑off delay time t ‑ tbd ‑ ns I = 2.1 A; =18 Ohm; =18 Ohm; R R =1200 Ohm; =0.82 nF; =12 R C V V; see Table 8 Rise time t ‑ tbd ‑ ns I = 2.1 A; =18 Ohm; =18 Ohm; R R =1200 Ohm; =0.82 nF; =12 R C V V; see Table 8 Fall time t ‑ tbd ‑ ns I = 2.1 A; =18 Ohm; =18 Ohm; R R =1200 Ohm; =0.82 nF; =12 R C V V; see Table 8 j GS(th) DS DS j DS DS j GS, clamp GS DSS DS GS j DS GS j DS(on) G D j G D j G,int res iss GS DS oss GS DS rss GS DS o(er) DS o(tr) GS DS D oss DS d(on) D ON OFF SS C DRV d(off) D ON OFF SS C DRV r D ON OFF SS C DRV f D ON OFF SS C DRV
Datasheet 6 Revision 0.1 https://www.infineon.com 2024‑04‑15 is a fixed capacitance that gives the same stored energy as while is rising from 0 to 400 V3) C C V is a fixed capacitance that gives the same charging time as while is rising from 0 to 400 V4) C C V Table 6 Gate charge characteristics Parameter Symbol Values Unit Note/ Test Condition Min. Typ. Max. Gate charge Q ‑ 1.8 ‑ nC V =0 to 3 V; =400 V, =2.1 AV I Table 7 Reverse conduction characteristics Parameter Symbol Values Unit Note/ Test Condition Min. Typ. Max. Source‑Drain reverse voltage V ‑ 2.2 2.5 V V =0 V; =2.1 AI Pulsed current, reverse I ‑ ‑ 16 A I =7.1 mA Reverse recovery charge 5) Q ‑ 0 ‑ nC I =2.1 A; =400 VV Excluding Qoss5) o(er) oss DS o(tr) oss DS G GS DS D SD GS SD SD,pulse G rr SD DS
Datasheet 7 Revision 0.1 https://www.infineon.com 2024‑04‑15
4 Electrical characteristics diagrams
Diagram 3: Safe operating area Diagram 4: Safe operating area I =f( ); =25 °C; =0; parameter: V T D t I =f( ); =125 °C; =0; parameter: V T D t Diagram 5: Repetitive safe operating area Diagram 6: Repetitive safe operating area I =f( ); =25 °C; ≤150 °C; parameter: V T T t I =f( ); =125 °C; ≤150 °C; parameter: V T T t D DS C p D DS C p D DS C j p D DS C j p 100 101 102 103 VDS [V] 10 2 10 1 100 101 102 ID [A] 20 ns 1 µs 10 µs 100 µs 1 ms DC 100 101 102 103 VDS [V] 10 3 10 2 10 1 100 101 ID [A] 20 ns 1 µs10 µs 100 µs 1 ms DC 0 100 200 300 400 500 600 VDS [V] 20ID [A] t 20 ns 0 100 200 300 400 500 600 VDS [V] 10ID [A] t 20 ns
Datasheet 8 Revision 0.1 https://www.infineon.com 2024‑04‑15 Diagram 7: Typ. output characteristics Diagram 8: Typ. output characteristics I =f( ); =25 °C; parameter: V T I I =f( ); =125 °C; parameter: V T I Diagram 9: Typ. Drain‑source on‑state resistance Diagram 10: Drain‑source on‑state resistance R =f( ); =125 °C; parameter: I T I R =f( ); =2.1 AT I D DS j GS D DS j GS DS(on) D j GS DS(on) j D 0 2 4 6 8 10 VDS [V] 25ID [A] 0.04 mA 0.07 mA 0.4 mA 0.7 mA 1.8 mA 4 mA 7 mA 0 2 4 6 8 10 VDS [V] 15ID [A] 0.04 mA 0.07 mA 0.4 mA 0.7 mA 1.8 mA 4 mA 7 mA ID [A] 360 380 400 420 440 460 480 500 RDS(on) [m ] 0.04 mA 0.07 mA 0.4 mA 0.7 mA 1.8 mA 4 mA 7 mA -50 -25 0 25 50 75 100 125 150 Tj [°C] 0.5 1.0 1.5 2.0 2.5 RDS(on) [normalized]
Datasheet 9 Revision 0.1 https://www.infineon.com 2024‑04‑15 Diagram 11: Typ. gate characteristics forward Diagram 12: Typ. gate characteristics reverse I =f( ); open drain; parameter: V T I =f( ); parameter: V T Diagram 13: Typ. transfer characteristics Diagram 14: Typ. transfer gate current characteristic I =f( ); =8V; parameter: I V T I =f( ); =8V; parameter: V V T GS GS j SG SG j D GS DS j G GS DS j VGS [V] 120 150 180IGS [mA] 55 °C 25 °C 125 °C VSG [V] 120 150ISG [mA] 55 °C 25 °C 125 °C 0 1 2 3 4 5 VGS [V] 40ID [A] 25 °C 125 °C 0 1 2 3 4 5 VGS [V] 20IG [mA] 25 °C 125 °C
Datasheet 10 Revision 0.1 https://www.infineon.com 2024‑04‑15 Diagram 15: Typ. channel reverse characteristics Diagram 16: Typ. channel reverse characteristics I =f( ); =25 °C; parameter: V T V I =f( ); =125 °C; parameter: V T V Diagram 17 Typ. gate charge Diagram 18: Typ. capacitances V =f( ); =2.1 A pulsed; parameter: Q I V C=f( ); =0 VV V S SD j GS S SD j GS GS gate D DD DS GS 0 1 2 3 4 5 6 7 8 VSD [V] 5IS [A]
3.5 V 0 V
VSD [V] 5IS [A] 3.5 V 0 V 1 V 2 V 3 V 4 V 5 V Qgate [nC] 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2VGS [V] 400 V 0 100 200 300 400 500 600 VDS [V] 10 2 10 1 100 101 102 103 C [pF] Ciss Coss Crss
Datasheet 11 Revision 0.1 https://www.infineon.com 2024‑04‑15
5 Test Circuits
Table 8 Reverse Channel Characteristics Test Table 9 Gate current switching waveform Switching times with inductive load Switching times waveform VDS VGS td(on) td(off)tr ton tf toff 10% 90% G SK S D RSS RON ROFF CG G SK S D RSS RON ROFF CG L 400V VDS ID CCCC CCCC Gate current switching waveform IG, avg t IG,pulse IG
Datasheet 12 Revision 0.1 https://www.infineon.com 2024‑04‑15
6 Package Outlines
Figure 1 Outline PG‑TSON‑8, dimensions in mm DIMENSIONSMIN.MAX.MILLIMETERSPG-TSON-8-U03PACKAGE - GROUPNUMBER: LL1 cDAb eE 0.451.100.55D11.27 0.600.802.102.30 D24.204.404.214.41
Datasheet 13 Revision 0.1 https://www.infineon.com 2024‑04‑15
7 Apendix A
IFX CoolGaN GaN 650 V webpageTM IFX CoolGaN GaN 650 V reliability white paperTM IFX CoolGaN GaN 650 V gate driver application noteTM IFX CoolGaN GaN 650 V applications informationTM
Datasheet 14 Revision 0.1 https://www.infineon.com 2024‑04‑15 IGLR65R200D2 Revision 2024‑04‑15, Rev. 0.1 Previous Revision Revision Date Subjects (major changes since last revision) 0.1 2024‑04‑15 Release of target Trademarks All referenced product or service names and trademarks are the property of their respective owners. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: erratum@infineon.com Published by Infineon Technologies AG
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