IGC10408

IM7332 INTERSIL | Alldatasheet

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° . Page 82043 2-24 eo ees olka NMOS ROMs poses Steer vie IM7332 218 BRE OR et, By 1M7364. 2-21 Gate Arrays ek Nee ene ors: : 3 IGC10000 2:28 Pe Re woe ae eres CMOS EPROMs er eewecg TEENS IMe653/4 an ieee ee,

DIGITAL _ a ROMs — Organization Max Access Time i 150 Maxim) We. Pin Package? Temp Ranga? 4096.8 M7332 300 80 + 24 SP c 51928 (M7364 350 1590 24 JP c re EPROMs Max Access Vee Ice Max (rua) log Max (uA) Organization Time ins) wy Operating” ‘Standby No. Pins Package” Temp Range Oe x 4 es) ___t Ne M6653 g 5 8 0 Fa J ut .IM5BA 0 10 % rr) 2 4 ik 512x8 M6654 550 s 6 140 24, J LM (M6648 300 0 12 140 4 J ho) a PERIPHERAL 18048 Poripheral . : >. _wwe2c43 — M08 1/0 Exponder Package and Temperature Key . —_ F-Flatpack ‘G—Commercial, 0°0 to -70°C ‘ J—Ceramic Dual In-Line Industrial, ~40°C to +85°C P—Plastic Dual Line M—Military, ~$5°C to + 125°C D-Ceramic Side Brazed (Not Recommended for High Volume) ———_sS OA IN UARTS . “Max. block XTAL art Number Frequency Freduency Vv Supply log Max. (M6402 1.0 MHz - 5.0 4.2 mA . iMBa02A 4.0 MHz - an 9.0 mA 1M6402-1 2.0 MHz _ 5.0 4.9 mA, (M6403 2.48 MHZ 2.46 MH? 5.0 3.7 mA 1m64034 8.0 MHz 6.0 Miz an 13.0 mA . M6404 3.58 Miz 3.58 MH2 50 5.5mA a GATE ARRAYS Input Nand vo art Number Delay Gate Equivalent els Yoo Se cc veot0408 éns 408 a av . (GC10756 Gas 756 ag aay 18011500 ns 1500 62 38V 1612001 60s 2001 70 3V 22 .

ll vi l El SIL Universal Asynchronous FEATURES GENERAL DESCRIPTION . @ Low Power — Less Than 10mW Typ. at 2MHz The IM6402 -and IM6403° are CMOS/LSI UART's for . . interfacing computers or microprocessors to’ asynchronous © Operation Up to 4MHz Ciock (IM6402A) serial data channels. The. receiver converts serial start; data, @ Programmable Word Length, Stop Bits ahd Parity parity and stop bits to parallel data verifying proper code : . . transmission, parity, and stop bits. The transmitter converts ® Automatic Data Formatting and Status Generation parallel data into serial form and automatically adds start, 2? © Compatible with Industry Standard UART’s Parity, and stop bits, . (M6402) Thetdata word length can be 5, 6, 7-or 8 bits. Parity maybe odd . 7 a 1 ‘or even, and parity checking and generation can be:inhibited. bd meager with External Crystal The stop bits may be one or two (or one and one-half when transmitting 5 bit code). Serial data format is shown in @ Operating Voltage — Figure 6. 1M6402-1/03-1; 5V The IM6402 and IM6403 can be uséd in a wide: range of 7 IM6402A/03A: 4-11V applications ‘including modems, printers, peripherals. and IM6402/03: 5V remote data acquisition .systems. CMOS/LSI technology permits clock frequencies up to 4,0MHz (250K Baud), an PIN CONFIGURATION (outline dwg DL; PL) | improvement of 10:to 1 over previous PMOS UART designs. ec Sh Power requirements, by comparison, aré reduced from Sd sapere 670mW to 10mW. Status logic increases flexibility and a simplifies the user interface. ° weuds ssbar TABLE 1 The (M6402 differs from the IM6403 in the use of five device foneds —ssfasens [EIN [imeaaa [wiesos wherau | imewy weexr tox]. | pins as indicated in Table 1 and Figure 1. Seeds Ses. [2 [awe | owes corer} oidaa Const memdio brane | [ae | xa | eanicactinast - geredry —aeBrens | 49 brisur| abaysAcive | aways Aen ORDERING INFORMATION mez BE rene | 22 frst] Amys actin | Atv Active s ) mdi Bre Leo} rac | “tan xD [_omoer cons [ imeaczsioes | mmcwczansa | mserzoa | sod Brno Sade | PRE. MILITARY TEMP. | iMGso2voasMDL | WescaOsaMDL | _—~__} Ri] 20 zpms ‘MILITARY TEMP. | _1M6402-1/03-7 (M6402103-AMDL | =| cnet wirw ae MDLesse eae ° FUNCTIONAL BLOCK DIAGRAM rue yp yy yom ; me somes i | . _ mgm | ft | imine wee | snc te] coda. | i i i z ied cust sas tn _——EE : i are] scewver ee OT) see 1] mays Cd tose | | ‘AND : ORR cONTROL ! | ‘Stop PARITY i “ SIL Caran] 1 i ee Se ee re [es ene. seen st eee? mane wise) - 1 Vise aa + Tse ote ate M6802 or aay ste GA) . 23 :

FIGURE 1. Functional Difference Between IM6402 and IM6403 UART (6403 has On-Chip 4/11 Stage Divider) be used asa timing source rather than additional circuitry such” divide by 16.

2 Input Voltage Low SR ON A

NOTE 1; Except IM6403 XTAL input pins-(ie. pins 17 and 40). . FIGURE 2. Data input Cycle “FIGURE 3. Control Register Load Cycle FIGURE 4, Status Flag Enable Time

transferred to the receiver buffer register. « a7 2s] TRE ‘BRR: active low}. *OIRFERS BETWSEN 1Mo4D2 AND 146409. Diegram and Figure 4. **FIGURE 5. Pin Configuration *1M6402 only. :** 1M6403 FUNCTIONAL PIN DEFINITION IM6403-XTAL| the receiver data rate. 1 Yoo Positive Power Supply low level. High: 24 (16) Divider ferred to the receiver buffer register.

3 GND | Ground INPUT is clocked into the receiver

4 RRD | A high level on RECEIVER REGISTER

outputs, Word formats less than 8 char- required after power-up.

22 TBRE | A high level on TRANSMITTER BUFFER

7 reré | See Pin 5 — RBRB ready for new data.

8 RBRS —_| See Pin S— RBRE 23 TBRL | A low level on TRANSMITTER BUFFER

9 Rer4 | See Fin 5 — RBRE puts TBRI-TBR8 into the transmitter

12 RBR1 =| See Pin 5 — ARE

13 PE A high level on PARITY ERROR indicates "

| that the received parity does not match of @ character including stop bits. | inhibited, this output is low. REGISTER OUTPUT.

26 TBRi ‘Character data Is loaded into the TRANS- 35 Pr A high level on PARITY INHIBIT inhibits

TBRI-TBRB. For character formats less forces PE output low. med word length. . 1.5 stop bits for a 5 character formatand 2. stop bits for other lengths.

37 CLS2* | These inputs program the CHARACTER

3 TeRe See Pin 26 — TERI 39 EPE* When PI is low, a high level on EVEN

a2 Ter? See Pin 26 — TERI . even parity. A low level selects odd parity.

33 Ti i —tT 7

TABLE 2. Control Word Function

4 L L H H 7 EVEN 2

4 H Lo] H L 8 EVEN 1

4 H L H H 8 EVEN 2

must be reset after power-up. The Master Reset (MR) pin is “@nsparent latch. BUFFER REGISTER onto the bus by using the RECEIVER complete character's stop bit is received. to generate a rising edge to TERL at the point where data is _until the next received stop bit after a DRR is performed. FIGURE 10. 110 Baud Serial Interface for IM6100 System

4096 Bit CMOS

FEATURES GENERAL DESCRIPTION © Organization — IM6653: 1024 x 4 The Intersil IM6653 and IM6B54 are fully decoded 4096 bit Imees4:' 512 x 8 CMOS electrically programmable ROMs (EPROMs) . ; fabricated with Intersil’s advanced CMOS processing : High Speed 770.W Maximum Standby technology. In all static states these devices exhibit the , microwatt power dissipation typical of CMOS. Inputs and — 300ns 10V Access Time for IM6653/54 Al __ three-state outputs are TTL compatible and allow for direct — 450ns 5V Access Time for IM6653/54-11 interface with common system bus structures. On-chip ad- * Single +5V supply operation dress registers and chip select functions simplify system * UVerasable ; interfacing requirements. ° Smehronous operation for low power The IM6653 and IM6654 are specifically designed for pro- issipation " gram development applications where rapid turn-around * Three-state outputs and chip select for easy for program changes is required, The devices may bé eras- system expansion ed by exposing their transparent lids to ultra-violet light, * Full —55°C to + 125°C MIL range devices— and then re-programried. IM6653/54 M, IMG65SA/64A M BLOCK DIAGRAM PIN CONFIGURATION (outline dwg JG/W) Voo PROGRAM Ati 24 Wee: Ayks Ag] 2 231A, . Ayres Ep O Vee a] 3 2A a,c] 4 ans . = ot & As] 5 iye65s 2° E Fa 5 Bel Srgae x a'e[ Yoo E, ADDRESS’ = o 64 x 64 o AC)7 18|-)PROGRAM

4 LATCH u ARRAY 5 AoC] 8 170,

x E ace 16a, p4or Lo Qj10 15K, esceses| 08 at ale GND 12 13a, tT . ote arcs 2615 Vee at]2 2a As] 3 2ME, 4 aps ORDERING INFORMATION , ea re Ae 5 iges547 IF : . M2) 8 5554 919 Vo0 SELECTION/TEMPERATURE RANGE AC7 18(7) PROGRAM

24 IN INDUSTRIAL acts Ho,

| ABSOLUTE MAXIMUM RATINGS : Supply Voltages . Vad ieeeteeeteeeeebescheseeaeeesesecesssesseeeeeetsseaaneneees $8,0V VoC=VoD ss sssseeeeessseeessseeeceeerececectettennaneesceeceees #B0V |, Operating Range Temperature Voltage . NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at ? these or any other conditions above those indicated in the operational sections of the specifica- tions is not implied. Exposure to absolute maximum rating conditions for extended periods . may affect device reliability. DC CHARACTERISTICS TEST CONDITIONS: Voc = Vpp =5V + 10%, Ta = Operating Temperature Range PARAMETER [MN Tmax UNiTs: RaaressPins [a7 [CCV Legical "O° Input Voltage [WP | iY | Input Leakage [| ai zWeVog_ [0 [0 Logieal “1” Outputvottage | Vow@ | low=0 | Voo-007| Logical “1” Output Voltage lon= = 0.2mA | 24 Logical "0" Output Voltage [Vor | om=0 |__| GND +001 v /{_Logical “0” Output Voltage l=2oma [oa Output Leakage GNDsVosVeo_[—19 [10 Standby Suppy Curent | Tones | Vin=Voo_- [P00 as Ico | Vin=Vop [0 Operating Supply Curent fooor | f= twhe [| 7» | ma | Tnput Capacitance [Note 0 J Output Capacitance [eo Note 00 Note 1: These parameters guaranteed but not 100% tested. AC CHARACTERISTICS. TEST CONDITIONS: Voc =Vpp = 5V + 10%, C, =50pf, Ta = Operating Temperature Range [_iessareea_[_Mossarsa1 | TMGESISE PARAMETER syweol [win [wax [MIN [wax | MIN [MAX | acess Tine From E, Texav | _f4s0_| so | | @00 | Output Enable Time TsLav {fate [ao [80 | Output Disable Time TEAOZ |_| 10 | a0} 0 E, Pulse With Positive) TEER [op [ee eo Poles Wath (epative | Address Setup Time TAVEL [| oo TAdcress Hold Time [tedax [eo too | ao Chip Enable Setup Time (6654) Tevet {| of ft of fo Chip Enable Hold Time (6654) TELEX | 80 | | 100 [ | 100 | 212

IM6653A/IM6654A . INTERSIL ABSOLUTE MAXIMUM RATINGS . . Supply Voltages VDDe se eetteeteesenneeettsceseeletteecetseseeteeereesinereneeessef 110V Voc =Vppinssssteetesettesessteeesagtneceerveterteestenstrsescerees HOV Operating Range Temperature : . IRdUSttial so. eeceeecebeeeeereeernseeeeseeeerseesreeses 240°C 10 485°C Voltage NOTE: Stresses above those listed under, Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifica- tions'is not implied. Exposure’ to absolute maximum rating conditions for extended periods ’ may affect device reliabitity. DC CHARACTERISTICS TEST CONDITIONS: Vec=Vpp=4.5V to 10.5V, T, = Operational Temperature Range imeesai54al, AM PARAMETER SYMBOL [ MIN’ [ max”s| UNITS. [Vn ress ins vep=20 Togical “0° Input Voltage es Input Leakage | anbeVnevog | a | 0 a] Logical "1" OutpatVaiage [Von | la=0 | Wego; | Logical "0" Output Voage TV, | tor=0 |_| GNDSODT | Output Leakage GND=Voevog | =10_ [10 4 Standby Supply Coram Toosd [00] a ice a Operating Supply Curent En Input Capacitance a Cutput Gapactance [69 ote 00 J Note 4: Thesé parameters guaranteed but not 100% tested. AC CHARACTERISTICS TEST CONDITIONS: Voc =Vpp = 10V + 5%, C_ = 50pf, Ta = Operating Temperature Range IM6653/54 Al IM6653/54 AM . PARAMETER sympot__ [min [Max [MIN [MAX {UNITS Tewov | fs ao | Output Enable Time a Output Disable Time fenoe ae E, Pulse Width (Positive) TE,RE,L ee ee | E; Pulse Width (Negative) TE, LEW [ Address Setup Time TAVEL [0 | | Address Hold Time Tewak [eof Ghip Enable Setup Time (8B_[——Tewe 0 Chip Enable ld Tine e659) [Tete [6 243

[1823 AoArAg [=| Address Lines O11,1347 Qo; Data Outlines, 6654 Qp-Q3 Data Outlines, 6653 [16 | Program (| — ——'| Programming pulse input [7 [Yoo sd] SO Chip V+ supply, normally tied to Voc” [20 |, «|__| Strobe ine, latches both address lines and, for 6864, Chip enable Ep fa [| Ss | et | Ghip select line, must ‘be low for valid data out Ae = ‘Additional address line for 6659 ° ? zB L Chip enable line, latched by Chip enable E, on 6654 Lf Vee = Output butter +Vv Supply READ CYCLE TIMING READ MODE OPERATION TE,6,3———+} ip a typical READ operation address lines and-chip enable TE(HEM. TELav—e] Ep"are {atched.by the falling edge of chip enable E, (T=0). & Va Valid data appears at the outputs one access time (TELQV) i ml later, provided level-sensitive chip select line S is low voy nana pe <a (1 =3). Data remains valid until either E, or'S returns toa sets EEN vin REEREEREEEEEEREEE high level (T=4), Outputs are then forced toa high-Z state. Tee _——" ‘Address lines and Ep must be'valid one setup time before _ SQ Y, Y yyy (TAVEL), and one hold time after (TELAX), the-falling edge ‘ «:;CWN WWW, stating the road cycle. Before becoming valid, Q out- put lines become active (T = 2). The Q output lines return to : a highZ state one output disable time (TE,HZ) after any Mu rising edge on E, or S. Ys 7|_[>TH02 The program line remains high throughout the'READ cycle. * Gowrpurs: Te ee qf vaun Chip enable line E, must remain high one minimum vy = positive pulse width (TEHEL) before the next cycle can roars d we tt tT TE gin, 1 ——. ++ a “Ay meta oy, sb ont a FUNCTION TABLE eer | e jer | s | a} a [1] 4 |x [x |x| 2 | bewcemacve fo |e |x |v | =z | cyccesecins; appREsses, E, LATCHED” ta). [x | x [|x | 2 | INTeRNAL OPERATIONS ONLY fo 2 [ec {x [ue | x [A | ourputs active uNDER CONTROL OF E, 5 ps fe tx Pe | x Tv | OUTPUTS VALID AFTER ACCESS TIME [aa READ COMPLETE Los fe x Tx [x] 2 | eve ENDS (GAME AS 1)

READ AND PROGRAM CYCLES . eT - Yu 7 TOVPL pe fe | | TPHOX. ° Vo. Vea toy 1 [ereten— ? pe "FN DC CHARACTERISTICS FOR PROGRAMMING OPERATION . TEST CONDITIONS: Vog=Vpp = 8V#5%, Ty= 25°C : PARAMETER symeoL | CONDITIONS | MIN | TYP | MAX | UNITS | Pragani in oad Curent | twos [eo | Programming Pulse Amplitude | Veroa | | 88a [Vee Garent | eg Pr [ Yoo Current To 00 Address Input High Voltage [Vina || Vo 20 Address Input Low Voltage [Wun PTV Data input High Voltage [Mig PS op =20 Data input Low Voltage a Ca AC CHARACTERISTICS FOR PROGRAMMING OPERATION TEST CONDITIONS: Vog = Vp =8V 5%, Ta=25° PARAMETER SYMBOL CONDITIONS [min | TYP | MAX | UNITS Program Pulse Duly ef Data Setup Time FOVPL [Os Data Hold Time TPHDX fT a | Strobe Pulse Width TeweE Address Setup Time TAVE,L fo}; CO Address Hold Time TELEX [100 [| recay pe PROGRAM MODE OPERATION Initially, all 4096 bits of the EPROM are in the logic one _latched by the downward edge on the strobe line (E;). Dur- (output high) state. Selective programming of proper bit _ing valid DATA IN time, the PROGRAM pin is pulsed from locations to “0"s is performed electrically. Vpp to — 40V. This pulse initiates the programming of the device to the levels set on the data outputs. Duty cycle In the PROGRAM mode for all EPROMS, Veg and Vpp are | uts, Dut r ! oo and | limitations are specified from chip heat dissipation con- tied together toa +5V operating supply. High logic levels _limitatic at all of the appropriate chip inputs and outputs must be ietations: PULSE RISE AND FALL TIMES MUST NOT BE set at Vpp~2V minimum. Low logic levels must be set at mS. GND-+.8V maximum. Addressing of the desired location in Intelligent programmer equipment with successive PROGRAM mode is done as in the READ mode. Address READ/PROGRAMIVERIFY sequences, such as the Intersil and data lines are set at the desired logic levels, andPRO- 6920 CMOS EPROM programmer, is recommended. GRAM and chip select (5) pins are set high, The address is 215

PROGRAMMING SYSTEM CHARACTERISTICS ERASING PROCEDURE 1. During programming the power supply should be The IM6653/54 are erased by exposure to high intensity capable of limiting peak instantaneous current to short-wave ultraviolet light at a wavelength of 2537 A. The yoomA. . recommended integrated dose (i.e.,UV intensity x ex- 2, The programming.pin is.driven from Vpp to —40-volts posure time) is 10W seo/om?, The lamps should be used (£2V) by pulses of 20 milliseconds duration, These Without short-wave filters, and the IM6653/54 to be erased pulses should be applied in the sequence shown inthe Should be placed about one inch away from the lamp flow chart. Pulse rise and fall times of 10 microseconds _tubes. For best results it is recommended that the device are recommended. Note that any individual: location remain inactive for 5 minutes after erasure, before : may be programmed at any time. reprogramming. 3. Addresses and data should be presented to the device ‘The erasing effect of UV light is cummulative. Care should within the recommended setup/hold time and ‘high/low be taken to protect EPROMSs from exposure to direct : logic level margins. Both “A” (10V) and non “A” sunlight or florescent iamps radiating UV light in the EPROMS are programmed at Vcc, Von of 5V +5%. * 2000A to 4000A range. 2? 4. Programming is to be done at room temperature, PROGRAMMING FLOW CHART . TOWER Down RiCiners YaeeVOSEOND ro neenopaisfe *rorTace pretiory “TO VERPY ALE : ssrasen atv . : “SELECT : «Beatin , | ecnirs E>O [resovaner J] ant thtion ‘tone Tee 216

IM6653 CMOS EPROMS AS EXTERNAL PROGRAM MEMORY WITH THE IM80C35 +5v GND fajale oF Vee Voo Vss . . a | oser pra zor ZB, Pi3} . i ref +8 oN +5 ono P16 a pre 7 Pund 7 Vee Yoo GND Voc Von 3 GND =” “ rae 8 a 1 Ey = . rake cs zg a 3 =“ a ‘ 2 wmaccas Pallas 2, Ps ? p25} 3h a a Par Es Ey 1 sass e059 INPUT S) pesps——— ae EPROM ee ee ‘PROM e| es ei os rr Des x sna rn Es . i i Vd 8

2 Oem as a

IM6653 CMOS EPROMS AS PROGRAM MEMORY WITH THE IM6100 t e i * T ano . Voc GND & ec GND S: Veco GND 5S ja os a +s GND a ——"": ec) = Rate : lose xe ff fp : ae CI +5 GND +8 GND +5 GND lose our acess a 3 g 3 st (LOE Ha ee —-S e —SSe ee | Fee i i Wt “yi ca rl fas _ “es a TT] LI |] L iors | SS Coasise sta, i | anoronaL won ean INH Ss , 247 :

32,768 BIT (4096 x 8) HMOS ROM FEATURES GENERAL DESCRIPTION * High - mum The {M7332 is a 32,768 bit read-only memory (ROM) . Cae iy ate Maximu required. time crganized 4098 words by 8 bits. The device is fabricated us- * Single +5V supply ing intersil’s HMOS technology to minimize cell area and op- ei ally TTL Compatible timize circult performance. i) Inputs and three-state outputs are TTL compatible and ? : Twop pitted Chip Selects allow for direct interfacing to common bus structures. Two 1 chip select inputs which are programmable to either active ° Industry standard 24 lead pinout high or active low, facilitate ease of memory expansion. The:IM7332 operates over 5V +5% at 75mA with an access time of 300ns. LOGICAL BLOCK DIAGRAM PIN LOGIC SYMBOL . CONFIGURATION as {S_] 7 wo ‘S151 Sila VEC oo ate enone ardi zap vec. ao | ME neconen “Sana aoclz zbas a1 a TI ast]3 2Das AZ Py aa TS} aca 21D SaiSe AS ar wt | ads mo B SiS Ma ° . ads to Bato as = sore wbar ar o core” 8 flas ae “ tet de bes s os ae] adn was ato 1 = sotto cnorfie- __18as att ato = GND ait tS : + seh RSE (outline dugs 36, Pa) | cuir sevecr a eae eee a7 as 0s os as ce at a ORDERING INFORMATION PIN NAMES [rar womser | paccaae | Tewk nance | [unsioe—| aumarusne | ot eo . 2418

ABSOLUTE MAXIMUM RATINGS . : NOTE: Stresses.above those listed under "Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these orany other conditions above those indicated'In the operational sections of the specifications Is not Implied. Exposure to absolute maximum rating conditions for extended perlods*may affect device reliability. . TEST CONDITIONS: Vcc = 5V+ 5%, Ta = 0°C to + 70°C : Limits DESCRIPTION ‘SYMBOL | TEST CONDITIONS [ min. Typ, [MAX | UNIT mutvignvonage | vw | Tae | vee | Input Low Voltage | Vy_[ [08 |_| 08 _| ; Tout = 400nA Output High Voltage Vou. $4/51 = So/S2 = 2.0V/0.8V 7 Tour =2.1mA v Output Low Voitage Vor__| 81/81 = Sp/Sp = 2.0V/0.8V Vout = OV to 525V Output Leakage Current lok | S51 = SofSp = 0.8V/2.0V -10 Ta = 0°G, Data Out Open Operating Supply Current loc Vin = 5.25V, S1/S4 = S/So = 2.0V/0.8V 78 Input Capacitance | Sw [Voc = 50V.vin=20v ff Output Capacitance Voo = 60V,vour= 200 | || ie]? NOTE: 1. Typical values are measured at Voc = 5.0V and Ta = +25°C. 2. Capacitance values are sampled, not 100% tested. : 219 :

IM7332 ' INTERSIL AC CHARACTERISTICS . 7332-45 450 Address Access. Time 7332]. taa TAVQV 300 hip Selst to Low impedance | “te |__Tevox | 0 | |] Chip Select Delay [too [rsvav [00 Chip Deselect Delay [te [ tsxaz 00 Output Hol Time [te [xx a READ CYCLE TIMING ’ y <—— teo Le tat HIGH E tie >| epee tons} a stl sO fea | : Yee AC TEST CONDITIONS VEG eee cece eee eee neceeeeeeeeee eee eees SVE 2.0k0 Th eeccccceesseteseeeeeeesseeeeraeenae O96 t0 70°C 1.4k0 . 1O0pF (NCLUDES SCOPE AND : LT JIG CAPACITANCE} OUTPUT LOAD CIRCUIT . 2:20 ,

65,536 BIT ( ) FEATURES GENERAL DESCRIPTION © High Speed — 350ns Maximum access time The IM7364 is a 65,536 bit read-only memory (ROM) © Completely static ~ no clock required organized 8192 words by 8 bits. The device is fabricated us- © Single +5V supply ing Intersil’s HMOS technology to minimize cell area and © Fully TTL Compatibie optimize 'circuit performance. * Two Programmable Chip Select Inputs: and three-state outputs are TTL compatible and © Three-state outputs allow for direct interfacing to common bus structures. A ? * Industry standard 24 lead pinout chip select input, which is programmable to either active high or active low, facilitates ease of memory expansion. ‘The IM7364 operates over 5V+5% at 90mA with an ac- cess time of 350ns, ~ LOGICAL BLOCK DIAGRAM PIN LOGIC SYMBOL CONFIGURATION aot at : ste : Es vec a RAY ards 24 vce Ao aT neg? a aB at ass Pas a aT} mae pare sa o ane ass aps Aa ae 22]8 yargce 19 F410 as be ad? span As o aoe s7por ar a0 re ood 1806 as be am al ardjio 1sPas a9 bed aed bas ato ne Pa Seeabeh eno fas ant ao————13] az an al ine DATA OUTPUT ir i [earacureur | (outline dwgs JG, PG) es ee « gs ) GeoREbrFEn STS ls a7 as as os a2 oz a: aD ORDERING INFORMATION PIN NAMES PARTNUMBER | PACKAGE | TEMP. RANGE [Ao — Aiz | ADDRESS INPUTS IM7364CPG 24 Pin PLASTIC | _0°C to +70°C [ss | pROGRA IM7364 CJG 24PinCERDIP | O°C to +70°C Si MMABLE CHIP SELECT 2-24

IM7364 ° @INTERSIL ABSOLUTE MAXIMUM RATINGS. NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause perma: nent damage to the device, These are stress ratings only and functional operation of the device at these of any other conditions above those indicated in the Operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extend- ed periods may attect device reltability. DC CHARACTERISTICS TEST CONDITIONS: Voc = 5V + 5%, Ta = O°C to + 70°C LIMITS. DESCRIPTION SYMBOL | TEST CONDITIONS [ min. [twp [ MAX. | Input Low Voltage, 7 a Input Leakage Current Vin = OV to 5.25V {| =10 [oa Tout =—400%A Output High Voltage Vou _| SiS = 20vi0.8v v Tout = 2.1mA Output Low Voltage Vo. | S/S = 20vi08v_ 0.4 Vout = ov to 5.26V Output Leakage Current S/S = 0.8V/2.0V 10 aA Ta = 0°C, Data Out Open Operating Supply Current Vin = 5.25V, S/S-= 2.0V/0.8V mA NOTE: 1. Typical values are measured at Vog = 5.0V and T, = +25°C. 2. Capacitance vatues are sampled, not 100% tested. 222

Access Time 7364 taa TAVQV Chip Select to Low Impedance | tz [| tsvax | 20 [TC Chip Select Delay [to f tavav 20 Chip Deselect Delay [top | tsxaz eo Taxox [20 J ee SSSFSSSSSSSSSSSSSSESESeeSeS READ CYCLE TIMING y l . ~~ be to le tar HIGH E —_ hy F > Zz — ae Zz a AC TEST CONDITIONS Veo TA bese eee e eb cece cence ee eereeseecses OC to 70°C 2.0K : Dour 1AkO. 400pF (INCLUDES SCOPE : To ANDaig = + CAPACITANCE) OUTPUT LOAD CIRCUIT 2:23 .

a aaa” CMOS Input/ Output ere” Expander egy a™ . oa oe FEATURES DESCRIPTION. © 8048/41 compatible /O expander The Intersil |M82C43 is a CMOS input/output expander * CMOS pin-for-pin replacement for standard equivalent to the NMOS 8243. It is designed to provide NMOS 8243 . VO expansion for the CMOS IM80C48 and NMOS 8048 © Low power dissipation — maximum 25mW active families of single-chip microcomputers. 2 }. © Four 4-bit 1/0 ports in 24-pin DIP The 24-pin IM82C48 provides four 4-bit bidirectional I/O i i ports: 8048/41 instructions control bidirectional transfers * Logical AND/OR directly to ports between the 82043 and the 8048 family microcomputers, * Single +5V supply the data contained in the 82C43 ports. LOGICAL BLOCK DIAGRAM" PIN CONFIGURATION aopness Peo} “2b Veo eat] s 22 Pose : east] 4 aPoss vals zee > jmezcas * Best proc CL] 7 18 Prez Decooes res] v7 Bre bY LaTcH PORTS. p22 16 F973 i] rac 10 ashen ror CTY root] 1 14 Ber . i for ono 12 13 evo {| I “| PORT (outline drawings JG, PG) Pros PS | anoioe Lo nur 1 ORDERING INFORMATION Logie JBUFFER| Laren cicurr suFFeR| 2:24

ABSOLUTE MAXIMUM RATINGS . NOTE: Stresses above those listed under Absolute Maximum Ps . are stress ratings only, and functional operation of the device Voltage on Any Pin + operationa! sections of the specifications is not implied. With Respect to Ground. Ground -0.5V to Vcc +0.5V Exposure ‘to absolute maximum rating conditions for Power Dissipation .c.cseeseceeececeseeeereeee TW extended periods. may affect device reliability. D.C. AND OPERATING CHARACTERISTICS Ta = 0°C to 70°C, Veo = 5V +10% [___parameren | _evmmou_[ conomons Twin. Trve.[ wax. | unsrs | Input Low Voltage a OT Input High Voltage Va [vec=as «| 20 | [Veo] [voomss 24 | Vect0 5] Ouiput Low Voltage Ports 47 “Possoma fT oa ov vo. [i= goma TT 08 | Cutout Low Vottge Por 2 Uioztena oe 2? Output High Voltage Ports 4-7 [von | ton=szma Tee TT | ‘Output Voltage Port 2 [Vow | low=tema | 2a TT ma input Leakage Pons 47, PoRaCS PROG | ux | Vwaveotoov [of [io [ua | Supply Current ° ioc WRITE mode, 1e mA . All outputs open, . te= 700ns . ‘Standby Current Ioose Vin=0 or Voc, CS = Veo, uA All outputs open Sum of all le from 16 Outputs 3 mA each pinaverage} | | 80 _| ma _] A.C: CHARACTERISTICS Ta=0°C to 70°C, Voc = 5V #10% * PARAMETER ‘SYMBOL CONDITIONS. [ min. [ Max. | UNITS Code Valid Before:PROG | t —*| 80. pF Load a Code Valid after PROG [te 20 pF Load [eo [| Data Valid Before PROG [| soprtoad | ao | Data Valid After PROG [4 | 20 pF Load [2 | | Floating After PROG [| 2opricag fo 80 | PROG Negative Pulse Width a GB Valid Before/Atter PROG [oe PO Ports 4-7 Valid Aiter PROG [= tro | 100 pF Load [_ [700 _ | Ports 4-7 Valid Before/After PROG [ww | Port 2 Valid After PROG [tec | apr uced 80 | FUNCTIONAL PIN DESCRIPTION _ FUNCTIONAL DESCRIPTION Pin The IM82C43 has four 4-bit 1/O ports, which are Designator Number Function’ _——_==aadddressed as Ports 4 thru 7 by the processor. The PROG 7 Swobeinpul The falingedge of PROG —_ following operations may be performed on these ports: implies valid address and contro! infor- © Transfer accumulator to port (write) ionon P20-P23, wi isi Heer enid gata Pao Pas ® Transfer port to accumulator \\read) * AND accumulator to port & 6 Chip select input. When HIGH; it dis- © OR accumulator to port . ables PROG. thus inhibiting changein aij communication between the microcomputer and ponras 1)” Pour th Uskectonas pon carving 188 82049 occurs over Port 2 (P20-P23) with timing 2cdress and control bits on the falling provided by an output pulse on the PROG pin of the sree er ROG snd 1/0 data on the Processor. Each data transfer consists of two bit rising edge of PROG. nibbles: : . pao-P43 2-3 Fourbitbidirectional /O ports. May be © The first contains the port address and command PS0-P53 17,2123 configured for input, tri-state output to the 82043. This is latched from Port 2 during P60-P63 17-20 (READ mode).or latched output. Data the high-to-low transition of PROG and is P70-P73 4316 on pins P20-23 may be directly written, encoded as shown in the table on page 3. ANDed, of OFied with Previous’ data, The second contains the four bits of data No 32 Cirouit ground potential associated with the instruction. The low-to-high Veo 24 +5 volt supply. transition of PROG indicates the presence of data. : 2:25

Port Address And Command Format input mode (read). The first read of a port, following a mode change from write to read should be ignored; all | p23] p22 | INSTRUCTION | et] p20] ADDRESS] following reads are valid. This is to allow the external CODE CODE driver on the portto settle after the first read instruction

0 Read Oo] Oo] Porta removes the low impedance drive from the 82C43 out-

0 Write o}] 1] Ports put. A read. of any port will leave that port in a high 1 ORLD 1 oO Port 6 impedance state. 1 ANLD 1 1, Port 7 . VO Expansion ite Me . The use of a single 82C43 with an 8048 or 8021 is Write Modes : ; shown in figure 1. If more ports are required, more The device:has three write modes. MOVD P,A directly 2043s can be added as shown in figure 2. Here, the writes new data into the selected ‘port with old data upper nibble of port 2 is used to select one of the being lost; ORLD P,A ORs the. new data-with the old 82C43s. Two lines could have been decoded but that data and writes it to the port; and ANLD P,A ANDsnew —_ would require additional hardware. Assuming that the data with old data and writes it to the selected port. leftmost 82043 chip select is connected to P24, the ? After the designated operation is performed, the data _instructions to select and de-select would be: is latched and directed to-the port. The old data MOV A, #0EFH P24=0 remains latched until the new data is written by the OUTL P2, A Enable 82043 rising edge of PROG. : Read Mode . The device has one read mode. The command and port ‘ . address are latched from port 2 on the high-to-low MO gisable Al transition of the PROG pin. As soon as the read " peration and port address are, decoded, the Power On Initialization : designated port output buffers are disabled and the initial applicaiton of power to the device forces ports 4 input buffers enabled. The read operation is termi- £6 and'7 to the high impedance state, Port 2 will be in nated by the low-to-high transition of the PROG pin. an input state if PROG or CS are high when power is The port selected is switched to the high impedance applied. The first high-to-low transition of PROG causes state while port 2 is returned to the input mode. the device to exit the power-on mode. The power-on Normally a port will be in an output mode {write)'or sequence is initiated’ if Voc drops below one volt. WAVEFORMS noc : tol be tenefeltafe vont OPERATIONS) (mean orsnariow | yo rortsa7 PREVIOUS OUTPUT VALID |) ourrur . he ale cD, te te: . a. creer cowomions; : Yann 2eV i INeUT RISE AD FALL TRS: Sn 1070 8ON) INPUT atu GutPut Tie VOLTAGE REFERENCE LEVELS: O8V AND 20 2-26 .

TYPICAL APPLICATIONS OUTPUT EXPANDER TIMING eas . 2] 12 EXPANDER INTERFACE PROG rn ey A e} Pa a ars cs 2] ow aK 10 ADDRESS (-5ITS) ATA (@ITS) a} soohess : PROG PROG Koz) 10 Note: : oR aeota ‘The 82C43 does not have the same quasi-bidirectional port structure soae Ys 0 8 P1/P2 of the 8048, When a"1” is written to P4-7 of the 82C43 itis fo ‘a "hard 1" (low impedance to+5V) which cannot be pulled tow byan nora param @xternel device. All bits of any port can be switched from output Koo mode to input mode-by executing a dummy read.which leaves the port ina high impedance (no pullup or pulldown) stats. nae 2 USING MULTIPLE 82C43s var os cy a 3 K=> => K=> K=> IL | wo KO | cee KEP] cee KS tea KY 048 rort2K 8 z 1 | ro ee Figure 2 . 227

: CMOS Gate Arrays FEATURES GENERAL DESCRIPTION Complexity from 408 to 1500 An !GC10000 Gate Array is a matrix of identical cells, Equivalent 2-input Gates each containing 3 uncommitted N-P transistor pairs.

7 Large numbers of identical arrays are prefabricated

Mature Silicon Gate CMOS Technology and stockpiled. A particular circuit is constructed from —Low development cost a prefabricated array by specifying the interconnec- —3.3 to 9V nominal power supply range tions among the transistors within and between cells +10% on the final metal layer. Because all except the final —Full CMOS temperature range: — 55°C to metal layer are prefabricated, the cost advantages of +125°C mass production can be realized even for low-volume . —Resistance to latch-up applications. In addition, prefabrication provides a sav- banat ing in both design and manufacturing time; in some and electrostatic discharge cases customers can receive prototype chips in as few @ Extensive Macro Cell Library as 6 weeks after initiation of the project. —Numerous combinational and sequential macros In most cases 1|GC10000 gate arrays are processed —Facilitates 7400 and 4000-based with one mask step (a customized metal mask along designs with a standardized contact mask). For some analog - applications or where more routing flexibility is need- —TTL-or CMOS compatible 0 ed, users have the option of programming the contact —Analog capability mask in addition to the metal mask. : & Fully Integrated CAD Software Support —Highly efficient auto-routing capability Layout fully verified against input logic THE 1GC10000 FAMILY OF GATE ARRAYS —Accurate post-layout simulation with Figure 1 shows a structural representation of an calculated RC delays \\GC10000 Gate Array. Each rectangle in the body of —Automatic test code conversion the matrix represents an array cell; the rectangles WO CELLS al kel bel il eb ll el led == ———— I ARRAY CELLS. fe aS SSSSSoSSSsaaaaaaa=, =| A eS Se b | Se SSS . eee BSS eee Sl 2 | SESE SST al | SSS Se | PSR S| PSS | ol | SSS eee] = SSS [el ie S=SSsSe=s===ee==== im) et oe S2===5=S===aeeeee naam! =| Se eee | es : ; Figure 1. Gate Array Configuration INTERSIL, INC., 10710 N. TANTAU AVE., CUPERTINO, CA 95014 (408) 996-5000 TWX; 910-338-0171 2:28

VO CELLS Designers implement their circuits by selecting and ' interconnecting the macros in the Macro Library, lO cells are used to interface. the. array with external i i O ce listed in Table 2. circuitry. Each I/O cell consists of an array of tran- sistors of varying sizes, and allows construction of normal digital /O interface circuits as well as analog Ves Von. circuitry, of simple to moderate complexity. . Y 2 . W/O cells have these features: H : vt * Protection against electrostatic discharge (ESD) B : : 2ill, * Logic level translation (CMOS-to-TTL and TTL-to- A H 5 . MOS) . : : : * Bonding pad for connecting the cell to its cor- 3 Hy : ? responding package pin 2 @eceveed H : * Ratioed transistors for analog implementation ri : The output drive capability of a single output buffer is 2 . : one TTL load. Applications that require additional : H drive capability can be handled by using multiple VO Ao +3 -Hto cells in parallel. (In a typical application, not, all available VO cells are needed for external conrec- 3 : tions; unused cells will thus usually be available to H 3 . provide added drive capability where needed.) 3, mH . MACROS i H : A macro is a physical implementation of a functional : 3 block and is realized by interconnections among tran- sistors in one or more array cells, For example, the ot 3-0 NOR function is constructed by connecting two 2 2 p-channel transistors in series to Vpp and two 3 3 n-channel transistors in parallel to Vgg, as shown in : 3 the topographical and schematic diagrams, Figures 4 and 5, Figure 5. Schematic Diagram for the 2-Input NOR ia ‘Y b ; Pata Eee =e as . (ia H ae ne ae eee een . a | See Se aa Py fT td ta hs Figure 4, interconnect Pattern for the 2-4nput NOR 2:30 :

Table 2. 1GC10000 MAGRO ‘Library

Table 2. 1GG10000 MACRO Library (continued) sult your Intersil Representative for Suitability fo your design. The 1GC10000 family is: supported by a proprietary ~ other parts of the software through the CADEXEC. into tester format. whose parameters are described in Table 3. The CAD tools are integrated under a supervisory pro- .

Table 3. Best, Typical, and Worst Case Parameters Post-layout simulation: A specialized circuit simulator has been developed at the General Electric. automatic router developed at the General Electric rivers on the net. SILICA router has a Critical Net feature that generation. pattern file to be used in testing the finished device. editing may be done on one of our CALMA worksta- pin grid arrays are provided in multilayer ceramic. venient verification of electrical integrity. each pin count and array size. Table 4. Recommended Package Types

DEVELOPMENT . customer interaction and approval. Figure 6 h - ____ delineates the responsibilities of the customer and of An overview of the gate arfay development process is Intersil, For more information, contact elther your shown in the flow Gnart ot eae 6, During Phase 1 jocal Intersil representative, or Semicustom (Design Translation), most of the responsiblity lies Marketing at the General Electric Microelectronics with the customer, during Phase 3 (Fabrication), with Center, Research Triangle Park, NO, telephone Intersil, In Phase 2 (Design Implementation), most of 949.549.3607. the activities are performed by Intersil, but require ‘CUSTOMER (CREATE SCHEMATIC DIAGRAM; DEFINE PRELIMINARY TEST VECTORS; VERIFY CORRECT FUNCTIONALITY PHASE 1 CUSTOMERIINTERSIL DESIGN TRANSLATE TO IGC10000 CMOS MACROS; TRANSLATION ENCODE IN TEGAS; PERFORM PRE-LAYOUT SIMULATION awrensie [Revisions | : PERFORM PRELIMINARY PLACEMENT ON ARRAY; ‘ RECOMMEND SCHEMATIC CHANGES: WHERE REQUIRED INTERSIL PERFORM FINAL PLACEMENT : ‘AND AUTOMATIC ROUTING CUSTOMER INTERSIL APPROVAL CALCULATE INTERCONNECTION-RELATED DELAYS; . PHASE? PERFORM POST-LAYOUT TEGAS SIMULATION

4 DESIGN IMPLEMENTATION

PROVIDE COMPLETE TEST VECTORS INTERSIL . CREATE PATTERN GENERATOR TAPE INTERSIL PHASE 3 FABRICATE MASKS AND WAFERS; PERFORM WAFER PROBE; FABRICATION ASSEMBLE PACKAGES; TEST; SHIP PROTOTYPES: . Figure 6. Simplitied Flowchart for Gate Array Development 2:34 ‘ .

OPERATING CHARACTERISTICS" ‘ Absolute Maximum Ratings’ (Referenced to Vgs) : ee DC Supply Voltage Vpp =05 to +10.0 v Input Voltage OM =05 to Vpp + 05. v DC Input Current ; 4 , +10 mA Operating Ambient Temperature Range Tr 55 to +125 “co Storage Temperature Range (Ceramic) Tste —65 to +150. °C Storage Temperature Range (Plastic) Tste —40 to +125 °C NOTE 1: Stress ratings only. Functional operation of the device at these or any conditions beyond those indicated as Recom- mended Operating Conditions is not implied, . NOTE 2: Stresses above those listed here May cause permanent damage to the device. Exposure to absolute maximum rating | conditions for extended periods may affect device reliability. Recommended Operating Conditions : DC Supply Voltage Vpp 3.34 0.3V to 9.0+0.9V v Typical Operating Frequency fox 8.0 MHz Operating Ambient Temperature Range’ | ° Ta —55 to + 125 se} NOTE 1: 1GC10000 gate array macros are currently characterized between 0 and 70°C, AC CHARACTERISTICS . Specified for nominal processing = 5V, 27°C. Calculated for a fanout of 1. Array Gell Macros : 2-input NAND D to Output 6 2input NOR D to Output. 6 4-input NAND D to Output 8 4-input NOR D to Output 18 1X inverter . D to Output 5 4X inverter D to Output 4 2-1 AND-OR invert D to Output 9 D flip-flop with reset CK to Output 9 Schmitt trigger Input to Output 18 Up counter with reset CK to Output "1 WO Gell Macros Input feedthrough __ |) Pad to Output ; 1 : Non-inverting Input Buffer Pad to Output 9 Non-inverting Output Buffer D to Pad 10 (15 pF) 19 (50 pF) 235

Vpp = SV +10% [oo | ac Tec Parameter [ai [ar | [Top [ xin [ Mak [Un Quiescent Device | Vj=Vpp or 100 | uA Current Vss Vou | Low Level Output | jlo} <1HA Vv ? Voltage Vou | High Level Output | |Io| = 1A Vpp Vpp Voo v Vit Low Level Input CMOS 15 15] Vv Voltage WO Macro Vin High Level Input. | CMOS 35 35 35 Vv Voltage WO Macro . Vit Low Level Input | TTL v : Voltage WO Macro Vin High Level Input | TTL 2.0 2.0 Vv Voltage WO Macro low? | Output Low* . (Sink Current) Vo=2.5V 3.8 76 3.4 mA Sd Output High (Source Current) Vo=2.5V 1.8 1.8 1.6 mA Input Leakage Vin =0 or #01 +001) +01 +1.0| pA Current Vop : Tristate Output Vo=0or + 1.0 001] +1.0 +10 uA Leakage Current Vpp sec ween || Pe ETI NOTES: . 4. 1GC10000 gate arrays are designed to perform under conditions up to 125°C. Limits reflect temperature range at which the macro library is characterized. 2. Any internal oscillators disabied. 3. Results depend on speciftc output macro used. ‘4, There may be limitations on maximum current when many outputs are simultaneously low. . 2:36

Summary

Universal Asynchronous Receiver Transmitter(UART)

Description