IFD-53010 HP | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 5
Technical content
Features
- Wide Operating Frequency Range: IFD-53010: 0.15 to 5.5 GHz IFD-53110: 0.15 to 3.5 GHz
- Low Phase Noise: -143 dBc/Hz @ 1 kHz Offset
- Output Power: -5 dBm Typ.
- Single Supply Voltage V cc = 5 V or Vee = -5 V
- On-Chip Terminations Provide Good Input and Output VSWRs
- Hermetic Gold-Ceramic Surface Mount Package 100 mil Stripline Package Description Hewlett-Packard's IFD-53010 and IFD-53110 are low phase noise silicon bipolar static digital frequency dividers using two scaled Emitter-Coupled-Logic (ECL) master-slave D flip-flops and buffer amplifiers. They are housed in hermetic high reliability surface mount packages suitable for commercial, industrial, and military applications. Typical applications include stabilized or digitally controlled local oscil- lators for GPS, SATCOM or military receivers, and frequency synthesizers and counters in instrumentation systems. The IFD-53110 is a lower cost selected version of the IFD-53010, and is distinguished by a reduced operating frequency range. The IFD series of frequency dividers is fabricated using Hewlett-Packard's 18 GHz, f ISOSAT™-2 silicon bipolar process which uses nitride self- alignment, submicrometer lithography, trench isolation, ion- implantation, gold metallization and polyimide intermetal dielectric and scratch protection to achieve excellent device uniformity, performance, and reliability. Functional Block Diagram Pin Configuration VEE RF INPUT RF OUTPUT VCC CQ CQ CQ CQ V CC VEE RF INPUT RF OUTPUT 5965-9115E
Symbol Parameter Units Absolute Maximum [1] Vcc - Vee Device Voltage V 8 Pdiss Power Dissipation[2,3] mW 650 P in RF Input Power dBm + 1 5 T j Junction Temperature °C 200 TSTG Storage Temperature °C -65 to +200 Thermal Resistance[2]: θjc = 107°C/W Notes: 1, Operation of this device above any one of these parameters may cause permanent damage. 2. Tcase = 25°C. 3. Derate at 9.3 mW/°C for TC ≥ 130°C. Typical Design Information, TA = 25°C, Z0 = 50 Ω , Vcc - Vee = 5.0 V, Pin = -10 dBm. All values apply to both IFD-53010 and IFD-53110. ftest is 5 GHz for IFD-53010 and 3 GHz for IFD-53110 (unless otherwise noted). Symbol Parameters and Test Conditions Units Value F MIN Minimum Clock Frequency[1] MHz 150 Pin Input Sensitivity f = f test dBm -22 mVpp 50 Pout Output Power f = 0.15 to f test dBm -5 mVpp 355 VSWR Input VSWR f = 0.15 to f test 2.0:1 Output VSWR f = 0.15 to f test 2.5:1 PN SSB Phase Noise f = 3 GHz, 1 kHz offset dBc/Hz -143 f = 5 GHz, 1 kHz offset (IFD-53010 only) -138 Tr Output Rise Time, 20% - 80% f = f test psec 145 Tf Output Fall Time, 20% - 80% f = f test psec 8 5 Note: 1. Minimum clock frequency when driven from a sinusoidal input. Operation to lower frequencies is possible when using input signals with faster rise times, such as occurs in the case of a cascade of two or more IFDs. Guaranteed Electrical Specifications, IFD-53010 and IFD-53110 TA = 25°C, ZO = 50 Ω , Vcc - Vee = 5.0 V Symbol Parameters and Test Conditions Units Min. Typ. Max. IFD-53010: FMAX Maximum Clock Frequency P in = -10 dBm (200 mVpp) GHz 5.5 6.0 IFD-53110: FMAX Maximum Clock Frequency P in = -10 dBm (200 mVpp) GHz 3.5 5.0 ICC IFD-53010 and IFD-53110: Supply Current mA 35 43 50
Graphs apply to both IFD-53010 and IFD-53110 (unless otherwise noted). Figure 8. IFD-53010 Typical Output Response with 5 GHz Input.Figure 7. SSB Phase Noise vs. Offset Frequency, and Input Frequency. Figure 4. Device Current vs. Voltage Figure 6. Output Power Level vs. Input Figure 5. Input and Output VSWR vs. Figure 1. Input Sensitivity vs. Input Figure 3. Input Sensitivity vs. Input Figure 2. Input Sensitivity vs. Input
5 GHz (IFD-53010)
2 TO 4 GHz
Figure 12. Sensitivity Test Configuration, IFD-53010 and IFD-53110.
- DIMENSIONS ARE IN mm (INCHES)
- TOLERANCES: in .xxx = ± .005