IFCM15P60GD INFINEON | Alldatasheet

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Datasheet Please read the Important Notice and Warnings at the end of this document V 2.2 www.infineon.com page 1 of 18 2017-09-06 Control Integrated POwer System (CIPOS™) IFCM15P60GD Datasheet

Datasheet 2 of 18 V 2.2 2017-09-06 Control Integrated POwer System (CIPOS™) IFCM15P60GD Table of contents

Datasheet 3 of 18 V 2.2 2017-09-06 Control Integrated POwer System (CIPOS™) IFCM15P60GD CIPOS™ Control Integrated POwer System Dual In-Line PFC integrated Intelligent Power Module 3ɸ-bridge 600V/15A, Single phase PFC 650V/30A

Features

 Dual In-Line molded module  Lead-free terminal plating; RoHS compliant  Very low thermal resistance due to DCB Inverter  TRENCHSTOP™ IGBT3  Rugged SOI gate driver technology with stability against transient and negative voltage  Allowable negative VS potential up to -11V for signal transmission at VBS=15V  Integrated bootstrap functionality  Over current shutdown  Temperature monitor  Under-voltage lockout at all channels  Low side common emitter  Cross-conduction prevention  All of 6 switches turn off during protection PFC  TRENCHSTOP™ 5  Rapid switching emitter controlled diode Target Applications  Home appliances  Low power motor drives

Description

The CIPOS ™ module family offers the chance for integrating various power and control components to increase reliability, optimize PCB size and system costs. It is designed to control three phase AC motors and permanent magnet motors with single phase PFC in variable speed drives for applications like an air conditioning and low power motor drives. The package concept is specially adapted to power applications, which need good thermal conduction and electrical isolation, but also EMI -save control and overload protection. TRENCHSTOP™ IGBT3 and anti-parallel diodes are combined with an optimized SOI gate driver for excellent electrical performance. System Configuration  3 half bridges with TRENCHSTOP ™ IGBT3 and anti parallel diodes  3ɸ SOI gate driver  Single phase PFC with TRENCHSTOP ™ 5 and Rapid switching emitter controlled diode  Thermistor  Pin-to-heatsink clearance distance typ. 1.6mm

Datasheet 5 of 18 V 2.2 2017-09-06 Control Integrated POwer System (CIPOS™) IFCM15P60GD Pin Assignment Pin Number Pin Name Pin Description

1 VS(U) U-phase high side floating IC supply offset voltage

2 VB(U) U-phase high side floating IC supply voltage

3 VS(V) V-phase high side floating IC supply offset voltage

4 VB(V) V-phase high side floating IC supply voltage

5 VS(W) W-phase high side floating IC supply offset voltage

6 VB(W) W-phase high side floating IC supply voltage

7 HIN(U) U-phase high side gate driver input

8 HIN(V) V-phase high side gate driver input

9 HIN(W) W-phase high side gate driver input

10 LIN(U) U-phase low side gate driver input

11 LIN(V) V-phase low side gate driver input

12 LIN(W) W-phase low side gate driver input

13 VDD Low side control supply

14 VFO Fault output / Temperature monitor

15 ITRIP Over current shutdown input

16 VSS Low side control negative supply

17 N Low side emitter

18 W Motor W-phase output

19 V Motor V-phase output

20 U Motor U-phase output

21 P Positive output voltage / Positive bus input voltage

22 X PFC IGBT collector

23 NX PFC IGBT emitter

24 GX PFC IGBT gate

HIN(U,V,W) and LIN(U,V,W) (Low side and high side control pins, Pin 7 - 12) These pins are positive logic and they are responsible for the control of the integrated IGBT . The Schmitt -trigger input threshold s of them are such to guarantee LSTTL and CMOS compatibility down to 3.3V controller outputs. Pull -down resistor of about 5k is internally provided to pre -bias inputs during supply start -up and a zener clamp is provided for pin protection purposes. Input Schmitt-trigger and noise filter provide beneficial noise rejection to short input pulses. The noise filter suppresses control pulses which are below the filter time tFILIN. The filter acts according to Figure 4. CIPOS UZ=10.5V INPUT NOISE FILTER  k5 Schmitt-Trigger SWITCH LEVEL VIH; VILVSS HINx LINx Figure 3 Input pin structure HIN LIN HO LOlow high tFILIN tFILINa) b) HIN LIN HO LO Figure 4 Input filter timing diagram

Datasheet 6 of 18 V 2.2 2017-09-06 Control Integrated POwer System (CIPOS™) IFCM15P60GD It is recommended for proper work of this product not to provide input pulse-width lower than 1.5us. The integrated gate drive provides additionally a shoot through prevention capability which avoids the simultaneous on-state of two gate drivers of the same leg (i.e. HO1 and LO1, HO2 and LO2, HO3 and LO3). When two inputs of a same leg are activated, only former activated one is activated so that the leg is kept steadily in a safe state. A minimum deadtime insertion of typ ically 380ns is also provided by driver IC, in order to reduce cross - conduction of the external power switches. VFO (Fault-output and NTC, Pin 14) The VFO pin indicates a module failure in case of under voltage at pin VDD or in case of triggered over current detection at ITRIP. A pull -up resistor is externally required to bias the NTC. VFO VSS VDD RON,FLT From ITRIP - Latch From UV detection CIPOS Thermistor Figure 5 Internal circuit at pin VFO The same pin provides direct access to the NTC, which is referenced to VSS. An external pull -up resistor connected to +5V ensures that the resulting voltage can be directly connected to the microcontroller. ITRIP (Over current detection function, Pin 15) CIPOS™ provides an over current detection function by connecting the ITRIP input with the motor current feedback. The ITRIP comparator threshold (typ. 0.47V) is referenced to VSS ground. An input noise filter (typ: tITRIPMIN = 530ns) prevents the driver to detect false over-current events. Over current detection generates a shut down of all outputs of the gate driver after the shutdown propagation delay of typically 1000ns. VDD, VSS (Low side control supply and reference, Pin 13, 16) VDD is the low sid e supply and it provides power both to input logic and to low side output power stage. Input logic is referenced to VSS ground. The under -voltage circuit enables the device to operate at power on when a supply voltage of at least a typical voltage of VDDUV+ = 12.1V is present. The IC shuts down all the gate drivers ’ power outputs, when the V DD supply voltage is below VDDUV- = 10. 4V. This prevents the external power switches from critically low gate voltage levels during on-state and therefore from excessive power dissipation. VB(U,V,W) and VS(U,V,W) (High side supplies, Pin 1 - VB to VS is the high side supply voltage. The high side circuit can float with respect to VSS following the external high side power device emitter voltage. Due to the low power consumption, the floating driver stage is supplied by integrated bootstrap circuit. The under-voltage detection operates with a rising supply threshold of typical VBSUV+ = 12.1V and a falling threshold of VBSUV- = 10.4V. VS(U,V,W) provide a high robustness against negative v oltage in respect of VSS of -50V transiently. This ensures very stable designs even under rough conditions. N (Low side emitter, Pin 17) The low side emitters are available for current measurements. It is recommend ed to keep the connection to pin VSS as short as possible in order to avoid unnecessary inductive voltage drops. W, V, U (High side emitter and low side collector, Pin 18 - 20) These pins are motor U, V, W input pins P (Positive bus input voltage, Pin 21) The high side IGBT s and PFC diode cathode are connected to the bus voltage. It is noted that the bus voltage does not exceed 450V. X, NX, GX (Single boost PFC, Pins 22-24) These pins are emitter, collector and gate of IGBT for single boost PFC.

Datasheet 7 of 18 V 2.2 2017-09-06 Control Integrated POwer System (CIPOS™) IFCM15P60GD Absolute Maximum Ratings (VDD = 15V and TJ = 25° C, if not stated otherwise) Module Section Description Condition Symbol Value Unit min max Storage temperature range Tstg -40 125 °C Isolation test voltage RMS, f = 60Hz, t =1min VISOL 2000 - V Operating case temperature range Refer to Figure 6 TC -40 125 °C Inverter Section Description Condition Symbol Value Unit min max Max. blocking voltage IC = 250µA VCES 600 - V DC link supply voltage of P-N Applied between P-N VPN - 450 V DC link supply voltage (surge) of P-N Applied between P-N VPN(surge) - 500 V Output current TC = 25°C, TJ < 150°C IC -15 15 A Maximum peak output current less than 1ms IC(peak) -30 30 A Short circuit withstand time1 VDC ≤ 400V, TJ = 150°C tSC - 5 µs Power dissipation per IGBT Ptot - 49.8 W Operating junction temperature range TJ -40 150 °C Single IGBT thermal resistance, junction-case RthJC - 2.51 K/W Single diode thermal resistance, junction-case RthJCD - 4.67 K/W Control Section Description Condition Symbol Value Unit min max Module supply voltage VDD -1 20 V High side floating supply voltage (VB vs. VS) VBS -1 20 V Input voltage LIN, HIN, ITRIP VIN VITRIP 10 V Inverter switching frequency fPWM - 20 kHz PFC switching frequency fPWM(PFC) - 60 kHz 1 Allowed number of short circuits: <1000; time between short circuits: > 1s.

Datasheet 8 of 18 V 2.2 2017-09-06 Control Integrated POwer System (CIPOS™) IFCM15P60GD PFC Section (VGE = 15V and TJ = 25° C, if not stated otherwise) Description Condition Symbol Value Unit min max Max. blocking voltage IC = 250µA VCES 650 - V Repetitive peak reverse voltage IR = 250µA VRRM 650 - V Gate-emitter voltage VGE -20 20 V Input RMS current TJ ≤ 150°C, TC = 25°C Ii - 30 A Maximum peak input current TJ ≤ 150°C, TC = 25°C less than 1ms, non- repetitive Ii(peak) - 60 A Power dissipation Ptot - 85.6 W Operating junction temperature range TJ -40 150 °C Single IGBT thermal resistance, junction-case RthJC - 1.46 K/W Single diode thermal resistance, junction-case RthJCD - 2.76 K/W Recommended Operation Conditions All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. Description Symbol Value Unit min typ max DC link supply voltage of P-N VPN 0 - 450 V High side floating supply voltage (VB vs. VS) VBS 13.5 - 18.5 V Low side supply voltage VDD 14.5 16 18.5 V Control supply variation ΔVBS, ΔVDD -1 - 1

1 V/µs

Logic input voltages LIN,HIN,ITRIP VIN VITRIP 0 - 5 5 V Between VSS - N and NX(including surge) VSS -5 - 5 V PFC IGBT gate-emitter voltage VGE 14 - 18 V PFC IGBT external gate parameters RG - 10 - Ω CGE - 4.7 - nF RGE - 10 - kΩ

Datasheet 9 of 18 V 2.2 2017-09-06 Control Integrated POwer System (CIPOS™) IFCM15P60GD Static Parameters Inverter Section (VDD = 15V and TJ = 25° C, if not stated otherwise) Description Condition Symbol Value Unit min typ max Collector-Emitter saturation voltage IC = 10A TJ = 25° C 150° C VCE(sat) 1.55 1.8 2.05 V Emitter-Collector forward voltage IF = 10A TJ = 25° C 150° C VF 1.75 1.8 2.45 V Collector-Emitter leakage current VCE = 600V ICES - - 1 mA Logic "1" input voltage (LIN,HIN) VIH - 2.1 2.5 V Logic "0" input voltage (LIN,HIN) VIL 0.7 0.9 - V ITRIP positive going threshold VIT,TH+ 400 470 540 mV ITRIP input hysteresis VIT,HYS 40 70 - mV VDD and VBS supply under voltage positive going threshold VDDUV+ VBSUV+ 10.8 12.1 13.0 V VDD and VBS supply under voltage negative going threshold VDDUV- VBSUV- 9.5 10.4 11.2 V VDD and VBS supply under voltage lockout hysteresis VDDUVH VBSUVH 1.0 1.7 - V Quiescent VBx supply current (VBx only) HIN = 0V IQBS - 300 500 µA Quiescent VDD supply current (VDD only) LIN = 0V, HINX=5V IQDD - 370 900 µA Input bias current VIN = 5V IIN+ - 1 1.5 mA Input bias current VIN = 0V IIN- - 2 - µA ITRIP input bias current VITRIP = 5V IITRIP+ - 65 150 µA VFO input bias current VFO = 5V, VITRIP = 0V IFO - 60 - µA VFO output voltage IFO = 10mA, VITRIP = 1V VFO - 0.5 - V

Datasheet 10 of 18 V 2.2 2017-09-06 Control Integrated POwer System (CIPOS™) IFCM15P60GD PFC Section (VGE = 15V and TJ = 25° C, if not stated otherwise) Description Condition Symbol Value Unit min typ max Collector-Emitter saturation voltage IC = 30A, TJ = 25° C 150° C VCE(sat) 1.7 2.0 2.3 V Diode forward voltage IF = 30A, TJ = 25° C 150° C VF 1.75 1.65 2.3 V Gate-Emitter threshold voltage IC = 0.3mA, VGE=VCE VGE(th) 3.2 4.0 4.8 V Collector-Emitter leakage current VCE = 650V, VGE = 0V ICES - - 1 mA Gate-Emitter leakage current VCE = 0V, VGE = 20V IGES - - 1 µA Diode reverse leakage current VR = 650V IR - - 1 mA Bootstrap Parameters (TJ = 25° C, if not stated otherwise) Description Condition Symbol Value Unit min typ max Repetitive peak reverse voltage VRRM 600 - - V Bootstrap diode resistance Between VF=4V and VF=5V RBSD - 40 -  Reverse recovery time IF = 0.6A, di/dt=80A/µs trr_BSD - 50 - ns Bootstrap diode forward voltage IF = 0.5mA VF_BSD - 1 - V

Datasheet 11 of 18 V 2.2 2017-09-06 Control Integrated POwer System (CIPOS™) IFCM15P60GD Dynamic Parameters Inverter Section (VDD = 15V and TJ = 25° C, if not stated otherwise) Description Condition Symbol Value Unit min typ max Turn-on propagation delay time VLIN,HIN = 5V, IC = 10A, VDC = 300V ton - 680 - ns Turn-on rise time tr - 30 - ns Turn-on switching time tc(on) - 220 - ns Reverse recovery time trr - 60 - ns Turn-off propagation delay time VLIN,HIN = 0V, IC = 10A, VDC = 300V toff - 950 - ns Turn-off fall time tf - 55 - ns Turn-off switching time tc(off) - 120 - ns Short circuit propagation delay time From VIT,TH+ to 10% ISC tSCP - 1250 - ns Input filter time ITRIP VITRIP = 1V tITRIPmin - 530 - ns Input filter time at LIN, HIN for turn on and off VLIN,HIN = 0V & 5V tFILIN - 290 - ns Fault clear time after ITRIP-fault VITRIP = 1V tFLTCLR 40 - - µs Deadtime between low side and high side DTPWM 1.5 - - µs Deadtime of gate drive circuit DTIC - 380 - ns IGBT turn-on energy (includes reverse recovery of diode) VDC = 300V, IC = 10A TJ = 25° C 150° C Eon 400 490 µJ IGBT turn-off energy VDC = 300V, IC = 10A TJ = 25° C 150° C Eoff 190 290 µJ Diode recovery energy VDC = 300V, IC = 10A TJ = 25° C 150° C Erec µJ

Datasheet 12 of 18 V 2.2 2017-09-06 Control Integrated POwer System (CIPOS™) IFCM15P60GD PFC Section (VGE = 15V and TJ = 25° C, if not stated otherwise) Description Condition Symbol Value Unit min typ max Input capacitance VCE = 25V, VGE = 0V, f = 1MHz Cies - 1800 - pF Output capacitance Coes - 45 - Reverse transfer capacitance Cres - 7 - Gate charge VDC = 520V, IC = 30A, VGE = 15V QG - 70 - nC Turn-on delay time VDC = 400V, IC = 30A, RG = 10Ω, CGE = 4.7nF, RGE = 10kΩ, TJ = 25° C td(on) - 20 - ns Turn-on rise time tr - 45 - ns Turn-off delay time td(off) - 115 - ns Turn-off fall time tf - 30 - ns Reverse recovery time trr - 80 - ns Turn-on energy VDC = 400V, IC = 30A, RG = 10Ω, CGE = 4.7nF, RGE = 10kΩ TJ = 25° C 150° C Eon 835 1025 µJ Turn-off energy VDC = 400V, IC = 30A, RG = 10Ω, CGE = 4.7nF, RGE = 10kΩ TJ = 25° C 150° C Eoff 315 395 µJ Diode recovery energy VDC = 400V, IC = 30A, RG = 10Ω, CGE = 4.7nF, RGE = 10kΩ TJ = 25° C 150° C Erec 170 µJ Figure 6 TC measurement point1 1 Any measurement except for the specified point in figure 6 is not relevant for the temperature verification and brings wrong or different information.

Datasheet 14 of 18 V 2.2 2017-09-06 Control Integrated POwer System (CIPOS™) IFCM15P60GD Circuit of a Typical Application <Signal for protection> VDD line 5 or 3.3V line Current sensing N (17) W (18) U (20) P (21) X (22) NX (23) (2) VB(U) (15) ITRIP (14) VFO (10) LIN(U) (11) LIN(V) (12) LIN(W) (16) VSS (13) VDD (4) VB(V) (6) VB(W) (7) HIN(U) (8) HIN(V) (9) HIN(W) (1) VS(U) (3) VS(V) (5) VS(W) V (19) GX (24) VSS VDD LIN3 LIN2 LIN1 VFO ITRIP LO3 LO2 LO1 HO1 HO2 HO3 VB1 VS1 VB2 VS2 VB3 VS3 HIN3 HIN2 HIN1 RBS1 RBS2 RBS3 PFC gate driver IC AC 3-ph AC Motor Input surge voltage sensing <Signal for protection> Micro Controller #6 #7 #7#8 VDD line RG CGERGE Figure 9 Application circuit Because PFC IGBT inside this product has very high speed switching characteristics, considerable large surge voltage between P and NX terminals and switching noise on signaling path are generated easily. Please pay attention to the below items for optimized application circuit design. 1. Input circuit - To reduce input signal noise by high speed switching, the RIN and CIN filter circuit should be mounted. (100Ω, 1nF) - CIN should be placed as close to VSS pin as possible. 2. Itrip circuit - To prevent protection function errors, CITRIP should be placed as close to Itrip and VSS pins as possible. 3. VFO circuit - VFO output is an open drain output. This signal line should be pulled up to the positive side of the 5V/3.3V logic power supply w ith a proper resistor RPU. It is recommended that RC filter be placed as close to the controller as possible. 4. VB-VS circuit - Capacitor for high side floating supply voltage should be placed as close to VB and VS pins as possible. 5. Snubber capacitor - The wiring between CIPOS™ Mini and snubber capacitor including shunt resistor should be as short as possible. 6. Shunt resistor - Each shunt resistor of SMD type should be used for reducing its stray inductance. 7. Ground pattern - Each ground pattern should be separated at only one point of shunt resistor as short as possible. - Power ground pattern between PFC and Inverter should be connected as short as possible. 8. Anti parallel diode - It’s mandatory to connect anti-parallel diode (2A, voltage rating higher than 650V) to PFC IGBT. 9. Input surge voltage protection circuit - This protection circuit is necessary for PFC IGBT to be protected from excessive surge voltage.

Datasheet 16 of 18 V 2.2 2017-09-06 Control Integrated POwer System (CIPOS™) IFCM15P60GD Package Outline

Datasheet 17 of 18 V 2.2 2017-09-06 Control Integrated POwer System (CIPOS™) IFCM15P60GD

Revision history

Date of release Description of changes V 2.1 Aug. 2017 Package outline update Fig.9 Application circuit V 2.2 Sep. 2017 Maximum operating case temperature, Tc= 125°C

81726 München, Germany

© 2017 Infineon Technologies AG. All Rights Reserved. Do you have a question about this document? Email: erratum@infineon.com Document reference IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”) . With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabiliti es of any kind, including without limitation warranties of non -infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this do cument and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies o ffice (www.infineon.com). Please note that this product is not qualified according to the AEC Q100 or AEC Q101 documents of the Automotive Electronics Council. WARNINGS Due to technical requirements products may contain da ngerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. Edition 2017-09-06 ifx1 Trademarks All referenced product or service names and trademarks are the property of their respective owners.