IDT2305B RENESAS | Alldatasheet
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2305B 3.3V ZERO DELAY CLOCK BUFFER APRIL 2016 2016 Integrated Device Technology, Inc.c COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FEATURES:
- Phase-Lock Loop Clock Distribution
- 10MHz to 133MHz operating frequency
- Distributes one clock input to one bank of five outputs
- Zero Input-Output Delay
- Output Skew < 250ps
- Low jitter <175 ps cycle-to-cycle
- 50ps typical cycle-to-cycle jitter (15pF, 66MHz)
- IDT2305B-1 for Standard Drive
- IDT2305B-1H for High Drive
- No external RC network required
- Operates at 3.3V V DD
- Power down mode
- Available in SOIC and TSSOP packages FUNCTIONAL BLOCK DIAGRAM IDT2305B3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2305B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2305B is an 8-pin version of the IDT2309B. IDT2305B accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates, up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT2305B enters power down. In this mode, the device will draw less than 25 μA, the outputs are tri-stated, and the PLL is not running, resulting in a significant reduction of power. The IDT2305B is characterized for both Industrial and Commercial operation. PLL CLK1 CLK2 CLK3 CLK4 Control LogicREF CLKOUT
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2305B 3.3V ZERO DELAY CLOCK BUFFER PIN CONFIGURATION SOIC/TSSOP TOP VIEW Symbol Rating Max. Unit VDD Supply Voltage Range –0.5 to +4.6 V VI (2) Input Voltage Range (REF) –0.5 to +5.5 V VI Input Voltage Range –0.5 to V (except REF) VDD+0.5 IIK (VI < 0) Input Clamp Current –50 mA IO (VO = 0 to VDD) Continuous Output Current ±50 mA VDD or GND Continuous Current ±100 mA TA = 55°C Maximum Power Dissipation 0.7 W (in still air)(3) TSTG Storage Temperature Range –65 to +150 °C Operating Commercial Temperature 0 to +70 ° C Temperature Range Operating Industrial Temperature -40 to +85 °C Temperature Range NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. NOTES: 1. Weak pull down on all outputs. PIN DESCRIPTION ABSOLUTE MAXIMUM RATINGS(1) APPLICATIONS:
- SDRAM Telecom Datacom PC Motherboards/Workstations Critical Path Delay Designs Pin Name Pin Number Type Functional Description REF 1 IN Input reference clock, 5 Volt tolerant input CLK2(1) 2 Out Output clock CLK1(1) 3 Out Output clock GND 4 Ground Ground CLK3(1) 5 Out Output clock VDD 6 PWR 3.3V Supply CLK4(1) 7 Out Output clock CLKOUT (1) 8 Out Output clock, internal feedback on this pin REF CLK1 CLK2 GND CLKOUT CLK4 VDD CLK3
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2305B 3.3V ZERO DELAY CLOCK BUFFER Symbol Parameter Min. Max. Unit VDD Supply Voltage 3 3.6 V TA Operating Temperature (Ambient Temperature) 0 70 °C CL Load Capacitance < 100MHz — 30 pF Load Capacitance 100MHz - 133MHz — 10 CIN Input Capacitance — 7 pF OPERATING CONDITIONS - COMMERCIAL DC ELECTRICAL CHARACTERISTICS - COMMERCIAL Symbol Parameter Conditions Min. Max. Unit VIL Input LOW Voltage Level — 0.8 V VIH Input HIGH Voltage Level 2 — V IIL Input LOW Current V IN = 0V — 50 μA IIH Input HIGH Current V IN = VDD —1 0 0 μA VOL Output LOW Voltage Standard Drive I OL = 8mA — 0.4 V High Drive I OL = 12mA (-1H) VOH Output HIGH Voltage Standard Drive I OH = -8mA 2.4 — V High Drive I OH = -12mA (-1H) IDD_PD Power Down Current REF = 0MHz — 12 μA IDD Supply Current Unloaded Outputs at 66.66MHz — 32 mA SWITCHING CHARACTERISTICS (2305B-1) - COMMERCIAL (1,2) Symbol Parameter Conditions Min. Typ. Max. Unit t1 Output Frequency 10pF Load 10 — 133 MHz 30pF Load 10 — 100 Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 % t3 Rise Time Measured between 0.8V and 2V — — 2.5 ns t4 Fall Time Measured between 0.8V and 2V — — 2.5 ns t5 Output to Output Skew All outputs equally loaded — — 250 ps t6 Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps t7 Device-to-Device Skew Measured at V DD/2 on the CLKOUT pins of devices — 0 700 ps tJ Cycle-to-Cycle Jitter Measured at 66.66MHz, loaded outputs — 50 175 ps tLOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms NOTES: 1. REF Input has a threshold voltage of V DD/2. 2. All parameters specified with loaded outputs.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2305B 3.3V ZERO DELAY CLOCK BUFFER Symbol Parameter Min. Max. Unit VDD Supply Voltage 3 3.6 V TA Operating Temperature (Ambient Temperature) -40 +85 °C CL Load Capacitance < 100MHz — 30 pF Load Capacitance 100MHz - 133MHz — 10 CIN Input Capacitance — 7 pF OPERATING CONDITIONS - INDUSTRIAL SWITCHING CHARACTERISTICS (2305B-1H) - COMMERCIAL (1,2) Symbol Parameter Conditions Min. Typ. Max. Unit t1 Output Frequency 10pF Load 10 — 133 MHz 30pF Load 10 — 100 Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 % Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT <50MHz 45 50 55 % t3 Rise Time Measured between 0.8V and 2V — — 1.5 ns t4 Fall Time Measured between 0.8V and 2V — — 1.5 ns t5 Output to Output Skew All outputs equally loaded — — 250 ps t6 Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps t7 Device-to-Device Skew Measured at V DD/2 on the CLKOUT pins of devices — 0 700 ps t8 Output Slew Rate Measured between 0.8V and 2V using Test Circuit #2 1 — — V/ns tJ Cycle-to-Cycle Jitter Measured at 66.66MHz, loaded outputs — — 175 ps tLOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms NOTES: 1. REF Input has a threshold voltage of V DD/2. 2. All parameters specified with loaded outputs. DC ELECTRICAL CHARACTERISTICS - INDUSTRIAL Symbol Parameter Conditions Min. Max. Unit VIL Input LOW Voltage Level — 0.8 V VIH Input HIGH Voltage Level 2 — V IIL Input LOW Current V IN = 0V — 50 μA IIH Input HIGH Current V IN = VDD —1 0 0 μA VOL Output LOW Voltage Standard Drive I OL = 8mA — 0.4 V High Drive I OL = 12mA (-1H) VOH Output HIGH Voltage Standard Drive I OH = -8mA 2.4 — V High Drive I OH = -12mA (-1H) IDD_PD Power Down Current REF = 0MHz — 25 μA IDD Supply Current Unloaded Outputs at 66.66MHz — 35 mA
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2305B 3.3V ZERO DELAY CLOCK BUFFER SWITCHING CHARACTERISTICS (2305B-1H) - INDUSTRIAL (1,2) Symbol Parameter Conditions Min. Typ. Max. Unit t1 Output Frequency 10pF Load 10 — 133 MHz 30pF Load 10 — 100 Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 % Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT <50MHz 45 50 55 % t3 Rise Time Measured between 0.8V and 2V — — 1.5 ns t4 Fall Time Measured between 0.8V and 2V — — 1.5 ns t5 Output to Output Skew All outputs equally loaded — — 250 ps t6 Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps t7 Device-to-Device Skew Measured at V DD/2 on the CLKOUT pins of devices — 0 700 ps t8 Output Slew Rate Measured between 0.8V and 2V using Test Circuit #2 1 — — V/ns tJ Cycle-to-Cycle Jitter Measured at 66.66MHz, loaded outputs — — 175 ps tLOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms NOTES: 1. REF Input has a threshold voltage of V DD/2. 2. All parameters specified with loaded outputs. SWITCHING CHARACTERISTICS (2305B-1) - INDUSTRIAL (1,2) Symbol Parameter Conditions Min. Typ. Max. Unit t1 Output Frequency 10pF Load 10 — 133 MHz 30pF Load 10 — 100 Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 % t3 Rise Time Measured between 0.8V and 2V — — 2.5 ns t4 Fall Time Measured between 0.8V and 2V — — 2.5 ns t5 Output to Output Skew All outputs equally loaded — — 250 ps t6 Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps t7 Device-to-Device Skew Measured at V DD/2 on the CLKOUT pins of devices — 0 700 ps tJ Cycle-to-Cycle Jitter Measured at 66.66MHz, loaded outputs — 50 175 ps tLOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms NOTES: 1. REF Input has a threshold voltage of V DD/2. 2. All parameters specified with loaded outputs.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2305B 3.3V ZERO DELAY CLOCK BUFFER REF to CLKA/CLKB Delay (ps) ZERO DELAY AND SKEW CONTROL All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for th e PLL, its relative loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other outputs that can adjust the Input-Output (I/O) Delay. For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive load equal to that on the other outputs in order to obtain true zero I/O Delay. If I/O Delay adjustments are needed, use the Output Load Difference diagram to calculate loading differences between the CLKOUT pin and other outputs. For zero output-to-output skew, all outputs must be loaded equally. REF TO CLKA/CLKB RELAY vs. OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS (pF)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2305B 3.3V ZERO DELAY CLOCK BUFFER All Outputs Rise/Fall Time Input to Output Propagation Delay Device to Device Skew Output to Output SkewDuty Cycle Timing SWITCHING WAVEFORMS Test Circuit 1 (all Parameters Except t8) Test Circuit 2 (t8, Output Slew Rate On -1H Devices) TEST CIRCUITS VDD OUTPUTS VDD GND GND 0.1F 0.1F VDD OUTPUTS 10pF VDD GND GND 0.1F 0.1F 1K 1K CLOAD CLKOUT CLKOUT Output 1.4V 1.4V Output REF VDD/2 Output CLKOUT Device 1 CLKOUT Device 2 VDD/2 VDD/2 VDD/2 1.4V1.4V 1.4V 2V0.8V t3 t4 0.8V 3.3V 2VOutput
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2305B 3.3V ZERO DELAY CLOCK BUFFER TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2305B-1 NOTES: 1. Duty Cycle is taken from typical chip measured at 1.4V. 2. I DD data is calculated from I DD = I CORE + nCVf, where I CORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F); V = Supply Voltage (V); f = Frequency (Hz)) VDD (V) Duty Cycle vs VDD (for 30pf loads over frequency - 3.3V, 25C) 33MHz 66MHz 100MHz Duty Cycle (% VDD (V) Duty Cycle vs VDD (for 10pF loads over frequency - 3.3V, 25C) 33MHz 66MHz 100MHz 20 40 60 80 100 120 140 Frequency (MHz) Duty Cycle vs Frequency (for 30pf loads over temperature - 3.3V) -40C 25C 70C 85C Duty Cycle (% Duty Cycle (% 133MHz 20 40 60 80 100 120 140 Frequency (MHz) Duty Cycle vs Frequency (for 10pF loads over temperature - 3.3V) -40C 25C 70C 85C Duty Cycle (% 02 4 6 8 Number of Loaded Outputs 100 120 140 IDD vs Number of Loaded Outputs (for 30pf loads over frequency - 3.3V, 25C) 33MHz 66MHz 100MHz IDD (m 02 4 6 8 Number of Loaded Outputs 100 120 140 IDD vs Number of Loaded Outputs (for 10pF loads over frequency - 3.3V, 25C) 33MHz 66MHz 100MHz IDD (m
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2305B 3.3V ZERO DELAY CLOCK BUFFER TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2305B-1H NOTES: 1. Duty Cycle is taken from typical chip measured at 1.4V. 2. I DD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F); V = Supply Voltage (V); f = Frequency (Hz)) VDD (V) Duty Cycle vs VDD (for 30pf loads over frequency - 3.3V, 25C) 33MHz 66MHz 100MHz Duty Cycle (% VDD (V) Duty Cycle vs VDD (for 10pF loads over frequency - 3.3V, 25C) 33MHz 66MHz 100MHz 20 40 60 80 100 120 140 Frequency (MHz) Duty Cycle vs Frequency (for 30pf loads over temperature - 3.3V) -40C 25C 70C 85C Duty Cycle (% Duty Cycle (% 133MHz 20 40 60 80 100 120 140 Frequency (MHz) Duty Cycle vs Frequency (for 10pF loads over temperature - 3.3V) -40C 25C 70C 85C Duty Cycle (% 02 4 6 8 Number of Loaded Outputs 100 120 140 IDD vs Number of Loaded Outputs (for 30pf loads over frequency - 3.3V, 25C) 33MHz 66MHz 100MHz IDD (m 02 4 6 8 Number of Loaded Outputs 100 120 140 IDD vs Number of Loaded Outputs (for 10pF loads over frequency - 3.3V, 25C) 33MHz 66MHz 100MHz IDD (m 160160
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2305B 3.3V ZERO DELAY CLOCK BUFFER 150 mil (Narrow Body) SOIC SEATING PLANE SEATING PLANE B A e h x 45°h x 45° α L C INDEX AREA INDEX AREA 121 2 N D E H MIN MAX MIN MAX A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0.33 0.51 .013 .020 C 0.19 0.25 .0075 .0098 D E 3.80 4.00 .1497 .1574 e H 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 L 0.40 1.27 .016 .050 N 0° 8° 0° 8° VARIATIONS MIN MAX MIN MAX 8 4.80 5.00 .1890 .1968 10-0030
0.050 BASIC
COMMON DIMENSIONS COMMON DIMENSIONS Reference Doc.: JEDEC Publication 95, MS-012 150 mil (Narrow Body) SOIC SEE VARIATIONS SEE VARIATIONS N D mm. D (inch) SEE VARIATIONS SEE VARIATIONS
1.27 BASIC
8-Pin SOIC Package Drawing and Dimensions
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2305B 3.3V ZERO DELAY CLOCK BUFFER INDEX AREA INDEX AREA 121 2 N D E1 E α SEATING PLANE SEATING PLANE AA2 e -C-- C - b c L aaa C MIN MAX MIN MAX A -- 1.20 -- .047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 D E E1 4.30 4.50 .169 .177 e L 0.45 0.75 .018 .030 N a 0 °8 °0 °8 ° VARIATIONS MIN MAX MIN MAX 8 2.90 3.10 .114 .122 10-0035 SEE VARIATIONS SEE VARIATIONS
0.65 BASIC
Reference Doc.: JEDEC Publication 95, MO-153 N SEE VARIATIONS SEE VARIATIONS D mm. D (inch) 4.40 mm. Body, 0.65 mm. Pitch TSSOP 6.40 BASIC 0.252 BASIC
0.0256 BASIC
(173 mil) (25.6 mil) SYMBOL 8-Pin TSSOP Package Drawing and Dimensions
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2305B 3.3V ZERO DELAY CLOCK BUFFER
ORDERING INFORMATION
Ordering Code Package Type Operating Range 2305B-1DCG8 (tape and reel) 8-Pin SOIC Commercial 2305B-1DCG 8-Pin SOIC Commercial 2305B-1DCGI8 (tape and reel) 8-Pin SOIC Industrial 2305B-1DCGI 8-Pin SOIC Industrial 2305B-1HDCG8 (tape and reel) 8-Pin SOIC Commercial 2305B-1HDCG 8-Pin SOIC Commercial 2305B-1HDCGI8 (tape and reel) 8-Pin SOIC Industrial 2305B-1HDCGI 8-Pin SOIC Industrial 2305B-1PGG8 (tape and reel) 8-Pin TSSOP Commercial 2305B-1PGG 8-Pin TSSOP Commercial 2305B-1PGGI8 (tape and reel) 8-Pin TSSOP Industrial 2305B-1PGGI 8-Pin TSSOP Industrial IDT XXXXX XX X Package ProcessDevice Type 2305B-1 2305B-1H Zero Delay Clock Buffer High Drive Output DC DCG Small Outline SOIC - Green Blank I Commercial (0 oCt o+ 7 0oC) Industrial (-40oCt o+ 8 5oC) PGG TSSOP - Green MARKING DIAGRAMS IDT2305 B-1DCG YYWW$ IDT2305 B-1DCGI YYWW$ IDT2305 B-1HDCG YYWW$ IDT2305 B-1HDCGI YYWW$ 2305B-1DCG/I 2305B-1HDCG/I 2305B-1PGG/I Notes: 1. "G" denotes Pb-free (green) 2. “YYWW” or "YWW" is the last digit(s) of the year and week that the part was assembled. 3. “I" denotes industrial temperature grade. 4. “$” denotes mark code. 5. "LOT" denotes lot number. YWW$ 05B1G LOT YWW$ 05B1GI LOT
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