IDT1338

IDT1338 IDT | Alldatasheet

Document overview

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PDF pages: 23

Technical content

Features

Real-Time Clock (RTC) counts seconds, minutes, hours, day, date, month, and year with leap-year compensation valid up to 2100
56-Byte battery-backed Non Volatile RAM for data storage
Fast mode I2C Serial interface
Automatic power-fail detect and switch circuitry
Programmable square-wave output
Packaged in 8-pin MSOP , 8-pin SOIC, or 16-pin SOIC (surface-mount package with an integrated crystal)
Industrial temperature range (-40°C to +85°C) Block Diagram VCC GND VBAT SCL SDA Crystal inside package for 16-pin SOIC ONLY 1 Hz/4.096 kHz/ 8.192 kHz/32.768 kHz SQW/OUT Power Control I2C Interface 32.768 kHz Oscillator and Divider Control Logic MUX/ Buffer Clock, Calendar Counter

56 Byte

1 Byte

7 Bytes

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 2 IDT1338 REV J 111009 Pin Assignment (8-pin MSOP/8-pin SOIC) Pin Assignment (16-pin SOIC) Pin Descriptions SCL SQW/OUT GND VCC1

5 SDA

V BAT IDT 1338 161 152 143 134 8 9 SCL VCC NC NC NC NC NC NC NC NC NC NC SDA GNDSQW/OUT V BAT IDT 1338C Pin Number Pin Name Pin Description/Function 8MSOP, 8SOIC 16SOIC 1 — X1 Connections for standard 32.768 kHz quartz cryst al. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 12.5 pF . An external 32.768 kHz oscillator can also drive the IDT1338. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is left floating. 2— X 2 31 4 V BAT Backup Supply Input for Lithium Coin Cell or Other Energy Source. Battery voltage must be held between the minimum and maximum limits for proper operation. Diodes placed in series between the backup source and the VBAT pin may prevent proper operation. If a backup supply is not required, VBAT must be connected to ground. 4 15 GND Connect to ground. 5 16 SDA Serial data input/output. SDA is the input/output pin for the I2C serial interface. It is an open-drain output and requires an external pull-up resistor (2 Kohm typical). 6 1 SCL Serial clock input. SCL is used to synchronize data movement on the serial interface. It is an open-drain output and requires an external pull-up resistor (2 Kohm typical) 7 2 SQW/OUT Square-Wave/Output driver. When enabled and the SQWE bit set to 1, the SQW/OUT pin outputs one of four square-wave frequencies (1 Hz, 4 kHz, 8 kHz, 32 kHz). It is an open drain output and requires an external pull-up resistor (10K ohm typical). Operates when the device is powered with VCC or VBAT. 83 V CC Device power supply. When voltage is applied within specified limits, the device is fully accessible by I2C and data can be written and read. — 4 - 13 NC No connect. These pins are unused and mu st be connected to ground for proper operation.

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 3 IDT1338 REV J 111009 Typical Operating Circuit Detailed Description The following sections discuss in detail the Oscillator block, Power Control block, Clock/Calendar Register Block and Serial I 2C block. Oscillator Block Selection of the right crystal, correct load capacitance and careful PCB layout are important for a stable crystal oscillator. Due to the optimization for the lowest possible current in the design for these oscillators, losses caused by parasitic currents can have a significant impact on the overall oscillator performance. Extra care needs to be taken to maintain a certain quality and cleanliness of the PCB. Crystal Selection The key parameters when selecting a 32 kHz crystal to work with IDT1338 RTC are:

Recommended Load Capacitance
Crystal Effective Series Resistance (ESR)
Frequency Tolerance Effective Load Capacitance Please see diagram below for effective load capacitance calculation. The effective load capacitance (CL) should match the recommended load capacitance of the crystal in order for the crystal to oscillate at its specified parallel resonant frequency with 0ppm frequency error. In the above figure, X1 and X2 are the crystal pins of our device. Cin1 and Cin2 are the internal capacitors which include the X1 and X2 pin capacitance. Cex1 and Cex2 are the external capacitors that are needed to tune the crystal frequency. Ct1 and Ct2 are the PCB trace capacitances between the crystal and the device pins. CS is the shunt capacitance of the crystal (as specified in the crystal manufacturer's datasheet or measured using a network analyzer). Note: IDT1338CSRI integrates a standard 32.768 kHz crystal in the package and contributes an additional frequency error of 10ppm at nominal VCC (+3.3 V) and TA=+25°C. CPU X1 X2 VCC SQW/OUT VBAT GND SDA SCL CRYSTAL IDT1338 VCC 2k2k VCCVCC 10k

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 4 IDT1338 REV J 111009 ESR (Effective Series Resistance) Choose the crystal with lower ESR. A low ESR helps the crystal to start up and stabilize to the correct output frequency faster compared to high ESR crystals. Frequency Tolerance The frequency tolerance for 32 KHz crystals should be specified at nominal temperature (+25°C) on the crystal manufacturer datasheet. The crystals used with IDT1338 typically have a frequency tolerance of +/-20ppm at +25°C. Specifications for a typical 32kHz crystal used with our device are shown in the table below. PCB Design Consideration

Signal traces between IDT device pins and the crystal must be kept as short as possible. This minimizes parasitic capacitance and sensitivity to crosstalk and EMI. Note that the trace capacitances play a role in the effective crystal load capacitance calculation.
Data lines and frequently switching signal lines should be routed as far away from the crystal connections as possible. Crosstalk from these signals may disturb the oscillator signal.
Reduce the parasitic capacitance between X1 and X2 signals by routing them as far apart as possible.
The oscillation loop current flows between the crystal and the load capacitors. This signal path (crystal to CL1 to CL2 to crystal) should be kept as short as possible and ideally be symmetric. The ground connections for both capacitors should be as close together as possible. Never route the ground connection between the capacitors all around the crystal, because this long ground trace is sensitive to crosstalk and EMI.
To reduce the radiation / coupling from oscillator circuit, an isolated ground island on the GND layer could be made. This ground island can be connected at one point to the GND layer. This helps to keep noise generated by the oscillator circuit locally on this separated island. The ground connections for the load capacitors and the oscillator should be connected to this island. PCB Layout PCB Assembly, Soldering and Cleaning Board-assembly production process and assembly quality can affect the performance of the 32 KHz oscillator. Depending on the flux material used, the soldering process can leave critical residues on the PCB surface. High humidity and fast temperature cycles that cause humidity condensation on the printed circuit board can create process residuals. These process residuals cause the insulation of the sensitive oscillator signal lines towards each other and neighboring signals on the PCB to decrease. High humidity can lead to moisture condensation on the surface of the PCB and, together with process residuals, reduce the surface resistivity of the board. Flux residuals on the board can cause leakage current paths, especially in humid environments. Thorough PCB cleaning is therefore highly recommended in order to achieve maximum performance by removing flux residuals from the board after assembly. In general, reduction of losses in the oscillator circuit leads to better safety margin and reliability. Parameter Symbol Min Typ Max Units Nominal Freq. f O 32.768 kHz Series Resistance ESR 50 k Ω Load Capacitance C L 12.5 pF

data can be written and read when VCC is greater than VPF. tREC (see the “Power-Up/Down Timing” diagram). Table 1. Power Control Table 2. Power-up/down Characteristics

continues to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read. Table 3. RTC and RAM Address Map Note: Bits listed as “0” should always be written and read as 0. oscillator is already running. mode-select bit. When high, the 12-hour mode is selected.

the hours register must be re-initialized to the new format. update of the main registers during a read. Table 4. Control Register (07H) The control register controls the operation of the SQW/OUT pin and provides oscillator status. = 0, the logic level on the SQW/OUT pin is 1 if OUT = 1; it is 0 if OUT = 0. 1) The first time power is applied. 2) The voltage present on VCC and VBAT are insufficient to support oscillation. 3) The CH bit is set to 1, disabling the oscillator. 4) External influences on the crystal (i.e., noise, leakage, etc.). BAT applied. The frequency of the square-wave output depends upon the value of the RS0 and RS1 bits. output has been enabled. The table below lists the square-wave frequencies that can be selected with the RS bits. Table 5. Square Wave Output

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 8 IDT1338 REV J 111009 I2C Serial Data Bus The IDT1338 supports the I2C bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The IDT1338 operates as a slave on the I 2C bus. Within the bus specifications, a standard mode (100 kHz maximum clock rate) and a fast mode (400 kHz maximum clock rate) are defined. The IDT1338 works in both modes. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The following bus protocol has been defined (see the “Data Transfer on I 2C Serial Bus” figure):

Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 9 IDT1338 REV J 111009 Data Transfer on I2C Serial Bus Depending upon the state of the R/W bit, two types of data transfer are possible: 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first. 2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. This is followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. Data is transferred with the most significant bit (MSB) first. The IDT1338 can operate in the following two modes: 1) Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit (see the “Data Write–Slave Receiver Mode” figure). The slave address byte is the first byte received after the START condition is generated by the master. The slave address byte contains the 7-bit IDT1338 address, which is 1101000, followed by the direction bit (R/W ), which is 0 for a write. After receiving and decoding the slave address byte the slave outputs an acknowledge on the SDA line. After the IDT1338 acknowledges the slave address + write bit, the master transmits a register address to the IDT1338. This sets the register pointer on the IDT1338, with the IDT1338 acknowledging the transfer. The master may then transmit zero or more bytes of data, with the IDT1338 acknowledging each byte received. The address pointer increments after each data byte is transferred. The master generates a STOP condition to terminate the data write. 2) Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the IDT1338 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer (see the “Data Read–Slave Transmitter Mode” figure). The slave address byte is the first byte received after the START condition is generated by the master. The slave address byte contains the 7-bit IDT1338 address, which is 1101000, followed by the direction bit (R/W ), which is 1 for a read. After receiving and decoding the slave address byte the slave outputs an acknowledge on the SDA line. The IDT1338 then begins to transmit data starting with the register address pointed to by

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 10 IDT1338 REV J 111009 the register pointer. If the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. The address pointer is incremented after each byte is transferred. The IDT1338 must receive a “not acknowledge” to end a read. Data Write – Slave Receiver Mode Data Read (from current Pointer location) – Slave Transmitter Mode Data Read (Write Pointer, then Read) – Slave Receive and Transmit

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 11 IDT1338 REV J 111009 Handling, PCB Layout, and Assembly The IDT1338 package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but precautions should be taken to ensure that excessive shocks are avioded. Ultarsonic cleaning equipment should be avioded to prevent damage to the crystal. Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. All NC (no connect) pins must be connected to ground. Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020 standard for moisture-sensitive device (MSD) classifications. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the IDT1338. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.Recommended DC Operating Conditions (VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3 V, TA = +25°C, unless otherwise noted.) (Note 1) Item Rating Voltage Range on Any Pin Relative to Ground -0.3 V to +6.0 V Storage Temperature -55 to +125 ° C Soldering Temperature 260 ° C Parameter Symbol Min. Typ. Max. Units Ambient Operating Temperature T A -40 +85 ° C VBAT Input Voltage, Note 2 V BAT 1.3 3.0 3.7 Pull-up Resistor Voltage (SQW/OUT), Note 2 V PU 5.5 V Logic 1, Note 2 V IH 0.7VCC VCC + 0.3 V Logic 0, Note 2 V IL -0.3 +0.3 VCC V Supply Voltage IDT1338-18 VCC VPF 1.8 5.5 V IDT1338-31 V PF 3.3 5.5 Power Fail Voltage IDT1338-18 VPF 1.40 1.62 1.71 V IDT1338-31 2.45 2.7 2.97

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 12 IDT1338 REV J 111009 (VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3 V, TA = +25°C, unless otherwise noted.) (Note 1) (VCC = 0V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VBAT = 3.0 V, TA = +25°C, unless otherwise noted.) (Note 1) Parameter Symbol Conditions Min. Typ. Max. Units Input Leakage I LI Note 3 1 µA I/O Leakage I LO Note 4 1 µA SDA Logic 0 Output I OLSDA VCC > 2 V; VOL = 0.4 V 3.0 mA VCC < 2 V; VOL = 0.2VCC 3.0 SQW/OUT Logic 0 Output I OLSQW VCC > 2 V; VOL = 0.4 V 3.0 mA

1.71 V < VCC < 2 V;

VOL = 0.2VCC 3.0 mA 1.3 V < VCC < 1.71 V; VOL = 0.2VCC 250 µA Active Supply Current (Note 5) I CCA IDT1338-18 75 150 µAIDT1338-31; VCC < 3.63 V 120 200 IDT1338-31; 3.63 V < VCC < 5.5 V 325 Standby Current (Note 6) I CCS IDT1338-18 60 100 µAIDT1338-31; VCC < 3.63 V 85 125 IDT1338-31; 3.63 V < VCC < 5.5 V 200 VBAT Leakage Current (VCC Active) I BATLKG 25 100 nA Parameter Symbol Conditions Min. Typ. Max. Units VBAT Current (OSC ON); VBAT =3.7 V, SQW/OUT OFF IBATOSC1 Note 7 800 1200 nA VBAT Current (OSC ON); VBAT =3.7 V, SQW/OUT ON IBATOSC2 Note 7 1025 1400 nA VBAT Data-Retention Current (OSC OFF); VBAT =3.7 V IBATDAT Note 7 10 100 nA

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 13 IDT1338 REV J 111009 (VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C) (Note 1) WARNING: Negative undershoots below 0.3 V while the device is in battery-backed mode may cause loss of data. Note 1: Limits at -40°C are guaranteed by design and are not production tested. Note 2: All voltages referenced to ground. Note 3: SCL only. Note 4: SDA and SQW/OUT. Note 5: ICCA—SCL clocking at max frequency = 400 kHz. Note 6: Specified with the I2C bus inactive. Parameter Symbol Conditions Min. Typ. Max. Units SCL Clock Frequency f SCL Fast Mode 100 400 kHz Standard Mode 0 100 Bus Free Time Between a STOP and START Condition tBUF Fast Mode 1.3 µs Standard Mode 4.7 Hold Time (Repeated) START Condition, Note 8 tHD:STA Fast Mode 0.6 µs Standard Mode 4.0 Low Period of SCL Clock t LOW Fast Mode 1.3 µs Standard Mode 4.7 High Period of SCL Clock t HIGH Fast Mode 0.6 µs Standard Mode 4.0 Setup Time for a Repeated START Condition tSU:STA Fast Mode 0.6 µs Standard Mode 4.7 Data Hold Time (Notes 9, 10) t HD:DAT Fast Mode 0 0.9 µs Standard Mode 0 Data Setup Time (Note 11) t SU:DAT Fast Mode 100 ns Standard Mode 250 Rise Time of Both SDA and SCL Signals (Note 12) tR Fast Mode 20 + 0.1C B 300 ns Standard Mode 20 + 0.1C B 1000 Fall Time of Both SDA and SCL Signals (Note 12) tF Fast Mode 20 + 0.1C B 300 ns Standard Mode 20 + 0.1C B 300 Setup Time for STOP Condition t SU:STO Fast Mode 0.6 µs Standard Mode 4.0 Capacitive Load for Each Bus Line (Note 12) CB 400 pF I/O Capacitance (SDA, SCL) C I/O Note 13 10 pF Oscillator Stop Flag (OSF) Delay t OSF Note 14 100 ms

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 14 IDT1338 REV J 111009 Note 7: Measured with a 32.768 kHz crystal on X1 and X2. Note 8: After this period, the first clock pulse is generated. Note 9: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 10: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 11: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > to 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t R(MAX) + tSU:DAT = 1000 + 250 = 1250 ns before the SCL line is released. Note 12: CB—total capacitance of one bus line in pF . Note 13: Guaranteed by design. Not production tested. Note 14: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V < VCC < VCCMAX and 1.3 V < VBACKUP < 3.7 V. Timing Diagram

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 15 IDT1338 REV J 111009 Typical Operating Characteristics IBAT vs VBAT (IDT1338-31) 494 534 574 614 654 694 734 VBat (V) Supply current (nA) SQWE=1 SQWE=0 Icc vs Vcc (IDT1338-31) Vcc (V) Supply Current (uA) SCL=400kHz SCL=0Hz IBAT vs Temperature 400 500 600 700 800 - 4 0 - 2 0 0 2 04 06 08 0 Temperature (C) IBAT (nA) SQWE=1 SQWE=0 Oscillator Frequency vs Supply Voltage 32767.750000 32767.800000 32767.850000 32767.900000 32767.950000 Oscillator Supply Voltage (V) Frequency (Hz) Freq

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 16 IDT1338 REV J 111009 Thermal Characteristics for 8MSOP Thermal Characteristics for 8SOIC Thermal Characteristics for 16SOIC Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 95 ° C/W Thermal Resistance Junction to Case θJC 48 ° C/W Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 150 ° C/W θJA 1 m/s air flow 140 ° C/W θJA 3 m/s air flow 120 ° C/W Thermal Resistance Junction to Case θJC 40 ° C/W Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 120 ° C/W θJA 1 m/s air flow 115 ° C/W θJA 3 m/s air flow 105 ° C/W Thermal Resistance Junction to Case θJC 58 ° C/W

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 17 IDT1338 REV J 111009 Marking Diagram (8 MSOP) Marking Diagram (8 SOIC) Notes: 1. ‘#’ is the lot number. 2. ‘$’ is the assembly mark code. 3. YYWW is the last two digits of the year and week that the part was assembled. 4. “G” denotes RoHS compliant package. 5. “I” denotes industrial grade. 6. Bottom marking: country of origin if not USA. Marking Diagram (16 SOIC) 38GI YWW$ IDT1338-31DVGI 18GI YWW$ IDT1338-18DVGI IDT1338 -31DCGI #YYWW$ IDT1338-31DCGI IDT1339 -18DCGI #YYWW$ IDT1338-18DCGI 1 8 916 IDT 1338C-31 SRI #YYWW$ IDT1338C-31SRI 1 8 916 IDT 1338C-18 SRI #YYWW$ IDT1338C-18SRI

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 18 IDT1338 REV J 111009 Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 INDEX AREA 1 2 D E SEATING PLANE A e - C - B .10 (.004) C C L H h x 45 Millimeters Inches Symbol Min Max Min Max A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0 . 3 30 . 5 1. 0 1 3. 0 2 0 C 0.19 0.25 .0075 .0098 D 4.80 5.00 .1890 .1968 E 3.80 4.00 .1497 .1574 e 1.27 BASIC 0.050 BASIC H 5.80 6.20 .2284 .2440 h 0 . 2 50 . 5 0. 0 1 0. 0 2 0 L 0 . 4 01 . 2 7. 0 1 6. 0 5 0 α 0° 8° 0° 8°

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 19 IDT1338 REV J 111009 Package Outline and Package Dimensions (8-pin MSOP, 3.00 mm Body) Package dimensions are kept current with JEDEC Publication No. 95 INDEX AREA 1 2 D E1 E SEATING PLANE A AA e - C - b aaa C c L *For reference only. Controlling dimensions in mm. Millimeters Inches* Symbol Min Max Min Max A- - 1 . 1 0 - - 0 . 0 4 3 A1 0 0.15 0 0.006 A2 0.79 0.97 0.031 0.038 b 0.22 0.38 0.008 0.015 C 0.08 0.23 0.003 0.009 D 3.00 BASIC 0.118 BASIC E 4.90 BASIC 0.193 BASIC E1 3.00 BASIC 0.118 BASIC e 0.65 Basic 0.0256 Basic L 0.40 0.80 0.016 0.032 α 0° 8° 0° 8° aaa - 0.10 - 0.004

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 20 IDT1338 REV J 111009 Package Outline and Package Dimensions (16-pin SOIC, 300 mil Body) Package dimensions are kept current with JEDEC Publication No. 95 INDEX AREA 1 2 D E1 E SEATING PLANE A AA e - C - b aaa C c L *For reference only. Controlling dimensions in mm. Millimeters Inches* Symbol Min Max Min Max A -- 2.65 -- 0.104 A2 2.05 2.55 0.081 0.100 b 0.33 0.51 0.013 0.020 c 0.18 0.32 0.007 0.013 D 10.10 10.50 0.397 0.413 E 10.00 10.65 0.394 0.419 E1 7.40 7.60 0.291 0.299 e 1.27 Basic 0.050 Basic L 0.40 1.27 0.016 0.050 α 0° 8° 0° 8° aaa - 0.10 - 0.004

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 21 IDT1338 REV J 111009

Ordering Information

The IDT1338 packages are RoHS compliant. Packages without the integrated crystal are Pb-free; packages that include the integrated crystal (as designated with a “C” before the dash number) may include lead that is exempt under RoHS requirements. The lead finish is JESD91 category e3. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature 1338-18DVGI see page 17 Tubes 8-pin MSOP -40 to +85 ° C 1338-18DVGI8 Tape and Reel 8-pin MSOP -40 to +85 ° C 1338-18DCGI Tubes 8-pin SOIC -40 to +85 ° C 1338-18DCGI8 Tape and Reel 8-pin SOIC -40 to +85 ° C 1338C-18SRI Tubes 16-pin SOIC -40 to +85 ° C 1338C-18SRI8 Tape and Reel 16-pin SOIC -40 to +85 ° C 1338-31DVGI Tubes 8-pin MSOP -40 to +85 ° C 1338-31DVGI8 Tape and Reel 8-pin MSOP -40 to +85 ° C 1338-31DCGI Tubes 8-pin SOIC -40 to +85 ° C 1338-31DCGI8 Tape and Reel 8-pin SOIC -40 to +85 ° C 1338C-31SRI Tubes 16-pin SOIC -40 to +85 ° C 1338C-31SRI8 Tape and Reel 16-pin SOIC -40 to +85 ° C

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 22 IDT1338 REV J 111009

Revision History

Rev. Originator Date Description of Change A J. Sarma 01/29/08 New device. Preliminary release. B J.Sarma 03/28/08 Added new note to Part Ordering information pertaining to RoHS compliance and Pb-free devices. C J.Sarma 04/03/04 combined -3 and -33 parts to -31 D J.Sarma 05/19/08 The part number for 16pin RoHS complaint part has now changed from IDT1338C-31SOGI to IDT1338C-31SRI and the IDT1338C-18SOGI changed to IDT1338C-18SRI E J.Sarma 10/29/08 F J.Sarma 11/10/08 Updated Block Diagram; Typical Operating Characteristics charts. G J.Sarma 11/13/08 Updated graphs in “Typical Operating Characteristics; added “Typical Operating Circuit” diagram H J.Sarma 11/18/08 Updated graphs in “Typical Operating Characteristics; updated Block Diagram; added “Battery Backed” to device title. I J.Sarma 12/02/08 Updated Typical Operating Characteristics graphs; added marking diagrams. J 11/10/09 Added “Handling, PCB Layout, and Assembly” section.

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Summary

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM

Description