82C284 INTERSIL | Alldatasheet
Document overview
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- PDF pages: 11
Technical content
Features
- Generates System Clock for 80C286 Processors
- Generates System Reset Output from Schmitt Trigger Input - Improved Hysteresis
- Uses Crystal or External Signal for Frequency Source
- Dynamically Switchable between Two Input Frequencies
- Provides LocalREAD Y and MULTIBUS READ Y Synchronization
- Static CMOS Technology
- Single +5V Power Supply
- Available in 18 Lead CerDIP Package
Description
The Intersil 82C284 is a clock generator/driver which provides clock signals for 80C286 processors and support components. It also contains logic to supply READ Y to the CPU from either asynchronous or synchronous sources and synchronous RESET from an asynchronous input with hysteresis. Pinout 82C284 (CERDIP) TOP VIEW Functional Diagram
Ordering Information
PART NUMBER TEMP. RANGE PACKAGE PKG. NO. CD82C284-12 0 oC to +70oC 18 Ld CERDIP F18.3 ID82C284-10 -40 oC to +85oC 18 Ld CERDIP F18.3 ID82C284-12 -40 oC to +85oC 18 Ld CERDIP F18.3
1 VCC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999 MULTIBUS is a patented Intel bus. File Number 2966.1
Pin DescriptionThe following pin function descriptions are for the 82C284 clock generator. PIN SYMBOL NUMBER TYPE DESCRIPTION CLK 10 O SYSTEM CLOCK: the signal used by the processor and support devices which must be synchro- nous with the processor. The frequency of the CLK output has twice the desired internal processor clock frequency. CLK can drive both TTL and CMOS level inputs. C 6 I FREQUENCY/CRYSTAL SELECT: this pin selects the source for the CLK output. When there is a LOW level on this input, the internal crystal oscillator drives CLK. When there is a HIGH level on F/C, the EFI input drives the CLK input. This pin can be dynamically switched, which allows changing the processor CLK frequency while running for low-power operation, etc. X1, X2 7, 8 I CRYSTAL IN: the pin stop which parallel resonant, fundamental mode crystal is attached for the in- ternal oscillator. When F/ C is LOW, the internal oscillator will drive the CLK output at the crystal fre- quency. The crystal frequency must be twice the desired internal processor clock frequency. EFI 5 I EXTERNAL FREQUENCY IN: drives CLK when the F/ C input is HIGH. The EFI input frequency must be twice the desired internal processor clock frequency. PCLK 13 O PERIPHERAL CLOCK: the output which provides a 50% duty cycle clock with one-half the frequen- cy of CLK. PCLK will be in phase with the internal processor clock following the first bus cycle after the processor has been reset. ARD YEN 17 I ASYNCHRONOUS READY ENABLE: an active LOW input which qualifies the ARD Y input. ARD YEN selectsARD Y as the source ofREAD Y for the current bus cycle. Inputs toARD YEN may be applied asynchronously to CLK. Setup and hold times are given to assure a guaranteed response to synchronous outputs. ARD Y 1 I ASYNCHRONOUS READY: an active LOW input used to terminate the current bus cycle. The ARD Y input is qualified byARD YEN. Inputs toARD Y may be applied asynchronously to CLK. Setup and hold times are given to assure a guaranteed response to synchronous outputs. SRD YEN 3 I SYNCHRONOUS READY ENABLE: an active LOW input which qualifies SRD Y.SRD YEN selects SRD Y as the source forREAD Y to the CPU for the current bus cycle. Setup and hold time must be satisfied for proper operation. SRD Y 2 I SYNCHRONOUS READY: an active LOW input used to terminate the current bus cycle. The SRD Y input is qualified by theSRD YEN input. Setup and hold time must be satisfied for proper operation. READ Y 4 O READY: an active LOW output which signals to the processor that the current bus cycle is to be com- pleted. TheSRD Y SRD YEN, ARD Y,ARD YEN, S1,S0, andRES inputs controlREAD Y as explained later in theREAD Y generator section.READ Y is an open drain output requiring an external pull-up resistor. S0,S1 15,16 I STATUS: these inputs prepare the 82C284 for a subsequent bus cycle. S0 andS1 synchronize PCLK to the internal processor clock and control READY. Setup and hold times must be satisfied for proper operation RESET 12 O RESET: an active HIGH output which is derived from the RES input RESET is used to force the sys- tem into an initial state. When RESET is active,READ Y will be active (LOW). RES 11 I RESET IN: an active LOW input which generates the system reset signal (RESET). Signals to RES may be applied asynchronously to CLK. A Schmitt trigger input is provided onRES, so that an RC circuit can be used to provide a time delay. Setup and hold times are given to assure a guaranteed response to synchronous inputs. V CC 18 SYSTEM POWER: The +5V Power Supply Pin. A 0.1 µF capacitor between VCC and GND is recom- mended for decoupling. GND 9 SYSTEM GROUND: 0V 82C284
The 82C284 generates the clock, ready, and reset signals required for 80C286 processors and support components. The 82C284 is packaged in an 18-pin DIP and contains a crystal controlled oscillator, clock generator, peripheral clock generator, MULTIBUS® ready synchronization logic, and system reset generation logic. Clock Generator The CLK output provides the basic timing control for an 80C286 system. CLK has output characteristics sufficient to drive CMOS devices. CLK is generated by either an internal crystal oscillator, or an external source as selected by the C input pin. When F/C is LOW, the crystal oscillator drives the CLK output. When F/C is HIGH, the EFI input drives the CLK output. The F/C pin on the Intersil 82C284 is dynamically switch- able. This allows the CLK frequency to the processor to be changed from one frequency to another in a running system. With this feature, a system can be designed which operates at maximum speed when needed, and then dynamically switched to a lower frequency to implement a low-power mode. The lower frequency can be anything down to, but excluding, DC. The following 3 conditions apply when dynamically switching the F/ C pin (see Figure 1): 1) The CLK is stretched in the low portion of theφ2 phase of its cycle during transition from one CLK frequency to the other (see Waveforms). 2) When switching CLK frequency sources, there is a max- imum transition latency of 2.5 clock cycles of the fre- quency being switched to, from the time CLK freezes low, until CLK restarts at the new frequency (see Wave- forms). 3) The maximum latency from the time F/C is dynamically switched, to the time CLK freezes low, is 4 CLK cycles (see Waveforms). The following steps describe the sequence of events that transpire when F/C is dynamically switched: A) F/ C switched from high (using EFI input) to low (using the crystal input X1 - see Figure 1A). 1) The state of F/C is sampled when both CLK and PCLK are high until a change is detected. 2) On the second following falling edge of PCLK, CLK is frozen low. 3) CLK restarts at the crystal frequency on the rising edge of Xl, after the second falling edge of X1. B) F/C switched from low (using the crystal input Xl) to high (using the EFI input - see Figure 1B). 1) The state of F/C is sampled when both CLK and PCLK are high until a change is detected. 2) On the second following falling edge of PCLK, CLK is frozen low. 3) CLK restarts at the EFI input frequency on the falling edge of EFl after the second rising edge of EFI. FIGURE 1A. F/C SWITCHED FROM HIGH (USING EFI INPUT) TO LOW (USING THE CRYSTAL INPUT X1) φ2φ1φ2φ1φ2φ1 CLK PCLK F/C 82C284
Absolute Maximum Ratings Thermal Information Thermal Resistance θJA (oC/W) θJC (oC/W) oC Operating Conditions Operating Temperature Range CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TA = -40oC to +85oC (ID82C284) SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIL Input LOW Voltage - 0.8 V V CC = 4.5V VIH Input HIGH Voltage 2.2 - V V CC = 5.5V VIHC EFI, F/C Input HIGH Voltage 3.2 - V V CC = 5.5V VIHR RES HIGH Voltage V CC -0.8 - V V CC = 5.5V VHYS RES Input Hysteresis 0.5 - V V CC = 5.5V VOL RESET, PCLK Output LOW Voltage - 0.4 V I OL = 5mA, VCC = 4.5V, Note 2 VOH RESET, PCLK Output HIGH Voltage V CC -0.4 - V I OH = -1mA, VCC = 4.5V, Note 2 VOLR READ Y Output LOW Voltage - 0.4 V I OL = 10mA, VCC = 4.5V, Note 2 VOLC CLK Output LOW Voltage - 0.4 V I OL = 5mA, VCC = 4.5V, Note 2 VOHC CLK Output HIGH Voltage V CC -0.4 - V I OH = -5mA, VCC = 4.5V, Note 2 IIL Input Leakage Current -10 10 µAV IN = VCC or GND, VCC = 5.5V ICCOP Active Power Supply Current - 60 mA 82C284-12 (Note 1) - 48 mA 82C284-10 (Note 1) NOTES: 2. Interchanging of force and sense conditions is permitted. TA = -40oC to +85oC (lD82C284) AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Waveforms, Unless Otherwise Noted. SYMBOL PARAMETER 10MHz 12.5MHz UNIT TEST CONDITIONSMIN MAX MIN MAX t1 EFl LOW Time 20 - 16 - ns At V CC /2 (Note 8) t2 EFI HIGH Time 20 - 20 - ns At V CC /2 (Note 8) 5A Status Setup Time for Status Going Active 20 - 18 - ns 5B Status Setup Time for Status Going Inactive 20 - 16 - ns 82C284
t6 Status Hold Time 1 - 1 - ns t7 F/ C Setup Time 15 - 15 - t8 F/ C Hold Time 15 - 15 - t9 SRD Y orSRD YEN Setup Time 15 - 15 - ns t10 SRD Y orSRD YEN Hold Time 2 - 2 - ns t11 ARD Y orARD YEN Setup Time 5 - 5 - ns (Note 3) t12 ARD Y orARD YEN Hold Time 30 - 25 - ns (Note 3) t13 RES Setup Time 20 - 18 - ns (Notes 3, 7) t14 RES Hold Time 10 - 8 - ns (Notes 3, 7) t16 CLK Period 50 - 40 - t17 CLK LOW Time 12 - 11 - ns (Notes 2, 6) t18 CLK HIGH Time 16 - 13 - ns (Notes 2, 6) t21 READ Y Inactive Delay 5 - 5 - ns At 0.8V (Note 4), Test Condition 2 t22 READ Y Active Delay - 24 - 18 ns At 0.8V (Note 4) t23 PCLK Delay - 20 - 16 ns C L = 75pF, Test Condition 1 t24 RESET Delay - 27 - 26 ns C L = 75pF, Test Condition 3 t25 PCLK LOW Time t16 -10 - t16 -10 - na C L = 75pF (Note 5) t26 PCLK HIGH Time t16 -10 - t16 -10 - ns C L= 75pF (Note 5) NOTES: 2. With the internal crystal oscillator using recommended crystal and capacitive loading; or with the EFI input meeting specifications t1 and t2. The recommended crystal loading for CLK frequencies of 8MHz to 20MHz are 25pF from pin X1 to ground, and 15pF from pin X2 to ground; for CLK frequencies from 20MHz to 25MHz the recommended loading is 15pF from pin X1 to GND. These recommended values are +5pF and include all stray capacitance. Decouple V CC and GND as close to the 82C284 as possible. 3. This is an asynchronous input. This specification is given for testing purposes only, to assure recognition at a specific CLK edge. 4. The pull-up resistor value for theREAD Y pin is 620Ω with the rated 150pF load. 5. t16 refers to any allowable CLK period. 6. When using a crystal with the recommended capacitive loading, CLK output HIGH and LOW times are guaranteed to meet 80C286 re- quirements. 7. Measured from 1.0V on the CLK to 0.8V on theRES waveform forRES waveform forRES active and to 4.2V on theRES waveform for RES inactive. 8. Input test waveform characteristics: VIL = 0V, VlH = 4.5V. TA = -40oC to +85oC (lD82C284) AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Waveforms, Unless Otherwise Noted. SYMBOL PARAMETER 10MHz 12.5MHz UNIT TEST CONDITIONSMIN MAX MIN MAX UNTESTED SPECIFICATIONS SYMBOL PARAMETER 10MHz 12.5MHz UNITS CONDlTIONS (NOTE 1)MIN MAX MIN MAX C IN Input Capacitance - 10 - 10 pF FREQ = 1MHz, All measurements are referenced to device GND, TA = +25oC t15A EFI HIGH to CLK LOW Delay - 30 - 25 ns (Note 2) t15B EFI LOW to CLK HIGH Delay - 35 - 30 ns (Note 3) 82C284
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- This is an asynchronous input. The setup and hold times are required to guarantee the response shown.
FIGURE 12. CLK AS A FUNCTION OF F/C, PCLK, X1, AND EFI DURING DYNAMIC FREQUENCY SWITCHING