ID8080A | DigiCamel IC Datasheet

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DISTINCTIVE CHARACTERISTICS 3 © High-speed version with 1.3usec instruction cyclo © 3.2mA of output drive at 0.4V (two ful TTL loads) | & © Military temperature range operation to 1.5usec © 700mV of high, 400mV of low level noise immunity Hi © lonimplanted, nchannl,sicon-gate MOS technology © 820mW maximimm power dissipation at 5% power | GENERAL DESCRIPTION 8 The 8080A products are complete, general-purpose, single- handled using asynchronous handshaking controls so that chip digital processors. They are fixed instruction set, any speed memory or I/O device is easily accommodated. parallel, 8-bit units fabricated with Advanced N-Channel a Siicon Gate MOS technology. When combined with exter- tha Srsurnmmoy. The si cgitors ar en its lone and nal memory and peripheral devices, powerful microcompu- may be used singly or in pairs for both 8- and 16-bit tor systems are formed. The 8080A may be used to perform ‘ operations. The accumulator forms the primary working a wide variety of operations, ranging from complex arithme- register and is the destination for many of the arit ic tic calculations to character handling to bit control. Several and logic operations. versions are available offering a range of performance options. ‘A general purpose push-down stack is an important part of the processor architecture. The contents of the stack The processor has a 16-bit address bus that may be used reside in R/W memory and the control logic, including a 16- to directly address up to 64K bytes of memory. The memory bit stack pointer, is located on the processor chip. Subrou- may be any combination of read/write and read-only. Data tne call and return instructions automatically use the stack are transferred into of out of the processor on a bi- to store and retrieve the contents of the program counter. directional 8-bit data bus that is separate from the address Push and Pop instructions allow direct use of the stack for lines. The data bus transfers instructions, data and status storing operands, passing parameters and saving the information between system devices. All transfers are machine state. BLOCK DIAGRAM carne ain ae] rr I a + =] | | | | ae }} ee |} ee] | | a a [etiam | saggesce —_ nas mer om ‘80009800 ae | one 70 ater Issue Dato: May 1987

3 CONNECTION DIAGRAM

& IPs 3 wo-—Cfre eH on 3 (on01vn 2 =~ a o> = an oC] 2p} aa oo ——C]s = — a oC sp} 0 os Cc} «TS ” Cl} 2[-}— oc 2f}— Le »f}— 8 esr ef] ap} wos 9 2} voor 1s =] or e—s xf} «0 oe ——] sf}- oom =<» 4 acl" nf}-— neor suc 0 ab—e (00005573 Note: Pin 1 is marked for orientation. 3.168

ORDERING INFORMATION - 8080A 3 AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed > by acombination of: a, Temperature Range 3 b. Package Type 3 ¢. Device Number FE d. Speed Option > e. Optional Processing tL @. OPTIONAL PROCESSING Biank = Standard Processing B= Burnin ¢. SPEED OPTION Blank = 2 MHz -2= 2.6 MHz T1231 MHz ©. DEVICE NUMBER/DESCRIPTION 8080A Bit Microprocessor b. PACKAGE TYPE. P= 40-Pin Plastic DIP (PD 040) D = 40-Pin Ceramic DIP (CD 040) . TEMPERATURE RANGE* Blank = Commercial (0 to +70°C)

1 Industral (-40 to +85°C)

Valid Combinations Valid Combinations [e0e0ans Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations, to check on newly released valid combinations, and to obtain additional data on AMD's standard military grade products. Po SS “This device is also available in Military temperature range. ‘See MOS Microprocessors and Peripherals Handbook (Order #09275A/0) for electrical performance characteristics. 3-169

g ORDERING INFORMATION - Am9080A E ‘AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is < formed by a combination of: a. Device Number < b. Speed Option (if applicable) 3 c, Package Type 3 d, Temperature Range . Optional Processing a1 2 ; @. OPTIONAL PROCESSING Blank = Standard processing B= Burn-in d. TEMPERATURE RANGE* C= Commercial (0 to +70°C) [= Industrial (-40 to +85°C) c, PACKAGE TYPE P= 40-Pin Plastic OIP (PD 040) D=40-Pin Ceramic DIP (CD 040) 'b. SPEED OPTION Blank = 2 MHz <2 25 MHz Ti=31 MHz ‘4. DEVICE NUMBER/DESCRIPTION ‘Amo080A ‘Bit Microprocessor Valid Combinations PC, OC, Valid Combinations list configurations planned to be 008, 08 supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on AMD's standard military grade products. *This device is also available in Military temperature range. ‘See MOS Microprocessors and Peripherals Handbook (Order #09275A/0) for electrical performance characteristics. 3.470

g [ree Tews [ asereviarion [sina wet [ot [ves rons weut | 3 _| Yoo. Voc. Va _| +12V, +5V, -5V Supplies 3 weet [2 [ong [Gos > wer [+ [aeser pest woot ft [wou fos [neu [fer erst [eur [1 | Reapy oureut [16 [Aras | Aaeress_ | output [1 __| INTE Interrupt Enable [oureur| 1 [ow | Oat aus in Conte oureur | [wa | Wee wot oureut | 1 | SN__| Oyo Syeterzaton ourrut Hols Ako [pve [ Names [vo] anerpton 22,18 The Clock inpuis provide basic ting goneraton for all intemal operations. They are non-overlapping two phase, hgh level signals. All othor Inputs to the processor are TTL. compaitie, ‘The Reset input initializes the processor by clearing the program counter, the instruction register, the interrupt RESET tenable tip-top and tha hold acknowledge fp-lop. Tho Resot signal should be active for atleast three clock eriods, Tho ganeral registers are not cioared. The Hold input allows an external sigal to cause the processe to relingush control over the address Ines 3 and tne data bus. Wnon Hold goes activo, th procassor competes Is current operation, activates the HLDA utbut, and puts the 3-state address and data ines no that high-impedance stato. The Holding device can then utlize the addross and data busses without interference. The Ready input aynctronizs the processor with external units. Whon Ready is absent indicating tho external READY operation is not complete, the processor will eniter the Wait state. it will remain in the Wait state until the clock cycle, following the appearance of Ready. The Intorupt input signal provides a mocnariem for extemal devios to modify the instruction flow of the “4 program n progress. Interrupt requesis are Nandiod efficiently withthe vectored interupt procedure and the General purpose stack. inlorupt processing is described in more detail on the next page. 36 0; vo The Data Sus is comprised of 8 bidirectional signal fines for transterring data, instructions and status 10-7, DoO7 information between the processor and all external units. ee re Seed SNe The Sync output indicates the stat of each processor cycle and in presence of processor status information on tho data bus. 7 The Data Bus in output signal indicates thet the bidirectional data bus is in the input mode and incoming data may bo. gatod onto the Data Bus. WaT “The Wail output incicates thal the processor has ortored the Wai Stata and is prepared lo accept a Ready from the current external operation. [a WR] 0] Tre wre output indicates the vality of output on the data bus during a wite operation “The Hold Acknowledge output signals & response toa Hold input. indcates that processor achviy has Boon suspended and the Address and Data Bus signals will enter their high-impedance state. NE Tie intorupt Enable ouput signe’ shows the stalus of he Interrupt enable fip-op, indieting whether or not tho procwssor wit accept inorupts 3471

& | 8080A/Am9080A INSTRUCTION SET During Sync time at the beginning of each instruction cycle, the be te operat format | the instructions executed by the 8080A are variable length _Sroners ine machiee sycte boing onoccted: Pootone forthe | and may be one, two of three bytes long. The length is status bits are: = | determined by the nature of the operation being performed 3 and the addressing mode being used. >lelslalalel:s|o The instruction summary shows the number of successive memory bytes occupied by each instruction, the number of Laka wo ar atehal ast clock cycles required for the execution of the instruction, the binary coding of the first byte of each instruction, the mnemon- STATUS DEFINITION: ic coding used by assemblers and a brief description of each ‘operation. Some branch-type instructions have two execution INTA Interrupt Acknowledge. Occurs in response to an ‘times depending on whether the conditional branch is taken or interrupt input and indicates that the processor will ‘not. Some fields in the binary code are labeled with alphabetic be ready for an interrupt instruction on the data abbreviations. That shown as vw is the address pointer used bus when DBIN goes true. in the one-byte Call instruction (RST). Those shown as ddd or © WO Write or Output indicated when signal is LOW. sss designate destination and source register fields that may When HIGH, @ Read or Input will occur. be filled as follows: STK Stack indicates that the content of the stack 411 A register Pointer is on the address bus. 000 & register HLTA Halt Acknowledge. O10 D eter OUT Output instruction is being executed. one revisor M1 First instruction byte is being fetched. 100 H register INP Input instruction is being executed. 101 L register MEMR = Memory Read operation.

110 Memory

The register diagram shows the internal registers that are INTERRUPT PROCESSING directly available to the programmer. The accumulator is the | primary working register for the processor and is @ specified or When the processor interrupt mechanism is enabled implied operand in many instructions. All |/O operations take «(INTE = 1), interrupt signals from external devices will be place via the accumulator, Registers H, L, D, E, B and C may recognized unless the processor is in the Hold State. In bbe used singly or in the indicated pairs. The H and L pair is the ‘handling an interrupt, the processor will complete the execu- implied address pointer for many instructions. tion of the current instruction, disable further interrupts and ‘The Flag register stores the program status bits used by the with INTA status instead of executing the next a ‘sequential instruction in the interrupted - conditional branch instructions: carry, zero, sign and parity. " Program. The fifth flag bit is the intermediate carry bit. The flags and the The interrupting device should supp accumulator can be stored on or retrieved from the stack with the mrccaeeer dunvg tho nex’ REIY tine efter INTR slate @ single instruction. Bit positions in the flag register when appears, pushed onto the stack (PUSH PSW) are: rlelsla}lalz2]i1]fo ‘Any opcode may be used except XTHL. If the instruction supplied is a single byte instruction, it will be executed. (The Pete Pe fete [ [1 [eve] — Sten oe natcton vied Ro) te nt instruction is two or three bytes long, the next one or two Where S = sign, Z= zero, CY = intermediate carry, processor cycles, as indicated by the DBIN signal, should be P= parity, CY2 = carry. used by the external device to supply the succeeding byte(s) of the interrupt instruction. Note that INTA status from the REGISTER DIAGRAM Processor is not present during these operations. 5 1f the interrupt instruction is not some form of CALL, it is ‘executed normally by the processor except that the Program ACCUMULATOR: 8 Counter is not incremented. The next instruction in the interrupted program is then fetched and executed. Notice that H REGISTER L REGISTER B+8 the interrupt mechanism must be re-enabled by the processor before another interrupt can occur. If the interrupt instruction is some form of CALL, it is executed B REGISTER C REGISTER B48 normally. The Program Counter is stored and control trans- ferred to the interrupt service subroutine. The routine has PROGRAM COUNTER 16 responsibility for saving and restoring the machine state and for re-enabling interrupts if desired. When the interrupt service STACK POINTER 16 is complete, a RETURN instruction will transfer control back to the interrupted program. 3472

Op Code No. of Clock Assembly Instruction Op Code No. of Clock Assembly instruction g ME Sal Site Nome Besrtan MB Eitae Sal Se oman Ben A DATA TRANSFER ARITHMETIC FS O1dddsss 1 5 MOV “Move register to register 10000sss 1 4 ADOr Add register to Acc r=] ortiOsss ft 7 MOVm, 1 Mowe register to memory 1o001sss 1 4 ADC ‘Add with cary register to Acc | > Seyigi2 2} BBN AE Swans Eby seeness: 3B BE EESAG Sate ioorores : tame Eagar tn ae STACK OPERATIONS CONTROL V1010101 1 1 PUSH Push regaters O & E on stack wig? | ot Sas eee) to RR, AS nae eave Toon. 11110000 1 5 RP ‘Return on positive INCREMENT/DECREMENT

ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Commercial (C) Devices 3 Vec. Vpp and Vsg With (VDD) -ssesssessesssessnessecereeereese 12 £5% ‘Stresses above those listed under ABSOLUTE MAXIMUM (MGB) ----esessecseesesseacreeeersvens SV £5% RATINGS may cause permanent device failure. Functionality (V0) -oesseessessseeseessecsseesseeses 12M £5% at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device Operating ranges define those limits between which the reliability. functionality and parameters of the device are guaranteed. DC CHARACTERISTICS over operating ranges unless otherwise specified Description Test Conditions [| _win_[ tye [max _| [ves-t [| Vestoaa [ v_ [90 [voor Jv [vss-t[ | Ves+oa fv _| [as [| voows |v _] lo. = 19mA on al outputs a ye [Vou | Outpet High Voltage |_| ton = - 180A. | 3s7 [fv ‘Avg. Power Supply _ Vet Ts Tey = 48yusec ‘Avg. Power Supply [own [amare | p fet [| |_teaay | Ava. Power Supply Current (Vas) | [ [oor [10 [ma] [iu Tirwst teatage +d Ms < Vv < Vor [0 a vss < Veioce < Yoo re eS ‘Data Bus Leakage in Input Mode Vgs < VIN < Vgg +0.8V vA Ves soe < Vinee Veo Ens 4 ‘Address and Data Bus Leakage Vapor/DATA = Voc WA bid ‘During HOLD VADOR/DATA ™ Vss + 0.45V ev Secon 6 for Thomal Garona Iilmaion

CAPACITANCE (Tq = 25°C, Voc = Von = Vss = OV. Vas =-5V) 1s 3 [Perametere] Description [Test Conditione]| Typ. [Max.| Unite | > [co | Cock Capactance e-imre [7 [as [ | [cn | input Capactance —lurmeneves Pre [6 | 10 | ot | fro [cour | Output Capaciance [Rewned to vss _[ to [2 [ # | ¢ Ss [Sl Se ape oar nee i mnimn or coer OS > 2 al supply / ATa= -0.45%/°C. os 5 7s 7 7 {ienT TEMPERATURE CC} ‘0P001690 Typical Supply Current Yt Temperature, Normalized 21 SWITCHING TEST LOAD CIRCUIT SWITCHING TEST INPUT/OUTPUT WAVEFORM “ 20 [| »> Cc. ‘er c= 1098 a —/ Lo aa on + WF0O7450 0001840 Cy = 100pF CL INCLUDES JIG CAPACITANCE E 3-175

3 [_SWITCHING CHARACTERISTICS over operating rangos uniess otherwise specifed = CHARACTERISTICS over operating ranges unless otherwise specified E [rommare| ont contre | a ip | $ |o48] 20 Tose] 20 [oss 20 [usec | [wy | Giock ise and Fal Time |-o | so [o [2s | 0 J 50 [nsec | z [igi To Pulse Wiatn [eo [fo] [eo | |asec | [azo [Tras] [a5 | Jasoc | fio; | Delay extoge [o [To [To J Ire | [woz [Detay eto p70 [feat [70 | Irsec| [10s | Delay #1 to $2 Leading Edges poof [eo [ro | fnsec | [es [paso wes oa on | Da ae [zo] [so] | ree] [top [Data Output Delay From gg | [200[ [180 [1200 nsec | y ‘Delay From 720 [ee | emacs ae = foro Le] Pel fe [tor OBIN Delay Frome [25 [sao] 2s [190] 26 | 140 [nsec | [toil [Belay tor input Bus to Enter Input Mode | por [ [tor | [toe [nsec | [toss ___[ Data Setup Time During 61 end DBIN, | ER | | tose [Data Setup Time to ¢2 During DBIN | [iso] [rao] [190 | [nsec | [tonTT [Data Hold time From ¢2 During OBIN | fa] [iP Ti [ [nsec | [eT INTE Output Delay From ge | C= 80 [| _[2o0[ [200] [200 [nsec | [tas READY Setup Time During @g | [x20] [0 | [90 [nse | [tus HOLD Setup Time to de iso] [ra0[ [20] Tree | [20[ [roof [100 | Tnsee | [ty | Hold Time From @2 (READY, INT, HOLD) | pet Tot [of [ree | [ro | Delay to Float Ouring Hold (Adoress and Oata Bus) | | [r20][r20] | 120 [nsec | a [tow | Output Data Stable Prior to WR [ie { [rer [Tre | Yrsee | [wo | Output Data Stable From WR | Th CL 100pF: Address, Da [twa [Adress staie From WR) tLe we non pen LE [| [nee | Ta Tres TT 061 [Tree [iif fre [tf [nsec | [=] [=] Ee) se] Notes: (Parenthosis gives -1, -2 specifications, respective- ) Output delay when measured to 3.0V = SPEC » +60ns @ Ci = SPEC, ©) It C= SPEC, add 6ns/pF if CL > + 1. Data input should be enabled with DBIN status. No actor tine ei ‘Sa ieee bus conflict can then occur and data hold time is assured. tp = 50 ns or tor, whichever is less. 4. law * 2tcy ~ tpg - trga - 140 ng (~1:110 ns, -2:130 ns). 2. toy = tos + tga + tye + tge + toe + tigi 2 480 ns 5. tow= ty ~tog tego 170 ns (—1:160 ns, -2:170 ns). (= 1:320 ns, = 2:380 ns). 6. If not HLDA, two = tWa= tog + trge + 10 ns. It HLDA, ‘two = twa = ‘wr: TYPICAL 4 OUTPUT DELAY VS. A CAPACITANCE 7. tur * to9 + tego 50 ns). z +2 8. tWF = tps + to - 10 ns. > f [| [A] 9, Data in must be stable for this period during OBIN ry vy “tency get rat eas rn a 10. Ready signal must be stable for this period during "0 11, Hold signal must be stable for this period during Tz Sia] | || oF Tw when erring hls made, and ated Toy Ta “100 =80 0 +80 +700 Ts and Twx when in hold mode. (External synchro- CAPACITANCE (pf) nization fe not required) (Cacrua. ~ Csrec) 12. Interrupt signal must be stable during this period of ‘oPoote10 the last clock cycle of any instruction in order to be recognized on the following instruction. (External syn- 3. The following are relevant when interfacing the 8080A " " tb dovicos Mavirg Vine 3¥. chronization is not required.) a) Maximum output rise time from .8V to 13. This timing diagram shows timing relationships only; 3.3V = 100ns @ C= SPEC. it does not represent any spacitic machine cycle. 3.176

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& | CLOCK SWITCHING CHARACTERISTICS over operating range unless otherwise specified FE ‘Am9080A-1, | Am9080A-2, | Amo080A, § 8080A-1 ‘8080A-2 8080A

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Product Information

ID8080A specifications and overview.

Summary

8-Bit Microprocessor

Description

8-Bit Microprocessor

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