IBM014400

IBM014400 IBM | Alldatasheet

Document overview

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Technical content

Features

• 1,048,576 word by 4 bit organization + Power Dissipation - Active (max) Standard Power (SP) and Low Power (LP) = Standby Current: TTL Inputs (max) * 1024 Refresh Cycles - 2.0 mA(SP version) - 16 ms Refresh Rate (SP version) - 1.0 mA (LP version) - 128 ms Refresh Rate (LP version) - Standby Current: CMOS Inputs (max) - 1.0 mA (SP version) * High Performance: - 0.15 mA (LP version) fo 20 70] Fast Page Mode [tac [RAS Access Time | ons | 7Ons | + RAS Only, and CAS before RAS Refresh exe [eASAccesstime | a6 | tor | Hidden Refresh i [counn ares esse Tene | | 25 ne [eventing [stone [scone] * SOFRefesh (P version ont) - * Packages: SOJ-26/20 (300mil i [FastPage wo roe Tw | one | a ges: S04 2620 ao

Description

The 1BM014400 is a fast-page dynamic RAM orga- _also refresh all memory locations. Self-Refresh nized 1,048,576 words by 4 bits. The devices are mode is entered by holding RAS low for >100uS fabricated in IBM's 4M-bit Shrink 2 CMOS silicon _ during a CBR cycle. Detection of this long RAS time gate technology. The circuits and process have during a CBR cycle starts an internal oscillator that been designed to provide high performance, low — maintains data integrity without external clocking. power dissipation, and high reliability. The devices _Self-Refresh mode is included as a standard feature operate with either a 5.0V + 0.5V or 3.3V+0.3V for Low Power devices (IBM014400M and power supply and are offered in a plastic 26/20 pin 1BM014400P). Self Refresh operating current is SOJ (300mil) or TSOP (300mil) package. Refresh- < 170A (max) and typically < 100pA. All low power ing may be accomplished by means of a CAS before _ devices support Extended Data Retention of 128ms, RAS refresh cycle (CBR) that internally generates _ eight times (8x) the retention supported by IBM's the refresh address. RAS - only refresh cycles can _ standard power devices. ee Pin Assignments Pin Description A0-AS vod1O 26 1 Vss vor cf 2 25 f 10s | E_output Enable | adg 18 AB ad 10 vba [ves [rou A2g 11 16 A6 A3 C 12 18D AS Vec C13 140 A4 rr anasae - ©1BM Corporation, 1996. All rights reserved. Samp ed ‘Use is further subject to the provisions at the end of this document. Page 1 of 24

18M014400P —_1BM014400B 1M x 410/10 DRAM SS

Ordering Information

[Pantnber “| “S670P [er ctesn] Power Suny] Speed [Package [Nats | teworasons so [sp] ne | so | om | soimiscuzeao | 1 _| | teworsscouto [sp | no | cov | row | soonisovzea0 | 1 | | —teworasnomur-so [sp | no | sav | om | soonnsoszea0 | + | [_teworesconst-7o | sp | no | sav | 70m | soonssovauao | 1 | | teworesoomir-so [up| ves [sav | com | soomusoszan0 | + | | toworaaonwr-zo [ur [ves | sev | rom | soomisovaszo | 1 | —teworessorurzo [up| ves | ssv_| om | soomisovzea0 | 1 | [_—tenoresorus-ro [ur | ves [sav | om | soonnsoszea0 | + | | eworeaowr-ao [uP [ves | sav | ome | oma Tsonaszo | 1 [teworescour 70 [up| ves_| sev | 70m | soon tsoraeao | 1 _| | tewovacorrs ao [up| ves | a5v | etme | oon eoraezo | + | [—ewoveoorrs 70 [ue | ves | sev | 70m | owonieoravzy | 1 | IBM Corporation, 1996 Alighisresened Sg Use is further subject to the provisions at the end of this document. SA14 4219-08 Page 2 of 24

ZL 18M014400_ 1BM014400M 1BM014400B _=1BM014400P. 4M x 4 10/10 DRAM SSS Block Diagram Vss_ Voc voo o1 voz WO3 Data Ir x ee _—— 7 cas Gon a us CAs ce 1 EN Column Address AO “ , a3 ons PEED Pee PETTY A —| AS s “ =]|| jz =

3 Be 1024 x 1024 x4

Row Col. [ne To | wy ee | | in| eg pp Rew pe | snes ne feo | aT rast Page Mode Read [ow ft | row | co | Fea onmin Fast Page bie We ” [| x | Row | [accra [epee | | wm | oo | ome | Fast Page Mode Read-Modiy- | ‘stGvee | t [Hot | Hot | tom | Row | coi | Data Out Datain FaSomnwton te] | |x| ow | mm | tonic fsineateneaws few fe fw ft | ww | co | omen SSS 27H4339, ©IBM Corporation, 1996. All rights reserved. SA14-4219-04 Use is further subject to the provisions at the end of this document. Revised 6/96 Page 3 of 24

1BM014400M —1BM014400 LEE IBMO14400P —_1BM014400B 1Mx 410/40 DRAM ————— SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSssFFFeeee Absolute Maximum Ratings Parameter Rating

5.0 Volt Device

[ee |Powersuppy vous [asm | owes] Vi | [ts losntnoterseate | ower | Sowa | [Too |somerengeate | sero ssw i [Po _|Poweroespaten | tS Y tid eee dA tt 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli- ability. Recommended DC Operating Conditions (T,=0 to 70°C) sym rameter ni as a SuppiyVotage | 45 | so | ss [30 | 33 | a6 | v | 1 | [vn eanonvotse [24 | — | veevas| 20 | — | varosl v | 1 | [ve |rputtowvotage [os | — | o8 | os | - | o | v [1 | a ce a A OL 1. All voltages referenced to Vss=0V. Capacitance (T,=25°C, f=1MHz) [symbol [Parameter [Min [Max [Units | —iNotes | [ts Poputcanesane nase) | | 8] rt a a ee a An a ce a 1. Input capacitance measurements made with rise time shift method withCAS = Vj, to disable output.

25352 1BM014400__1BM014400M 1BMO14400B _1BM014400P 4M x 410/10 DRAM — Sw ane | min | Max. | min. | Max. | Operating Current | -o | er Alia Po Supe Operating Curent }=f# [= {ss | ‘Standby Current (TTL) Seee beeh S0 care | — | 20 | — | 20 | |Average Power Supply Current, RAS Only Mode mA Fast Page Mode Current [so =| — | 6 | | 60 | lcca |Average Power Supply Current, Fast Page Mode | = | mA Standby Curent CHOS [seven |— [+] —) 2 | locs_ |Power Supply Standby Current ma | 78 fcc F wrvesin | — [ow] — [ar | TAS Before RAS Refresh Current [0 | lccs |Average Power Supply Current, CAS Before RAS Mode | = | [= [es | 1,3,4,5 (RAS Gycling, CAS before RAS, tae = teo min) | 0 | - | » | - [7 | Self Refresh Current, LP version only locr Average Power Supply Current during Self Refresh 170 170 | vA | 78 (CBR cycle with RAS > taass (min)) Battery Backup Refresh Current, LP version only Average Power Supply Current during Battery Backup refresh HA | 7,89 (CAS <Viy, WE 2Vin, tras S 1[1Sec, trc=125,1Sec) ‘Standby Current lecg | Standby current with Qutput’s enabled (RAS 2 Vin (min) and AS Vi. (max) Input Leakage Current, any input ly [0 Vins Woc + 1.0V) for 5.0V, or +10 +10 | pA (0.0 < Vin $ (Vcc + 0.3V)) for 3.3V. All Other Pins Not Under Test = OV j Output Leakage Current WA Ot) | (Dour is disabled, 0.0 < Vour < Voc max) Output Level (TTL) Von |Output *H” Level Voltage Vec | 24 | Vec | v (lour = -5MA for 5.0V, oF lour = -2mA for 3.3V) Output Level (TTL) Vo. Output “L” Level Voltage v (lout = +4.2mA for 5.0V, of lout = +2mA for 3.3V) ee ee eee eee ee ee 1. Icer, Ices, loca and Ioog depend on cycle rate. 2. ccs and icc depend on output loading. Specified values are obtained with the output open. 3. Column address can be changed once or less while RAS =V;, and CAS =Viy. 4. AILV/O and other input pins must be < Vi_(max) or >Vy(min), 5. Enables on-chip refresh and address counters. 6. Assumes no resistive loads on /O pins. 8. Allother /O and other inputs at Vy or Viv. 9. 1024 rows at 128s = 128ms. —_SW 27H4339, GIBM Corporation, 1996. All rights reserved. SA14-4219-04 Use is further subject to the provisions at the end of this document. Revised 6/96 Page 5 of 24

1BM014400M —1BM014400 225372 1BM014400P —_1BM014400B 4M x 410/10 DRAM —_——S.s AC Characteristics (T,=0 to +70°C) 1. An initial pause of 100us is required after power-up followed by 8 RAS only refresh cycles or 8CAS before RAS refresh cycles. 2. AC measurements assume ty=5ns. 3. Vix(min) and Vi.(max) are reference levels for measuring timing of input signals. Also, transition times are measured between \\(y and Vj, (or between Vi_ and Vix). 4. In addition to meeting the transition rate specification, all input signals must transit between \\y and Vi, (or between Vi, and Vy) in a monotonic manner. 5. If OE is tied permanently low, Late-Write or Read-Modify-Write operations are not possible. 6. If CAS = Viu(min), data outputs are in high impedance. Read, Write, Read-Modify-Write and Ref. Cycles (Common Parameters) symbol paramete ee “ ed [min [Max | win [ Max | i a [ee fexsrasewian is | ook | | omc nef a a |e fRASHowtine ws Pe Pe a [treason ew Ds p=tsp=pe > [two _Eemoeey Tne ds pp | a |_____[Transion Time (Rise and Fa [3 | | s [0 |e | iar | SSS ee ee ee ee ee | 1. AC measurements assume t=5ns. 2. Vin(min) and Vj(max) are reference levels for measuring timing of input signals. Also, transition times are measured between Ma and Vi, (or between Vy, and Vix). 3. Operation within the tacp(max) limit ensures that tzac(max) can be met. tacp(max) is specified as a reference point only. If rep is greater than the specified tacp(max) limit, then access time is controlled by tac. 4. Operation within the trap(max) limit ensures that frac(max) can be met. trap(max) is specified as a reference point only. If feap is greater than the specified trap(max) limit, then access time is controlled by fa. 5. Either tcop or topp must be satisfied. 6. Either tozc or tpzo must be satisfied. 7. In addition to meeting the transition rate specification, all input signals must transit between Vy and Vy (or between Vj, and Vjy) in a monotonic manner. 18M Corporation, 1996. All rights reserved. eanaeitiagsg Use is furthe toth ions at the end of this document. 14-42 se is further subject to the provisions at the end of this document 144218 04 Page 6 of 24

Se eTe 1BM014400 —_18M014400M 1BM014400B = 1BM014400P 1M x 4 10/10 DRAM a es Write Cycle symbol p J ff [we wns comanavowtne fe | = os = pw | 3] rc |__ ts __ [Pw Setup Tine pe {|= fof - [iw | 2 | [_[ontiostme Sd Ps | ef ee ee ee ee es ee 1. twes. trwo, tewo and tawp are not restrictive operating parameters. trwo, towo, and tawo apply to Read-Modify-Write cycles. If twcs 2 twes(min), the cycle is an Early Write cycle and the data 1/0 pins will remain open circuit (high impedance) throughout the entire cycle. If trwo 2 tawo(min), tewo 2 tewo(min), and tawo 2 tawo(min), the cycle is a Read-Modify-Write cycle and the data /O pins will contain read data from the selected cells. If neither of the above sets of conditions are satisfied, the condition of the data VO pins (at access time) is indeterminate. __ 2. These parameters are referenced to the falling edge ofCAS for Early-Write cycles and to the falling edge of WE for Delayed-Write or Read-Modify-Write cycles. 3. Parameter twp is applicable for a Delayed-Write cycle such as a Read-Write or Read-Modify-Write cycle. For Early-Write cycles, both twes and two must be met. 4. The /O pins go into high impedance during Read cycles once to¢z of torr occurs. If TAS goes high first, OE becomes a “don't care”. IfOE goes high and CAS stays low, OE is not a “don't care”, and the I/Os will provide the previously read data if OE is taken back low (while CAS remains low). Read-Modify-Write-Cycle symbol paramete ee i aed [ min. | Mex. [win] Max._| [te Restate ee tw | ws | — [me] | me [te [eS wm ceayTme fs | | wp fe I nnn. ee ee ee ee es ee es 1. twes. trwo: town and tawo are not restrictive operating parameters. tao, town, and tawo apply to Read-Modify-Write cycles. if twes 2 twes(min), the cycle is an Early Write cycle and the data I/O pins will remain open circuit (high impedance) throughout the entire cycle. If trwo 2 tawo(min), tewo 2 tewo(min), and tawn 2 tawo(min), the cycle is a Read-Modify-Write cycle and the data /O. Pins will contain read data from the selected cells. If neither of the above sets of conditions are satisfied, the condition of the data W/O pins (at access time) is indeterminate. 2. These parameters are referenced to the falling edge of CAS for Early-Write cycles and to the falling edge of WE for Late-Write and Read-Modify-Write cycles must have both (ez and toe Satisfied (OE high during Write cycle) in order to insure that the output buffers will be in high impedance during the Write cycle. The data /O pins will remain in high impedance until the next valid Read cycle. 27H4339 ©IBM Corporation, 1996. All rights reserved. SA14-4219-04 Use is further subject to the provisions at the end of this document. Revised 6/96 Page 7 of 24

1BM014400M —1BM014400 2S72 1BM014400P _1BM014400B 1M x 410/10 DRAM —_—— SS Read Cycle symbol paramet ee me oe [min [Max | win. | Max | [to [accnetinetonis | | | — | | m | a a [ws [peetconna sate =f ef — | 9 | = pf [ww [Reesconmorstoertnwmas [a | — | 0 | =| fs a [ee lowasutertunonoveyronde |e | 1s | 0 | | |e] a ee aN AS SR OL 1. Assumes that taco S taco(max) and trap S trap(max). If taco OF tap is greater than the maximum recommended value shown in this table, then trac will exceed the value shown. 2. Assumes that tacp 2 taco(max) and tran $ tran(max) 3. Either teop or too must be satisfied, 4. Measured with a load circuit equivalent to 2 TTL loads and 100pF. 5. Either taci oF tarn must be satisfied for a Read cycle. 6. torr(max) and togz(max) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 7. Access time is determined by the longer of tas oF teac OF tcpa. 8. Assumes that taco < tacp(max) and trap 2 trap(max). 9. If OE is tied permanently low, Late-Write or Read-Modify-Write operations are not possible. Fast Page Mode Read-Modify-Write Cycle ; ; ee ee me saree [Min [max | min | Max_| sw ‘©1BM Corporation, 1996. All rights reserved. 27H4339 Use is further subject to the provisions at the end of this document. Sai} 208 Page 8 of 24

===7= 1BM014400 —_ IBM014400M 1BM014400B _1BM014400P 1M x 4 10/10 DRAM — SS Fast Page Mode Cycle | ome _| a | o“ [min | Max | Min [Max a i eae ee Oe Oe | 1. Measured with a load circuit equivalent to 2 TTL loads and 100pF. 2. trasp defines tras in fast page mode cycles. Refresh Cycle [sme | a | | ~~ [ Min. [max | min. | Max. | to CAS Setup Time oR (CAS before RAS Refresh) TAS Hold Time tcxe —_| (CAS before RAS Refresh) 10 10 WE Setup Time (CAS before RAS Refresh) ton WE Hold Time _ " (CAS before RAS Refresh) trer Refresh period ms [| upversion | — [ve | = | ize | ee eee 1. Enables on-chip refresh and address counters. 2. 1024 cycles. Self Refresh Cycle - Low Power version only [em — ee [min [ Max | in [ ax | [aa i a wa an es ec 1. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed in a EVENLY DISTRIBUTED manner over the refresh interval using CBR refresh cycles, then only! one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in a ROR man- ner over the refresh interval, then a full burst of all row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh. If row addresses are being refreshed in a CBR-Burst manner over the refresh interval (i.e. burst of 8), then upon exiting from Self Refresh the user must conform to whatever refresh (i.e. burst of 8) method that was. being used prior to entering Self Refresh 2. VO pins will go into high impedance after 10Qus. —_—_. 27H4339, ‘©IBM Corporation, 1996. All rights reserved. aaa Use is further subject to the provisions at the end of this document. evi Page 9 of 24

1BM014400M —1BM014400 252 1BMO14400P —_1BM014400B 4M x 410/10 DRAM Read Cycle tre tras tre Vin — RAS Vu - ‘ese teoo test tore. ons tors Vu = } trap tra taser tse trea tan Vu - as : : . Address eal eX) Column — }} Vii = i tron treet —— Vin — WE Va - oo OE | ' : ‘ j Vu - fs 4 toze teoo —_ . tozo tooo a Vins ~ = ee aS a Dw : Hi-Z : Va - 4 : teac lot con taz toez Von — N Dour Hiz ( Valid Data Out — |} Hi-Z — Vou = : trac. tou (] 2 “H" or “L” tono eS ‘©IBM Corporation, 1996, Alll rights reserved. 27H4339, Use is further subject to the ovine at the end of this document. SA azie Page 10 of 24

25552 1BM014400—_1BM014400M 1BM014400B _1BM014400P 4M x 4 10/10 DRAM SK Write Cycle (Early Write) tee tras: tke Vin RAS Vi - tosh ————-4 treo test: tore. Vi = { CAS teas Vii — k tran tase tase trean| toan| Vin -| : Address ( eax) Column Vi = twes twox: Vu -] WE tw -——+ Vv __ Vw] OE Vu - tos ton Ow | Valid DataIn iY ‘ ‘ Von — Dour _ Hi. S$ VoL — SSS 27H4339 ‘©IBM Corporation, 1996. All rights reserved. SA14-4219-04 Use is further subject to the provisions at the end of this document. Revised 6/96 Page 11 of 24

1BM014400M —1BM014400 LL 1BMO14400P —_1BM014400B 41M x 410/10 DRAM ee Write Cycle (Delayed Write) tec tras tee Vin — RAS Va = ter. Vin — i [ CAS Vii = ‘ teap tase tase trean| Vin a oes pea Address { \\ {} Column jj Vie i S i i ¢ = a Vn aa ; = Vie He : : | few Vn : toc —| Vi topo: ‘tow tozo tos Ve ‘re ae : : Ow HiZ F)| Valid Data In |} : Vi ee : ol pete Vou — low . Dour ———_ Hi-Z Hi-Z: Vo. — “Output remains Hi-Z because WE is | 2H" or “L” latched internally following typ min. eee ©IBM Corporation, 1996. All rights reserved. j sat 274339 Use is further subject to the provisions at the end of this document. Revised B/96 Page 12 of 24

2 FFE 1BM014400 1BM014400M

1BM014400B = 1BM014400P 1M x 4 10/10 DRAM -—_S Read-Modify-Write Cycle tawe tras: tre Via RAS Vi - tore| Vin y CAS Vue - fran k I tasr’ I~ asc treaty Vin 2 2 = Address 3 | \\ (} Column — \\ Vu — 3s j tewo te. —| 7 to Vn tae . toeH Vn = a . OE Vu Be | toze bs ton ozo r Di g Hi-Z | ye : Vi =| : ; toac touz tooo + toez Vou . Dour Hi-Z Dour | Hi-Z —— Vou — trac + ton E] 2“H" or “Ll” “Output remains Hi-Z because WE is latched internally following tye min. Ss 27H4339 ‘©1BM Corporation, 1996. All rights reserved. SA14-4219-04 Use is further subject to the provisions at the end of this document. Revised 6/96 Page 13 of 24

1BM014400M —_1BM014400 255352 1BM014400P —_1BMO014400B 1Mx 4 10/40 DRAM aR Fast Page Mode Read Cycle tras tee RES Via = top Van = tec RCO top tee test tore Vin — ¥ : CAS teas foas teas Va = i i tase} Ite Address cou Ny y Was {Column 2. |} | ) Vi a ry i [| Ve Lo . L Vie =I ee V treet = Va] i SEE fae LO OE i : ' is : : tono toHo tono ou ton to be ton toze e-toze too, Ee ao : tooo tooo tooo N VK ioe teac 4 K teac j tore trac “espe | tore Vor tog ad Vo.— Home) em: | V {ow EF] “H’ or “L” ‘©1BM Corporation, 1996. All rights reserved. 27H4339 Use is further subject to the provisions at the end of this document. SA14-4219-04 Revised 6/96 Page 14 of 24

1BM014400B _IBM014400P 4M x 410/10 DRAM SS Fast Page Mode Write Cycle tease tre Vn = RAS: Ve - +— tro treo top: [> top test for Vin = ¥ i CAS teas teas Vi. 7 iN fl tasr| d | Address 2 y) eX \\ - | I X\\Columnn tao tow: ten twcr twox y twen __ Vin TSS ¥ twp twe é twe Vit : 3 be \\ Vie : : i i el | | | ton " Vii =A | ey : i } Vou — D. ee our HiZ 4 = “Hor “L” = eeeFeeeeeSSSSsee 27H4339, ‘©IBM Corporation, 1996. All rights reserved. SA14-4219-04 Use is further subject to the provisions at the end of this document. Revised 6/96 Page 15 of 24

IBMO14400M —_1BM014400 LAL 1BM014400P —_18M014400B 4M x 410/10 DRAM ——— Fast Page Mode Read-Modify-Write Cycle trasp tap Vin— RAS Vi - torwe taco: top top: tes tore: Vin— { f CAS teas teas teas tem tasel toan few. Address 2 \\ : ( 3 : 1 oS oF co oe 1 oe tawo ‘ tres sia town” . D t _t town" tin Vm SEE = - Vi- g y + Vin- 5 4 N — i i i OF toot ton toes : ; to rte toe DH oH toze re | [ee fe tooo tooo a tooo tozo* >, A wa ane 4 \\ } ee toez ez. toez tono- tonom | [a toro-| faz taz of taz | out IX ) \\ KY} Hi-z>—— trac: Dour 1 Dour 2 DourN :“H" or “L” ‘IBM Corporation, 1996. All rights reserved. 27H4339 Use is further subject to the provisions at the end of this document. SA14-4219-04 Revised 6/96 Page 16 of 24

ZS FL 1BM014400 —_1BM014400M 1BM014400B _1BM014400P 1M x 4 10/10 DRAM ss RAS Only Refresh Cycle tre tras tee Vin — RAS Vi tepc torp Vi CAS Vi = asp ae Address ( ie i Vi - Ses 4 VoH— Dour —_ SA 2 SSS Vo.— [a 2 “H” or “L” NOTE: WE, OE and Djy are “H” or “L” kw 2714339 ©IBM Corporation, 1996. All rights reserved. SA14-4219-04 Use is further subject to the provisions at the end of this document. Revised 6/96 Page 17 of 24

1BMO14400M —_1BM014400 25372 1BM014400P —_1BM014400B 4M x 410/10 DRAM $$ eee CAS Before RAS Refresh Cycle [+ tre tras tre Viq— RAS Vi - tree: teec | +H tse tesa top Van tour: Rane CAS Vu : : twrH twrH twee tome fe V2 : : Vu - oe Eo) tooo teoo Vou — Ow Hi-Z Vou= toez fore Vou Dour Hi-Z ——_ Vou NOTE: Address is “H” or “L” ©IBM Cor tion, 1996. All rights reserved. 27H4339 Use is. further subject to the provisions at the end of this document. saia2t 388 Page 18 of 24

ZL 1BM014400 —_1BM014400M 18M014400B _1BM014400P 4M x 4 10/10 DRAM Ss Hidden Refresh Cycle (Read) tee tre tre tre tras tras Via - RAS \\ Ve - tro tes +— tone tere Via — CAS Vi - ‘ trap tear task tase tran! Itoar Via — : g Address | \\ | Column jf Vie S| WE Vi - ae ‘ tore | teon On fe 8 : iu — i : : teac os ie faz toez Vox — Dour HiZ x Valid Data Out \\) Hi-Z —— Vo. trac ton SSS 27H4339. ‘©IBM Corporation, 1996. All rights reserved. SA14-4219-04 Use is further subject to the provisions at the end of this document. Revised 6/96 Page 19 of 24

1BM014400M —18M014400 2552 IBMO14400P —_1BM014400B 1M x 410/10 DRAM SS Hidden Refresh Cycle (Write) tre tre tee tre tras tras Vin — RAS Vi - treo test tour tere Vin = { CAS y ase ay tase than Vu Loe y q Address ( KX) Column : : ture fE twes: wou Le ta Vin as : as WE twe 3 : Vi =} A Vu -# d sa : picts tos tou Dv (| Valid Data Xe ie Vou — Dour Vo A$ A A SSS ‘©IBM Corporation, 1996. All rights reserved. 27H4339 Use is further subject to the provisions at the end of this document. SA14-4219-04 Revised 6/96 Page 20 of 24

252 1BM014400 —_ 1BM014400M 1BM014400B 1BM014400P 41M x 410/10 DRAM Self Refresh Cycle (Sleep Mode) - Low Power version only tras: tres Vie— RAS \\ Vi- two ee Te tore twa twee kK torr Vou} D, . a :“H" or “L” NOTE: Address and OE are “H” or “L” Once RAS (min) is provided and RAS remains low, the DRAM will be in Self Refresh, commonly known as “Sleep Mode.” 2744339 ©IBM Corporation, 1996. All rights reserved. SA14-4219-04 Use is further subject to the provisions at the end of this document. Revised 6/96 Page 21 of 24

1BM014400M —_1BM014400 ZL IBM014400P —_1BM014400B 4M x 4 10/40 DRAM SSS Package Dimensions (300mil; 26/20 lead; Small Outline J-Lead) 3.5020.25 2.083 min 17.145 + 0.127 0.76 min S) 3 3| 38 a| & 6.858 Basic x| 3 Pin #1 1D. 0.054 +0, Lead #1 0.20 "0.022 Seating Plane se LI Jk JL Hee 4.27 Basic 0.690 “9.030 0.420 “3058 NOTE: All dimensions are in millimeters; Package diagrams are not drawn to scale. SSS IBM Corporation, 1996. All rights reserved. 27H4339 Use is further subject to the provisions at the end of this document. SA14-4219-04 Revised 6/96 Page 22 of 24

25 E 18M014400_18M014400M

1BM014400B _1BM014400P 4M x 4 10/10 DRAM SSS PACKAGE DIMENSIONS (30omit; 26/20 lead; Thin Small Outline Package) 17.14 £0.10 Detail AN AA AA A AAA A A ‘ : g] 8 ol o Hl oH R| 3 EWSEEE HHEEE ele 0.125 * 9.075 Pin #1 1D ~ 0.005 ‘Seating plane en LI JL ela 1.27 Basic 0.40 £0.10 0.95 REF Detail A 3 0.25 Basic 1.00 + 0.05 Ss Gage Plane = a LT 0.05 *8:38 050.1 NOTE: All dimensions are in millimeters; Package diagrams are not drawn to scale. SSS 27H4339, ‘©IBM Corporation, 1996. All rights reserved. SA14-4219-04 Use is further subject to the provisions at the end of this document. Revised 6/96 Page 23 of 24

1BM014400M _1BM014400 255552 18MO14400P _1BM014400B 4M x 41040 DRAM ———SSSSSSeSeSSeSSSSSSSSSSSeeeeSSESEeeeee Revision Log [Revision | Contents of Modification 1. tape femoved from TAS Before RAS Refresh Cycle timing diagram (end of cycle only). GAS specified as. 01/17/95 “Don't Care” after teu. 2. Corrected tapc value for -70; value changed from 10 to 0. 1, Packaging diagrams updated. 2. The Low Power and Standard Power Specifications were combined. ES# 27H4338 and ES# 27H4339 were combined into ES# 27H4339. 3. Truth Table added. 4. Vin and Vour were added to the Absolute Maximum Ratings table. 5. tcay was changed from 15ns to 10ns for the -70 speed sort. 120/95 6. tox was reduced from 15ns to 12ns for the -60 speed sort. 7. tcus was removed from the Self Refresh Cycle. 8. tcHo was added to the Self Refresh Cycle with a value of 10ns for all speed sorts. 9. The Self Refresh timing diagram was changed to allowCAS to go high tcp (10ns) after RAS falls entering a Self Refresh. 10. The CBR timing diagram was changed to allow CAS to remain low for back-to-back CBR cycles. 05/06/96 1. Die Revision G Part Numbers added. 2. Add Hidden Refresh (Write) timing diagram. ee ©IBM Corporation, 1996. All rights reserved. 27H4339 Use is further subject to the provisions at the end of this document. SA14-4219-04 Revised 6/96 Page 24 of 24