IAM-20381HT

IAM-20381HT TDK | Alldatasheet

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High Performance Automotive Grade-2 3-Axis Accelerometer InvenSense, Inc. reserves the right to change specifications and information herein without notice unless the product is in mass production and the datasheet has been designated by InvenSense in writing as subject to a specified Product / Process Change Notification Method regulation. InvenSense, Inc. 1745 Technology Drive, San Jose, CA 95110 U.S.A +1(408) 988–7339 www.invensense.com Document Number: DS-000559 Revision: 1.0 Rev. Date: 11/24/2023 GENERAL DESCRIPTION The IAM-20381HT is a grade-2 3 -axis accelerometer for Automotive non-safety applications, housed in a thin 3x3x0.75mm3 (16-pin LGA) pack age. It also features a 4096-byte FIFO that can lower the traffic on the serial bus interface and reduce power consumption by allowing the system processor to burst read sensor data and then go into a low -power mode. IAM-20381HT, with its 3-axis integration, enables manufacturers to eliminate the costly and complex selection, qualification, and system level integration of discrete devices, guaranteeing optimal motion performance. The accelerometer has a user -programmable full -scale range of ±2g, ±4g, ±8g and ±16g. Factory-calibrated initial sensitivity of sensors reduces production -line calibration requirements. Other industry -leading features include on -chip 16 -bit ADCs, programmable digital filters, an embedded temperature sensor, and two programmable interrupts. The device features I 2C and SPI serial interfaces, a VDD operating range of 1.71V to 3.6V, and a separate digital IO supply, VDDIO from 1.71V to 3.6V. BLOCK DIAGRAM

APPLICATIONS

IAM-20381HT address a wide range of Automotive applications, including but not limited to:

• Lift Gate Motion Detection
• Tilt measurement
• Infotainment and Navigation Systems
• Car Alarm
• Telematics
• Insurance Vehicle Tracking
• Drive Style Recording

ORDERING INFORMATION

PART† AXES TEMP RANGE PACKAGE MSL* IAM-20381HT X, Y, Z -40°C to +105°C 16-Pin LGA 3 †Denotes RoHS and Green-compliant package * Moisture sensitivity level of the package

FEATURES

• Digital-output X-, Y-, and Z-axis accelerometer with a user-programmable full-scale range of ±2g, ±4g, ±8g and ±16g and integrated 16-bit ADCs
• User-programmable digital filters for accelerometer and temperature sensor
• Embedded Self-test
• Two interrupt lines
• Wake-on-Motion interrupt for low-power operation of applications processor
• Reliability testing performed according to AEC–Q100: PPAP and qualification report available upon request
• Final test at -40°C, 25°C, and +105°C TYPICAL OPERATING CIRCUIT

Document Number: DS-000559 Revision: 1.0 Page 2 of 46 TABLE OF CONTENTS

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1 INTRODUCTION

This document is a pr oduct specification, providing description, specifications, and design related information on the IAM-20381HT Automotive MotionTracking device. The device is housed in a thin 3x3x0.75 mm3 16-pin LGA package. PRODUCT OVERVIEW The IAM-20381HT is a grade-2 3-axis accelerometer for Automotive non-safety applications contained in a thin 3x3x0.75 mm3 (16-pin LGA) package. It also features a 4096-byte FIFO that can lower the traffic on the serial bus interface and reduce power consumption by allowing the system processor to burst read sensor data and then go into a low -power mode . IAM-20381HT, with its 3-axis integration, enables manufacturers to eliminate the costly and complex selection, qualification, and system level integration of discrete devices, guaranteeing optimal motion performance. The accelerometer has a user-programmable full-scale range of ±2g, ±4g, ±8g and ±16g. Factory -calibrated initial sensitivity of both sensors reduces production-line calibration requirements. Other industry -leading features include on -chip 16 -bit ADCs, programmable digital filters, an embedded temperature sensor, and programmable interrupts. The device features I2C and SPI serial interfaces, a VD D operating range of 1.71 V to 3.6V, and a separate digital IO supply, VDDIO from 1.71V to 3.6V. Communication with all registers of the device is performed using either I2C up to 400 kHz or SPI up to 8 MHz. By leveraging its pate nted and volume -proven CMOS -MEMS fabrication platform, which integrates MEMS wafers with companion CMOS electronics through wafer -level bonding, TDK-InvenSense has driven the package size down to a footprint and thickness of 3x3x0.75 mm3 (16-pin LGA), to provide a very small yet high-performance. The device provides high robustness by supporting 10,000g shock reliability. Typical applications include, but aren’t limited to:

• Lift Gate Motion Detections
• Accurate Location for Vehicle to Vehicle and Infrastructure
• View Camera Stabilization and Vision Systems
• Head-up display (HUD) and augmented reality HUD
• Car Alarm
• Telematics
• Insurance Vehicle Tracking

Document Number: DS-000559 Revision: 1.0 Page 8 of 46

2 FEATURES

The triple-axis MEMS accelerometer in IAM-20381HT includes a wide range of features:

• Digital-output X-, Y-, and Z-axis accelerometer with a programmable full-scale range of ±2g, ±4g, ±8g and ±16g and integrated 16-bit ADCs
• Two user-programmable interrupts
• Wake-on-Motion (WoM) interrupt for low-power operation of applications processor
• Self-test ADDITIONAL FEATURES The IAM-20381HT includes the following additional features:
• Thinnest LGA package for automotive applications: 3x3x0.75 mm3 (16-pin LGA)
• 4096-byte FIFO buffer enables the applications processor to read data in bursts
• Digital-output temperature sensor
• User-programmable digital filters for accelerometer and temperature sensor
• 10,000g shock tolerant
• 400 kHz Fast Mode I2C for communicating with all registers
• 8 MHz SPI serial interface for communicating with all registers
• MEMS structure hermetically sealed and bonded at wafer level
• RoHS and Green compliant

3 ELECTRICAL CHARACTERISTICS

All Zero-g output, sensitivity, and noise specifications include board soldering effects , unless otherwise noted. Table 1. Accelerometer Specifications

1. Based on characterization data on a limited number of parts.
2. Tested in production at component level. Over temperature tests are performed at 25°C, 105°C, and/or -40°C.
3. Calculated from Total RMS Noise.
4. Lifetime estimated from AEC-Q100 HTOL test.

Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, Low-Noise Mode enabled unless otherwise noted. Table 2. D.C. Electrical Characteristics

1. Based on characterization data on a limited number of parts.

Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted. Table 3. A.C. Electrical Characteristics

1. Based on characterization data on a limited number of parts.

Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted. Table 4. Other Electrical Specifications

1. Based on characterization data on a limited number of parts.
2. SPI clock duty cycle between 45% and 55% should be used for 8-MHz operation.

Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted. Table 5. I2C Timing Characteristics

1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets.

Figure 1. I2C Bus Timing Diagram

Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted. Table 6. SPI Timing Characteristics (8 MHz Operation)

1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets.
2. Based on other parameter values.

Figure 2. SPI Bus Timing Diagram

extended periods may affect device reliability. Table 7. Absolute Maximum Ratings Table 8. Thermal Information

4 APPLICATIONS INFORMATION

1 VDDIO Digital I/O supply voltage

2 SCL/SPC I2C serial clock (SCL); SPI serial clock (SPC)

3 SDA/SDI I2C serial data (SDA); SPI serial data input (SDI)

4 SA0/SDO I2C slave address LSB (SA0); SPI serial data output (SDO)

5 CS Chip select (0 = SPI mode; 1 = I2C mode)

6 INT Interrupt digital output (push-pull or open-drain)

7 INT2 Second Interrupt digital output (push-pull or open-drain)

13 GND Connect to GND

14 REGOUT Regulator filter capacitor connection

16 VDD Power Supply

Table 9. Signal Descriptions 4.17.2 for detailed power-up instructions. Figure 3. Pin out Diagram for IAM-20381HT 3.0x3.0x0.75mm3 LGA

Figure 4. IAM-20381HT LGA Application Schematic Note: I2C lines are open drain and pullup resistors (e.g. 10 kΩ) are required. Table 10. Bill of Materials

Figure 5. IAM-20381HT Block Diagram

• Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning
• Primary I2C and SPI serial communications interfaces
• Self-Test
• Clocking
• Sensor Data Registers
• FIFO
• Two independent Interrupts
• Digital-Output Temperature Sensor
• Bias and LDOs
• Charge Pump
• Standard Power Modes

Document Number: DS-000559 Revision: 1.0 Page 20 of 46 SELF-TEST Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self -test for each measurement axis can be activated by means of dedicated self-test register (address 0x28 – see 9.4). When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The output signal is used to observe the self-test response. The self-test response is defined as follows: SELF-TEST RESPONSE = SENSOR OUTPUT WITH SELF-TEST ENABLED – SENSOR OUTPUT WITH SELF-TEST DISABLED When the value of the self-test response is within the specified min/max limits of the product specification, the part has passed self- test. When the self-test response exceeds the min/max values, the part is deemed to have failed self -test. CLOCKING The IAM-20381HT has a flexible clocking scheme, allowing a variety of internal clock sources to be used for the internal synchronous circuitry. This synchronous circuitry includes the signal conditioning and ADCs, and various control circuits and registers. An on-chip PLL provides flexibility in the allowable inputs for generating this clock. Allowable internal sources for generating the internal clock are: a) An internal relaxation oscillator b) Auto-select between internal relaxation oscillator and MEMS oscillator to use the best available source The only setting supporting specified performance in all modes is option “b”. Option “b” is the recommended setting to be used. SENSOR DATA REGISTERS The sensor data registers contain the latest accelerometer and temperature measurement data. They are read-only registers and are accessed via the serial interface. Data from these registers may be read anytime. FIFO The IAM-20381HT contains a 4096-byte FIFO register that is accessible via the Serial Interface. The FIFO configuration register determines which data are written into the FIFO. Possible choices include accelerometer data, temperature readings and FSYNC input. A FIFO counter keeps track of how many bytes of valid data are contained in the FIFO. The FIFO register supports burst reads. The interrupt function may be used to determine when new data are available. INTERRUPTS Interrupt functionality is configured via the Interrupt Configuration register. Configurable items include INT pin configuration, interrupt latching and clearing method and interrupt sources. Available interrupt sources are new data available to be read (from the FIFO and Data registers), FIFO overflow and wake on motion. The interrupt status can be read from the Interrupt Status register. DIGITAL-OUTPUT TEMPERATURE SENSOR An on-chip temperature sensor and ADC are used to measure the IAM-20381HT die temperature. The readings from the ADC can be read from the FIFO or the Sensor Data registers. BIAS AND LDOS The bias and LDO section generates the internal supply and the reference voltages and currents required by the IAM-20381HT. Its two inputs are an unregulated VDD and a VDDIO logic reference supply voltage. The LDO output is bypassed by a capacitor at REGOUT. For further details on the capacitor, please refer to the Bill of Materials for External Components. CHARGE PUMP An on-chip charge pump generates the high voltage required for the MEMS oscillator operativity.

Table 11 lists the user-accessible power modes for IAM-20381HT.

1 Sleep Mode Off

3 Accelerometer Wake-on-Motion (WoM) Mode Duty-Cycled

4 Accelerometer Low-Noise Mode On

Table 11. Standard Power Modes for IAM-20381HT

1. Power consumption for individual modes can be found in section 3.2.1.

• Power-up sequence
• Sensor initialization and clock source selection
• Digital interface access test
• Output data rate (i.e. sampling frequency) selection
• Full scale range selection
• Filter frequency selection
• Power mode selection Power-up sequence When applying VDD, the power voltage ramp is detected and a power -on-reset sequence is triggered inside the component. During this phase the device starts operating and internal logic levels are defined. For proper component initialization the power-up should be performed with both CS and SCL/SPC low, ensuring that CS and SCL pins are not in an undetermined state during the VDD ramp. If starting in I2C mode (CS at logic high), power-up should be performed with SCL/SPC low. Power-up with SCL/SPC high is not a supported case and must be avoided. It is worth noting that if the I/O pins (e.g. CS, SCL/SPC) are between VIL and VIH when the power-on-reset sequence is triggered, their value is undetermined and the internal logic levels may not be properly defined. It should also be noted that VIL and VIH are related to VDDIO and their value changes at power-up according to the applied VDDIO voltage ramp. Power-up sequences that do not respect the conditions above may not lead to proper digital interface initialization. In this case a preliminary soft reset operation (PWR_MGMT_1 register set 0x81) must be performed to reset the digital interface , as soon as both VDD and VDDIO are stable at their final voltage. Since the digital interface may not be properly initialized, the device may not provide the acknowledge signal if the I2C protocol is used. Sensor Initialization and Clock Source Selection When power-up sequence is completed (as per section 4.17.1), a soft reset is required to initialize the sensor and let the IAM- 20381HT select the best clock source. The soft reset must be performed by setting the register PWR_MGMT_1 (address 0x6B) to 0x81 (see section 9.18), prior to registers initialization. Soft reset must be performed as first operation after the power-up sequence to ensure the proper component registers setting. Correct WHO_AM_I value is ensured only after the soft reset has been completed. Digital interface access test When soft reset is completed, make sure the component registers access can be done as expected. WHO_AM_I (address 0x75) register can be used for this purpose to verify the identity of the device. Output Data Rate Selection To set the output data rate (ODR) to the desired frequency, select the sample rate divider by setting the register SMPLRT_DIV (address 0x19) to the desired value (see section 9.2). For instance, to set the output data rate to 100 Hz, write 0x09 into SMPLRT_DIV. Full-Scale Range Selection To set the full-scale range (FSR) of the accelerometer, set the register ACCEL_CONFIG (address 0x1C) to the desired value (see section 9.4). For instance, to set the FSR of the accelerometer to 2g, write 0x00 into ACCEL_CONFIG.

Document Number: DS-000559 Revision: 1.0 Page 22 of 46 Filter Selection To set the corner frequency of the digital low-pass filter (DLPF) of the accelerometer, set the register ACCEL_CONFIG2 (address 0x1D) to the desired value (see section 9.5). For instance, to set the corner frequency of the DLPF of the accelerometer to 10.2 Hz, write 0x05 into ACCEL_CONFIG2.

5 PROGRAMMABLE INTERRUPTS

the source of an interrupt. Interrupt sources may be enabled and disabled individually. Table 12. Table of Interrupt Sources

• In PWR_MGMT_1 register (0x6B) set ACCEL_CYCLE = 0, SLEEP = 0; Step 2: Accelerometer Configuration
• In ACCEL_CONFIG2 register (0x1D) set ACCEL_FCHOICE_B = 0 and A_DLPF_CFG[2:0] = b111 Step 3: Enable Motion Interrupt
• In INT_ENABLE register (0x38) set WOM_INT_EN[2:0] = b111 to enable motion interrupt Once triggered, WOM interrupt is generated on INT pin (if INT2_EN bit is set to 0) or on INT2 pin (if INT2_EN is set to 1). Step 4: Set Motion Threshold
• Set the motion threshold in ACCEL_WOM_THR register (0x1F) Step 5: Enable Accelerometer Hardware Intelligence
• In ACCEL_INTEL_CTRL register (0x69) set ACCEL_INTEL_EN = 1 to enable the Wake-on-Motion detection logic
• In ACCEL_INTEL_CTRL register (0x69) set ACCEL_INTEL_MODE = 1 to make the detection insensitive to the acceleration DC- component
• In ACCEL_INTEL_CTRL register (0x69) ensure that bit 0 is set to 0. Step 6: Set Accelerometer WoM ODR Selection
• In LP_MODE_CFG register (0x1E) set ACCEL_WOM_ODR_CTRL[3:0] according to Table 18 Step 7: Enable Cycle Mode (Accelerometer WoM Mode)
• In PWR_MGMT_2 register (0x6C) set STBY_XA = STBY_YA = STBY_ZA = 0
• In PWR_MGMT_1 register (0x6B) set ACCEL_CYCLE = 1

6 DIGITAL INTERFACE

1 VDDIO Digital I/O supply voltage.

4 SA0 / SDO I2C Slave Address LSB (SA0); SPI serial data output (SDO)

2 SCL / SPC I2C serial clock (SCL); SPI serial clock (SPC)

3 SDA / SDI I2C serial data (SDA); SPI serial data input (SDI)

Table 13. Serial Interface performed immediately after waiting for the time specified by the “Start-Up Time for Register Read/Write” in section 3.2.2. For further information regarding the I2C_IF_DIS bit, please refer to sectio ns 8 and 9 of this document. slave address on the bus, and the slave device with the matching address acknowledges the master. and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400 kHz. (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH (see Figure 8). Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition. Figure 8. START and STOP Conditions

SDA line remains high at the 9th clock cycle. The following figures show single and two-byte read sequences. Table 14. I2C Terms

Slave device during standard Master-Slave SPI operation. among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the master. to remain in a high-impedance (high-z) state so that they do not interfere with any active devices.

1. Data are delivered MSB first and LSB last
2. Data are latched on the rising edge of SPC
3. Data should be transitioned on the falling edge of SPC
4. The maximum frequency of SPC is 8 MHz
5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first byte contains the
6. Supports Single or Burst Read/Writes.

Figure 11. Typical SPI Master/Slave Configuration

7 SERIAL INTERFACE CONSIDERATIONS

The IAM-20381HT supports I2C communications on its serial interface. The IAM-20381HT’s I/O logic levels are set to be VDDIO. Figure 12 depicts a sample circuit of IAM-20381HT. It shows the relevant logic levels and voltage connections. Figure 12. I/O Levels and Connections

8 REGISTER MAP

The following table lists the register map for the IAM-20381HT. Table 15. Register map Note: Register Names ending in _H and _L contain the high and low bytes, respectively, of an internal register value.

• Self-test registers 0, 1, 2, 13, 14, 15 contain pre-programmed values
• Register 107, PWR_MGMT_1 = 0x01
• Register 117, WHO_AM_I: (default value is reported in section 9.22)
• Registers 119, 120, 122, 123, 125, 126 contain pre-programmed offset cancellation values

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9 REGISTER DESCRIPTIONS

This section describes the function and contents of each register within the IAM-20381HT. Note: The device will come up in 6-Axis Low-Noise Mode upon power-up. REGISTERS 13 TO 15 – ACCELEROMETER SELF-TEST REGISTERS Register Name: SELF_TEST_X_ACCEL, SELF_TEST_Y_ACCEL, SELF_TEST_Z_ACCEL Type: READ/WRITE Register Address: 13, 14, 15 (Decimal); 0D, 0E, 0F (Hex) REGISTER BIT NAME FUNCTION SELF_TEST_X_ACCEL [7:0] XA_ST_DATA[7:0] The value in this register indicates the self-test output generated during manufacturing tests. This value is to be used to check against subsequent self-test outputs performed by the end user. SELF_TEST_Y_ACCEL [7:0] YA_ST_DATA[7:0] The value in this register indicates the self-test output generated during manufacturing tests. This value is to be used to check against subsequent self-test outputs performed by the end user. SELF_TEST_Z_ACCEL [7:0] ZA_ST_DATA[7:0] The value in this register indicates the self-test output generated during manufacturing tests. This value is to be used to check against subsequent self-test outputs performed by the end user. The equation to convert self-test codes in OTP to factory self-test measurement is: (lsb) 01.1*)2/2620(_ )1_( −= codeSTFSOTPST where ST_OTP is the value that is stored in OTP of the device, FS is the Full Scale value, and ST_code is based on the Self-Test value (ST_ FAC) determined in InvenSense’s factory final test and calculated based on the following equation: 1))01.1log( FSFACSTroundcodeST REGISTER 25 – SAMPLE RATE DIVIDER Register Name: SMPLRT_DIV Register T ype: READ/WRITE Register Address: 25 (Decimal); 19 (Hex) BIT NAME FUNCTION [7:0] SMPLRT_DIV[7:0] Divides the internal sample rate (see register CONFIG) to generate the sample rate that controls sensor data output rate, FIFO sample rate. Note: This register is only effective when FCHOICE_B register bits are 2’b00, and (0 < DLPF_CFG < 7). This is the update rate of the sensor register: SAMPLE_RATE = INTERNAL_SAMPLE_RATE / (1 + SMPLRT_DIV) Where INTERNAL_SAMPLE_RATE = 1 kHz REGISTER 26 – CONFIGURATION Register Name: CONFIG Register T ype: READ/WRITE Register Address: 26 (Decimal); 1A (Hex) BIT NAME FUNCTION [7] - Always set to 0 [6] FIFO_MODE When set to ‘1’, when the FIFO is full, additional writes will not be written to FIFO. When set to ‘0’, when the FIFO is full, additional writes will be written to the FIFO, replacing the oldest data.

[5:3] EXT_SYNC_SET[2:0] Enables the FSYNC pin data to be sampled.

1 TEMP_OUT_L[0]

2 Reserved

3 Reserved

4 Reserved

5 ACCEL_XOUT_L[0]

6 ACCEL_YOUT_L[0]

7 ACCEL_ZOUT_L[0]

toggles, but won’t toggle again until the new latched value is captured by the sample rate strobe. [2:0] DLPF_CFG[2:0] For the DLPF to be used, FCHOICE_B[1:0] is 2’b00. DLPF_CFG and FCHOICE_B as shown in Table 16. Table 16. Temperature Sensor bandwidth configuration

[3] ACCEL_FCHOICE_B Used to bypass DLPF as shown in the table below. [2:0] A_DLPF_CFG Accelerometer low pass filter setting as shown in the table below. Table 17. Accelerometer Data Rates and Bandwidths (Low-Noise Mode) the accelerometer is duty-cycled. To operate in accelerometer WoM mode, ACCEL_CYCLE must be set to ‘1’ in PWR_MGMT_1 (address 0x6B).

Table 18. Example Configurations for Accelerometer WoM Mode Accelerometer WoM Mode ODR configuration. threshold resolution is 4 mg/LSB regardless the selected full scale.

Document Number: DS-000559 Revision: 1.0 Page 34 of 46 REGISTER 35 – FIFO ENABLE Register Name: FIFO_EN Register T ype: READ/WRITE Register Address: 35 (Decimal); 23 (Hex) BIT NAME FUNCTION [7] TEMP_FIFO_EN 1 – Write TEMP_OUT_H and TEMP_OUT_L to the FIFO at the sample rate; If enabled, buffering of data occurs even if data path is in standby. 0 – Function is disabled. [6:4] - Reserved. [3] ACCEL_FIFO_EN 1 – Write ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L, ACCEL_ZOUT_H, and ACCEL_ZOUT_L to the FIFO at the sample rate; 0 – Function is disabled. [2:0] - Reserved. REGISTER 54 – FSYNC INTERRUPT STATUS Register Name: FSYNC_INT Register T ype: READ to CLEAR Register Address: 54 (Decimal); 36 (Hex) BIT NAME FUNCTION [7] FSYNC_INT This bit automatically sets to 1 when a FSYNC interrupt has been generated. The bit clears to 0 after the register has been read. REGISTER 55 – INT/INT2 PIN / BYPASS ENABLE CONFIGURATION Register Name: INT_PIN_CFG Register T ype: READ/WRITE Register Address: 55 (Decimal); 37 (Hex) BIT NAME FUNCTION [7] INT_LEVEL 1 – The logic level for INT/INT2 pin is active low. 0 – The logic level for INT/INT2 pin is active high. [6] INT_OPEN 1 – INT/INT2 pin is configured as open drain. 0 – INT/INT2 pin is configured as push-pull. [5] LATCH_INT_EN 1 – INT/INT2 pin level held until interrupt status is cleared. 0 – INT/INT2 pin indicates interrupt pulse’s width is 50 µs. [4] INT_RD_CLEAR 1 – Interrupt status is cleared if any read operation is performed. 0 – Interrupt status is cleared only by reading INT_STATUS register [3] FSYNC_INT_LEVEL 1 – The logic level for the FSYNC pin as an interrupt is active low. 0 – The logic level for the FSYNC pin as an interrupt is active high. [2] FSYNC_INT_MODE_EN When this bit is equal to 1, the FSYNC pin will trigger an interrupt when it transitions to the level specified by FSYNC_INT_LEVEL. When this bit is equal to 0, the FSYNC pin is disabled from causing an interrupt. [1] - Reserved. [0] INT2_EN When INT2_EN = 0, all of the interrupts appear on the INT pin, and INT2 interrupt pin is unused. When INT2_EN = 1, all interrupts except for data ready appear on the INT2 pin, and data ready interrupt appears on the INT interrupt pin.

Document Number: DS-000559 Revision: 1.0 Page 35 of 46 REGISTER 56 – INTERRUPT ENABLE Register Name: INT_ENABLE Register T ype: READ/WRITE Register Address: 56 (Decimal); 38 (Hex) BIT NAME FUNCTION [7:5] WOM_INT_EN[2:0] 111 – Enable WoM interrupt on accelerometer. 000 – Disable WoM interrupt on accelerometer. [4] FIFO_OFLOW_EN 1 – Enables a FIFO buffer overflow to generate an interrupt. 0 – Function is disabled. [3:1] - Reserved. [0] DATA_RDY_INT_EN Data ready interrupt enable. Data ready interrupt is always generated on INT pin. All the other interrupts signals are generated on INT pin if INT2_EN bit is set to 0 or on INT2 pin if INT2_EN bit is set to 1. REGISTER 58 – INTERRUPT STATUS Register Name: INT_STATUS Register T ype: READ to CLEAR Register Address: 58 (Decimal); 3A (Hex) BIT NAME FUNCTION [7:5] WOM_INT[2:0] Accelerometer WoM interrupt status. Cleared on Read. 111 – WoM interrupt on accelerometer [4] FIFO_OFLOW_INT This bit automatically sets to 1 when a FIFO buffer overflow has been generated. The bit clears to 0 after the register has been read. [3:1] - Reserved. [0] DATA_RDY_INT This bit automatically sets to 1 when a Data Ready interrupt is generated. The bit clears to 0 after the register has been read. REGISTERS 59 TO 64 – ACCELEROMETER MEASUREMENTS Register Name: ACCEL_XOUT_H Register T ype: READ only Register Address: 59 (Decimal); 3B (Hex) BIT NAME FUNCTION [7:0] ACCEL_XOUT_H[15:8] High byte of accelerometer x-axis data. Register Name: ACCEL_XOUT_L Register T ype: READ only Register Address: 60 (Decimal); 3C (Hex) BIT NAME FUNCTION [7:0] ACCEL_XOUT_L[7:0] Low byte of accelerometer x-axis data. Register Name: ACCEL_YOUT_H Register T ype: READ only Register Address: 61 (Decimal); 3D (Hex) BIT NAME FUNCTION [7:0] ACCEL_YOUT_H[15:8] High byte of accelerometer y-axis data. Register Name: ACCEL_YOUT_L Register T ype: READ only Register Address: 62 (Decimal); 3E (Hex) BIT NAME FUNCTION [7:0] ACCEL_YOUT_L[7:0] Low byte of accelerometer y-axis data.

Document Number: DS-000559 Revision: 1.0 Page 36 of 46 Register Name: ACCEL_ZOUT_H Register T ype: READ only Register Address: 63 (Decimal); 3F (Hex) BIT NAME FUNCTION [7:0] ACCEL_ZOUT_H[15:8] High byte of accelerometer z-axis data. Register Name: ACCEL_ZOUT_L Register T ype: READ only Register Address: 64 (Decimal); 40 (Hex) BIT NAME FUNCTION [7:0] ACCEL_ZOUT_L[7:0] Low byte of accelerometer z-axis data. REGISTERS 65 AND 66 – TEMPERATURE MEASUREMENT Register Name: TEMP_OUT_H Register T ype: READ only Register Address: 65 (Decimal); 41 (Hex) BIT NAME FUNCTION [7:0] TEMP_OUT[15:8] High byte of the temperature sensor output. Register Name: TEMP_OUT_L Register T ype: READ only Register Address: 66 (Decimal); 42 (Hex) BIT NAME FUNCTION [7:0] TEMP_OUT[7:0] Low byte of the temperature sensor output TEMP_degC = ((TEMP_OUT – RoomTemp_Offset)/Temp_Sensitivity) + 25degC REGISTER 104 – SIGNAL PATH RESET Register Name: SIGNAL_PATH_RESET Register T ype: READ/WRITE Register Address: 104 (Decimal); 68 (Hex) BIT NAME FUNCTION [7:2] - Reserved. [1] ACCEL_RST Reset accel digital signal path. Note: Sensor registers are not cleared. Use SIG_COND_RST to clear sensor registers. [0] TEMP_RST Reset temp digital signal path. Note: Sensor registers are not cleared. Use SIG_COND_RST to clear sensor registers. REGISTER 105 – ACCELEROMETER INTELLIGENCE CONTROL Register Name: ACCEL_INTEL_CTRL Register T ype: READ/WRITE Register Address: 105 (Decimal); 69 (Hex) BIT NAME FUNCTION [7] ACCEL_INTEL_EN This bit enables the Wake-on-Motion detection logic. [6] ACCEL_INTEL_MODE 0 – Compares the current sample to the first sample taken when entering in WoM mode. 1 – Compare the current sample with the previous sample. [5:1] - Reserved. [0] - Reserved, must be set to 0 when WoM is activated. Please refer to section 5.1

Document Number: DS-000559 Revision: 1.0 Page 37 of 46 REGISTER 106 – USER CONTROL Register Name: USER_CTRL Register T ype: READ/WRITE Register Address: 106 (Decimal); 6A (Hex) BIT NAME FUNCTION [7] - Reserved. [6] FIFO_EN 1 – Enable FIFO operation mode. 0 – Disable FIFO access from serial interface. To disable FIFO writes by DMA, use FIFO_EN register. [5] - Reserved. [4] I2C_IF_DIS 1 – Disable I2C Slave module and put the serial interface in SPI mode only. [3] - Reserved. [2] FIFO_RST 1 – Reset FIFO module. Reset is asynchronous. This bit auto clears after one clock cycle of the internal 20 MHz clock. [1] - Reserved. [0] SIG_COND_RST 1 – Reset all accel digital signal path and temp digital signal path. This bit also clears all the sensor registers. REGISTER 107 – POWER MANAGEMENT 1 Register Name: PWR_MGMT_1 Register T ype: READ/WRITE Register Address: 107 (Decimal); 6B (Hex) BIT NAME FUNCTION [7] DEVICE_RESET 1 – Reset the internal registers and restores the default settings. The bit automatically clears to 0 once the reset is done. [6] SLEEP When set to 1, the chip is set to sleep mode. Default setting is 0. [5] ACCEL_CYCLE When set to 1, and SLEEP and STANDBY are not set to 1, the chip will cycle between sleep and taking a single accelerometer sample. Note: When all accelerometer axes are disabled via PWR_MGMT_2 register bits and cycle is enabled, the chip will wake up at the rate determined by the respective registers above, but will not take any samples. [4] - Reserved. [3] TEMP_DIS When set to 1, this bit disables the temperature sensor. [2:0] CLKSEL[2:0] Code Clock Source 0 Internal 20 MHz oscillator.

1 Auto selects the best available clock source – PLL if ready, else use the Internal oscillator

2 Auto selects the best available clock source – PLL if ready, else use the Internal oscillator

3 Auto selects the best available clock source – PLL if ready, else use the Internal oscillator

4 Auto selects the best available clock source – PLL if ready, else use the Internal oscillator

5 Auto selects the best available clock source – PLL if ready, else use the Internal oscillator

6 Internal 20 MHz oscillator. 7 Stops the clock and keeps timing generator in reset. Note: The default value of CLKSEL[2:0] is 001. REGISTER 108 – POWER MANAGEMENT 2 Register Name: PWR_MGMT_2 Register T ype: READ/WRITE Register Address: 108 (Decimal); 6C (Hex) BIT NAME FUNCTION [7] FIFO_LP_EN 1 – Enable FIFO in Accelerometer WoM mode. Default setting is 0. [6] - Reserved. [5] STBY_XA 1 – X accelerometer is disabled. 0 – X accelerometer is on. [4] STBY_YA 1 – Y accelerometer is disabled. 0 – Y accelerometer is on. [3] STBY_ZA 1 – Z accelerometer is disabled. 0 – Z accelerometer is on. [2:0] - Reserved.

Document Number: DS-000559 Revision: 1.0 Page 38 of 46 REGISTERS 114 AND 115 – FIFO COUNT REGISTERS Register Name: FIFO_COUNTH Register T ype: READ Only Register Address: 114 (Decimal); 72 (Hex) BIT NAME FUNCTION [7:5] - Reserved. [4:0] FIFO_COUNT[12:8] High Bits; count indicates the number of written bytes in the FIFO. Reading this byte latches the data for both FIFO_COUNTH, and FIFO_COUNTL. Register Name: FIFO_COUNTL Register T ype: READ Only Register Address: 115 (Decimal); 73 (Hex) BIT NAME FUNCTION [7:0] FIFO_COUNT[7:0] Low Bits; count indicates the number of written bytes in the FIFO. Note: Must read FIFO_COUNTH to latch new data for both FIFO_COUNTH and FIFO_COUNTL. REGISTER 116 – FIFO READ WRITE Register Name: FIFO_R_W Register T ype: READ/WRITE Register Address: 116 (Decimal); 74 (Hex) BIT NAME FUNCTION [7:0] FIFO_DATA[7:0] Read/Write command provides Read or Write operation for the FIFO. Description: This register is used to read and write data from the FIFO buffer. Data are written to the FIFO in order of register number (from lowest to highest). If all the FIFO enable flags (see below) are enable d, the contents of registers 59 through 66 will be written in order at the Sample Rate. The contents of the sensor data registers (Registers 59 to 66) are written into the FIFO buffer when their corresponding FIFO enable flags are set to 1 in FIFO_EN (Register 35). If the FIFO buffer has overflowed, the status bit FIFO_OFLOW_INT is automatically set to 1. This bit is in INT_STATUS (Register 58). When the FIFO buffer has overflowed, the oldest data will be lost and new data will be written to the FIFO unless register 26 CONFIG, bit[6] FIFO_MODE = 1. If the FIFO buffer is empty, reading register FIFO_DATA will return a unique value of 0xFF until new data are available. Normal data are precluded from ever indicating 0xFF, so 0xFF gives a trustworthy indication of FIFO empty. REGISTER 117 – WHO AM I Register Name: WHO_AM_I Register T ype: READ only Register Address: 117 (Decimal); 75 (Hex) BIT NAME FUNCTION [7:0] WHOAMI Register to indicate to user which device is being accessed. This register is used to verify the identity of the device. The contents of WHOAMI is an 8-bit device ID. The default value of the register is 0xB7 This is different from the I2C address of the device as seen on the slave I2C controller by the applications processor. The I2C address of the IAM-20381HT is 0x68 or 0x69 depending upon the value driven on AD0 pin.

Document Number: DS-000559 Revision: 1.0 Page 39 of 46 REGISTERS 119, 120, 122, 123, 125, 126 ACCELEROMETER OFFSET REGISTERS Register Name: XA_OFFSET_H Register T ype: READ/WRITE Register Address: 119 (Decimal); 77 (Hex) BIT NAME FUNCTION [7:0] XA_OFFS[14:7] Bits 14 to 7 of the 15-bit of the X accelerometer offset cancellation (2’s complement). ±16g Offset cancellation in all Full-Scale modes, 15 bit 0.98-mg steps. Register Name: XA_OFFSET_L Register T ype: READ/WRITE Register Address: 120 (Decimal); 78 (Hex) BIT NAME FUNCTION [7:1] XA_OFFS[6:0] Bits 6 to 0 of the 15-bit of the X accelerometer offset cancellation (2’s complement). ±16g Offset cancellation in all Full-Scale modes, 15 bit 0.98-mg steps. [0] - Reserved. This bit is set during factory calibration and the value must be kept unchanged. Register Name: YA_OFFSET_H Register T ype: READ/WRITE Register Address: 122 (Decimal); 7A (Hex) BIT NAME FUNCTION [7:0] YA_OFFS[14:7] Bits 14 to 7 of the 15-bit of the Y accelerometer offset cancellation (2’s complement). ±16g Offset cancellation in all Full-Scale modes, 15 bit 0.98-mg steps. Register Name: YA_OFFSET_L Register T ype: READ/WRITE Register Address: 123 (Decimal); 7B (Hex) BIT NAME FUNCTION [7:1] YA_OFFS[6:0] Bits 6 to 0 of the 15-bit of the Y accelerometer offset cancellation (2’s complement). ±16g Offset cancellation in all Full-Scale modes, 15 bit 0.98-mg steps. [0] - Reserved. This bit is set during factory calibration and the value must be kept unchanged. Register Name: ZA_OFFSET_H Register T ype: READ/WRITE Register Address: 125 (Decimal); 7D (Hex) BIT NAME FUNCTION [7:0] ZA_OFFS[14:7] Bits 14 to 7 of the 15-bit of the Z accelerometer offset cancellation (2’s complement). ±16g Offset cancellation in all Full-Scale modes, 15 bit 0.98-mg steps. Register Name: ZA_OFFSET_L Register T ype: READ/WRITE Register Address: 126 (Decimal); 7E (Hex) BIT NAME FUNCTION [7:1] ZA_OFFS[6:0] Bits 6 to 0 of the 15-bit of the Z accelerometer offset cancellation (2’s complement). ±16g Offset cancellation in all Full-Scale modes, 15 bit 0.98-mg steps. [0] - Reserved. This bit is set during factory calibration and the value must be kept unchanged.

10 ASSEMBLY

Figure 13 below shows the orientation of the axes of sensitivity. Note the pin 1 identifier (•) in the figure. Figure 13. Orientation of Axes of Sensitivity

16 Lead LGA 3x3x0.75 mm3 NiAu pad finish. Figure 14. Package Dimensions

Table 19. Package Dimensions

11 PART NUMBER PACKAGE MARKING

Table 20. Part Number Package Marking Figure 15. Part Number Package Marking specifications reported in the datasheet. Engineering samples are not production -intent parts.

Document Number: DS-000559 Revision: 1.0 Page 44 of 46

12 REFERENCE

Please refer to “InvenSense MEMS Motion Handling and Assembly Guide (AN-IVS-0002A-00)” for the following information:

• Manufacturing Recommendations o Assembly Guidelines and Recommendations o PCB Design Guidelines and Recommendations o MEMS Handling Instructions o ESD Considerations o Reflow Specification o Storage Specifications o Package Marking Specification o Tape & Reel Specification o Reel & Pizza Box Label o Packaging o Representative Shipping Carton Label
• Compliance o Environmental Compliance o DRC Compliance o Compliance Declaration Disclaimer

Document Number: DS-000559 Revision: 1.0 Page 45 of 46

13 REVISION HISTORY

REVISION DATE REVISION DESCRIPTION 11/24/2023 1.0 Initial revision

Document Number: DS-000559 Revision: 1.0 Page 46 of 46 This information furnished by InvenSense, Inc. (“InvenSense”) is believed to be accurate and reliable. However, no responsibility is assumed by InvenSense for its use, or for any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to change without notice. InvenSense reserves the right to make changes to this product, including its circuits and software, in order to improve its design and/or performance, without prior notice. InvenSense makes no warranties, neither expressed nor implied, regarding the information and specifications contained in this document. InvenSense assumes no responsibility for any claims or damages arising from information contained in this document, or from the use of products and services detailed therein. This includes, but is not limited to, claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights. Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted b y implication or otherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied. Trademarks that are registered trademarks are the property of their respective companies. InvenSense sensors should not be used or sold in the development, storage, production or utilization of any conventional or mass-destructive weapons or for any other weapons or life threatening applications, as well as in any other life critical applications such as m edical equipment, transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment. ©2017—2023 InvenSense. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps, DMP, AAR, and t he InvenSense logo are trademarks of InvenSense, Inc. The TDK logo is a trademark of TDK Corporation. Other company and product names may be trademarks of the respective companies with which they are associated. ©2017—2023 InvenSense. All rights reserved.