IA4420

IA4420 ETC1 | Alldatasheet

Document overview

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Technical content

FEATURES

• Fully integrated (low BOM, easy design-in)
• No alignment required in production
• Fast-settling, programmable, high-resolution PLL synthesizer
• Fast frequency-hopping capability
• High bit rate (up to 115.2 kbps in digital mode and 256 kbps in analog mode)
• Direct differential antenna input/output
• Integrated power amplifier
• Programmable TX frequency deviation (15 to 240 KHz)
• Programmable RX baseband bandwidth (67 to 400 kHz)
• Analog and digital RSSI outputs
• Automatic frequency control (AFC)
• Data quality detection (DQD)
• Internal data filtering and clock recovery
• RX synchron pattern recognition
• SPI compatible serial control interface
• Clock and reset signals for microcontroller
• 16 bit RX Data FIFO
• Two 8 bit TX data registers
• Low power duty cycle mode
• Standard 10 MHz crystal reference
• Wake-up timer
• 2.2 to 5.4 V supply voltage
• Low power consumption
• Low standby current (0.3 µA)
• Compact 16 pin TSSOP package TYPICAL APPLICATIONS
• Remote control
• Home security and alarm
• Wireless keyboard/mouse and other PC peripherals
• Toy controls
• Remote keyless entry
• Tire pressure monitoring
• Telemetry
• Personal/patient data logging
• Remote automatic meter reading See back page for ordering information.

DESCRIPTION

Integration’s IA4420 is a single chip, low power, multi-channel FSK transceiver designed for use in applications requiring FCC or ETSI conformance for unlicensed use in the 315, 433, 868 and 915 MHz bands. The IA4420 transceiver is a part of Integration’s EZRadioTM product line, which produces a flexible, low cost, and highly integrated solution that does not require production alignments. The chip is a complete analog RF and baseband transceiver including a multi-band PLL synthesizer with PA, LNA, I/Q down converter mixers, baseband filters and amplifiers, and an I/Q demodulator. All required RF functions are integrated. Only an external crystal and bypass filtering are needed for operation. The IA4420 features a completely integrated PLL for easy RF design, and its rapid settling time allows for fast frequency-hopping, bypassing multipath fading and interference to achieve robust wireless links. The PLL’s high resolution allows the usage of multiple channels in any of the bands. The receiver baseband bandwidth (BW) is programmable to accommodate various deviation, data rate and crystal tolerance requirements. The transceiver employs the Zero-IF approach with I/Q demodulation. Consequently, no external components (except crystal and decoupling) are needed in most applications. The IA4420 dramatically reduces the load on the microcontroller with the integrated digital data processing features: data filtering, clock recovery, data pattern recognition, integrated FIFO and TX data register. The automatic frequency control (AFC) feature allows the use of a low accuracy (low cost) crystal. To minimize the system cost, the IA4420 can provide a clock signal for the microcontroller, avoiding the need for two crystals. For low power applications, the IA4420 supports low duty cycle operation based on the internal wake-up timer. FUNCTIONAL BLOCK DIAGRAM IA4420-DS Rev 1.4r 0705 www.integration.com PRELIMINARY IA4420 PIN ASSIGNMENT revC and later SDI SCK nSEL SDO nIRQ FSK / DATA / nFFS DCLK / CFIL / FFIT CLK nINT / VDI ARSSI VDD VSS RF1 RF2 nRES XTL / REF RF Parts Low Power parts Data processing units BB Amp/Filt./Limiter AMP OC AMP OC LNA MIX I Q MIX Data Filt CLK Rec data clk DQD COMP RSSI AFC PLL & I/Q VCO with cal. Controller Xosc Self cal. LBD WTM with cal. CLK div Bias RF1 RF2 12 CLK XTL / REF nINT / VDI ARSSI SCK nSEL SDO nIRQ VSS VDD SDI DCLK / CFIL / FFIT / FSK / DATA / nFFS FIFO nRES PA I/Q DEMOD

DETAILED FEATURE-LEVEL DESCRIPTION The IA4420 FSK transceiver is designed to cover the unlicensed frequency bands at 315, 433, 868 and 915 MHz. The devices facilitate compliance with FCC and ETSI requirements. The receiver block employs the Zero-IF approach with I/Q demodulation, allowing the use of a minimal number of external components in a typical application. The IA4420 incorporates a fully integrated multi-band PLL synthesizer, PA with antenna tuning, an LNA with switchable gain, I/Q down converter mixers, baseband filters and amplifiers, and an I/Q demodulator followed by a data filter. PLL The programmable PLL synthesizer determines the operating frequency, while preserving accuracy based on the on-chip crystal- controlled reference oscillator. The PLL’s high resolution allows the usage of multiple channels in any of the bands. The RF VCO in the PLL performs automatic calibration, which requires only a few microseconds. Calibration always occurs when the synthesizer starts. If temperature or supply voltage changes significantly, VCO recalibration can be invoked easily. Recalibration can be initiated at any time by switching the synthesizer off and back on again. The power amplifier has an open-collector differential output and can directly drive a loop antenna with a programmable output power level. An automatic antenna tuning circuit is built in to avoid costly trimming procedures and the so-called “hand effect.” Baseband Filters The receiver bandwidth is selectable by programming the bandwidth (BW) of the baseband filters. This allows setting up the receiver according to the characteristics of the signal to be received. An appropriate bandwidth can be chosen to accommodate various FSK deviation, data rate and crystal tolerance requirements. The filter structure is 7th order Butterworth low-pass with 40 dB suppression at 2*BW frequency. Offset cancellation is done by using a high-pass filter with a cut-off frequency below 7 kHz. LNA The LNA has 250 Ohm input impedance, which functions well with the proposed antennas (see: Application Notes available from http://www.integration.com) If the RF input of the chip is connected to 50 Ohm devices, an external matching circuit is required to provide the correct matching and to minimize the noise figure of the receiver. The LNA gain can be selected (0, –6, –14, –20 dB relative to the highest gain) according to RF signal strength. It can be useful in an environment with strong interferers. Data Filtering and Clock Recovery Output data filtering can be completed by an external capacitor or by using digital filtering according to the final application. Analog operation: Analog operation: Analog operation: Analog operation: Analog operation: The filter is an RC type low-pass filter followed by a Schmitt-trigger (St). The resistor (10 kOhm) and the St are integrated on the chip. An (external) capacitor can be chosen according to the actual bit rate. In this mode, the receiver can handle up to 256 kbps data rate. The FIFO can not be used in this mode and clock is not provided for the demodulated data. Digital operation: Digital operation: Digital operation: Digital operation: Digital operation: A digital filter is used with a clock frequency at 29 times the bit rate. In this mode there is a clock recovery circuit (CR), which can provide synchronized clock to the data. Using this clock the received data can fill a FIFO. The CR has three operation modes: fast, slow, and automatic. In slow mode, its noise immunity is very high, but it has slower settling time and requires more accurate data timing than in fast mode. In automatic mode the CR automatically changes between fast and slow mode. The CR starts in fast mode, then after locking it automatically switches to slow mode (Only the digital data filter and the clock recovery use the bit rate clock. For analog operation, there is no need for setting the correct bit rate.) RF Power Amplifier (PA)

The IA4420 has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for the PLL. To reduce external parts and simplify design, the crystal load capacitor is internal and programmable. Guidelines for selecting the appropriate crystal can be found later in this datasheet. The transceiver can supply the clock signal for the microcontroller; so accurate timing is possible without the need for a second crystal. Interface and Controller An SPI compatible serial interface lets the user select the frequency band, center frequency of the synthesizer, and the bandwidth of the baseband signal path. Division ratio for the microcontroller clock, wake-up timer period, and low supply voltage detector threshold are also programmable. Any of these auxiliary functions can be disabled when not needed. All parameters are set to default after power-on; the programmed values are retained during sleep mode. The interface supports the read-out of a status register, providing detailed information about the status of the transceiver and the received data. The transmitter block is equipped with an 8 bit wide TX data register. It is possible to write 8 bits into the register in burst mode and the internal bit rate generator transmits the bits out with the predefined rate. It is also possible to store the received data bits into a FIFO register and read them out in a buffered mode. By using an integrated Automatic Frequency Control (AFC) feature, the receiver can minimize the TX/RX offset in discrete steps, allowing the use of: Inexpensive, low accuracy crystals Narrower receiver bandwidth (i.e. increased sensitivity) Higher data rate AFC -65 dBm 1300 mV -65 dBm 1000 mV -100 dBm 600 mV -100 dBm 300 mV Input Power [dBm] RSSI voltage [V] Data Validity Blocks RSSI RSSI RSSI RSSI RSSI A digital RSSI output is provided to monitor the input signal level. It goes high if the received signal strength exceeds a given preprogrammed level. An analog RSSI signal is also available. The RSSI settling time depends on the external filter capacitor. Pin 15 is used as analog RSSI output. The digital RSSI can be can be monitored by reading the status register. Low Battery Voltage Detector The low battery detector circuit monitors the supply voltage and generates an interrupt if it falls below a programmable threshold level. The detector circuit has 50 mV hysteresis. Wake-Up Timer The wake-up timer has very low current consumption (1.5 uA typical) and can be programmed from 1 ms to several days with an accuracy of ±5%. It calibrates itself to the crystal oscillator at every startup, and then at every 30 seconds. When the crystal oscillator is switched off, the calibration circuit switches it back on only long enough for a quick calibration (a few milliseconds) to facilitate accurate wake-up timing. Event Handling In order to minimize current consumption, the transceiver supports different power saving modes. Active mode can be initiated by several wake-up events (negative logical pulse on nINT input, wake-up timer timeout, low supply voltage detection, on-chip FIFO filled up or receiving a request through the serial interface). If any wake-up event occurs, the wake-up logic generates an interrupt signal, which can be used to wake up the microcontroller, effectively reducing the period the microcontroller has to be active. The source of the interrupt can be read out from the transceiver by the microcontroller through the SDO pin. DQD DQD DQD DQD DQD The Data Quality Detector is based on counting the spikes on the unfiltered received data. For correct operation, the “DQD threshold” parameter must be filled in by using the Data Filter Command. Analog RSSI Voltage vs. RF Input Power When the microcontroller turns the crystal oscillator off by clearing the appropriate bit using the Configuration Setting Command, the chip provides a fixed number (196) of further clock pulses (“clock tail”) for the microcontroller to let it go to idle or sleep mode.

Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output Note: Note: Note: Note: Note: The actual mode of the multipurpose pins (pin 6 and 7) is determined by the TX/RX data I/O settings of the transceiver. SDI SCK nSEL SDO nIRQ FSK / DATA / nFFS DCLK / CFIL / FFIT CLK nINT / VDI ARSSI VDD VSS RF1 RF2 nRES XTL / REF Pin Name Type Function SDI DI Data input of the serial control interface (SPI compatible) SCK DI Clock input of the serial control interface nSEL DI Chip select input of the serial control interface (active low) SDO DO Serial data output with bus hold nIRQ DO Interrupt request output (active low) FSK DI Transmit FSK data input DATA DO Received data output (FIFO not used) nFFS DI FIFO select input (active low) In FIFO mode, when bit ef is set in Configuration Setting Command DLCK DO Received data clock output (Digital filter used, FIFO not used) CFIL AIO External data filter capacitor connection (Analog filter used) FFIT DO FIFO interrupt (active high) Number of the bits in the RX FIFO that reach the preprogrammed limit In FIFO mode, when bit ef is set in Configuration Setting Command CLK DO Microcontroller clock output XTL AIO Crystal connection (the other terminal of crystal to VSS) or external reference input REF AIO External reference input. Use 33 pF series coupling capacitor nRES DIO Open drain reset output with internal pull-up and input buffer (active low) VSS S Ground reference voltage RF2 AIO RF differential signal input/output RF1 AIO RF differential signal input/output VDD S Positive supply voltage ARSSI AO Analog RSSI output nINT DI Interrupt input (active low) VDI DO Valid data indicator output

Typical application with FIFO usage Pin 6 Pin 7 Transmit mode el=0 in Configuration Setting Command Transmit mode el=1 in Configuration Setting Command Receive mode ef=0 in Configuration Setting Command Receive mode ef=1 in Configuration Setting Command RX Data output RX Data clock output nFFS input FFIT output TX Data input Connect to logic high 100p 10p 10MHz IA4420 VCC SCK SDO nIRQ SDI CLKin nSEL nFFS FFIT nRES PCB Antenna Microcontroller nRES 2.2n CLK (optional) TP (optional) (optional) (optional) (optional) (optional) VDI

GENERAL DEVICE SPECIFICATION All voltages are referenced to Vss, the potential on the ground reference pin VSS. Absolute Maximum Ratings (non-operating) Recommended Operating Range No No No No Nottttte 1: e 1: e 1: e 1: No No No No Nottttte 2: e 2: e 2: e 2: e 2: At maximum, Vdd+1.5 V cannot be higher than 5.5 V. Symbol Parameter Min Max Units Vdd Positive supply voltage -0.5 V Vin Voltage on any pin (except RF1 and RF2) -0.5 Vdd+0.5 V Voc Voltage on open collector outputs (RF1, RF2) -0.5 Vdd+1.5 (Note 1) V Iin Input current into any pin except VDD and VSS -25 mA ESD Electrostatic discharge with human body model 1000 V Tst Storage temperature -55 125 oC Tld Lead temperature (soldering, max 10 s) 260 oC Symbol Parameter Min Max Units Vdd Positive supply voltage 2.2 5.4 V VocDC DC voltage on open collector outputs (RF1, RF2) Vdd+1.5 (Note 2) V VocAC AC peak voltage on open collector outputs (RF1, RF2) Vdd+1.5 V Top Ambient operating temperature -40 oC Vdd-1.5 (Note 1)

(Min/max values are valid over the whole recommended operating range. Typical conditions: Top= 27 oC; Vdd = Voc = 2.7 V) DC Characteristics Symbol Parameter Conditions/Notes Min Typ Max Units 315/433 MHz bands

868 MHz band

915 MHz band

Standby current (Sleep mode) All blocks disabled 0.3 µA Ilb Low battery voltage detector current consumption 0.5 µA Iwt Wake-up timer current consumption 1.5 µA Ix Idle current Crystal oscillator and baseband parts are on 3.5 mA Vlb Low battery detect threshold Programmable in 0.1 V steps 2.2 5.3 V Vlba Low battery detection accuracy +/-75 mV Vil Digital input low level voltage 0.3*Vdd V Vih Digital input high level voltage 0.7*Vdd V Iil Digital input current Vil = 0 V µA Iih Digital input current Vih = Vdd, Vdd = 5.4 V µA Vol Digital output low level Iol = 2 mA 0.4 V Voh Digital output high level Ioh = -2 mA Vdd-0.4 V Idd_TX_PMAX Supply current (TX mode, Pout = Pmax) mA Idd_RX Supply current (RX mode) mA Idd_TX_0 Supply current (TX mode, Pout = 0 dBm) mA

AC Characteristics (Receiver) AC Characteristics (PLL parameters) All notes for tables above are on page 10. All notes for tables above are on page 10. All notes for tables above are on page 10. All notes for tables above are on page 10. All notes for tables above are on page 10. Symbol Parameter Conditions/Notes Min Typ Max Units mode 0 mode 1 120 134 150 mode 2 180 200 225 mode 3 240 270 300 mode 4 300 350 375 mode 5 360 400 450 BR FSK bit rate With internal digital filters 0.6 115.2 kbps BRA FSK bit rate With analog filter 256 kbps Pmin Receiver Sensitivity BER 10-3, BW=67 kHz, BR=1.2 kbps (Note 2) -109 -100 dBm AFCrange AFC locking range dfFSK: FSK deviation in the received signal 0.8*dfFSK IIP3inh Input IP3 In band interferers in high bands (868, 915 MHz) -21 dBm Out of band interferers l f-fo l > 4 MHz IIP3inl IIP3 (LNA –6 dB gain) In band interferers in low bands (315, 433 MHz) -15 dBm Out of band interferers l f-fo l > 4 MHz Pmax Maximum input power LNA: high gain dBm Cin RF input capacitance pF RSa RSSI accuracy +/-5 dB RSr RSSI range dB CARSSI Filter capacitor for ARSSI nF RSstep RSSI programmable level steps dB RSresp DRSSI response time Until the RSSI signal goes high after the input signal exceeds the preprogrammed limit CARRSI = 5 nF 500 us kHz dBm -18 BW Receiver bandwidth IIP3outh Input IP3 -12 dBm IIP3outl IIP3 (LNA –6 dB gain) Symbol Parameter Conditions/Notes Min Typ Max Units fref PLL reference frequency (Note 1) MHz 315 MHz band, 2.5 kHz resolution 310.24 319.75 433 MHz band, 2.5 kHz resolution 430.24 439.75 868 MHz band, 5.0 kHz resolution 860.48 879.51 915 MHz band, 7.5 kHz resolution 900.72 929.27 Frequency error < 1kHz after 10 MHz step tst, P PLL startup time With a running crystal oscillator 250 us us tlock PLL lock time fo Receiver LO/Transmitter carrier frequency MHz

AC Characteristics (Transmitter) AC Characteristics (Turn-on/Turnaround timings) AC Characteristics (Others) All notes for tables above are on page 10. All notes for tables above are on page 10. All notes for tables above are on page 10. All notes for tables above are on page 10. All notes for tables above are on page 10. Symbol Parameter Conditions/Notes Min Typ Max Units Crystal load capacitance, see crystal selection guide tPOR Internal POR timeout After Vdd has reached 90% of final value (Note 7) 100 ms tPBt Wake-up timer clock period Calibrated every 30 seconds 0.95 1.05 ms Cin, D Digital input capacitance pF tr, f Digital output rise/fall time 15 pF pure capacitive load ns pF Cxl Programmable in 0.5 pF steps, tolerance +/- 10% 8.5 Symbol Parameter Conditions/Notes Min Typ Max Units tsx Crystal oscillator startup time Crystal ESR < 100 ms Ttx_rx_XTAL_ON Transmitter - Receiver turnover time Synthesizer off, crystal oscillator on during TX/RX change with 10 MHz step 450 us Trx_tx_XTAL_ON Receiver - Transmitter turnover time Synthesizer off, crystal oscillator on during RX/TX change with 10 MHz step 350 us Ttx_rx_SYNT_ON Transmitter - Receiver turnover time Synthesizer and crystal oscillator on during TX/RX change with 10 MHz step 425 us Trx_tx_SYNT_ON Receiver - Transmitter turnover time Synthesizer and crystal oscillator on during RX/TX change with 10 MHz step 300 us Symbol Parameter Conditions/Notes Min Typ Max Units IOUT Open collector output DC current Programmable 0.5 mA In low bands In high bands Pout Typical output power Selectable in 3 dB steps (Note 5) Pmax-21 Pmax dBm Psp Spurious emission At max power with loop antenna (Note 6) -50 dBc Output capacitance In low bands 2.6 3.2 (set by the automatic antenna tuning circuit) In high bands 2.1 2.7 3.3 In low bands In high bands 100 kHz from carrier -75

1 MHz from carrier

-85 BR FSK bit rate 256 kbps dffsk FSK frequency deviation Programmable in 15 kHz steps 240 kHz Pmax Available output power with optimal antenna impedance (Note 3, 4) dBm pF Co Qo Quality factor of the output capacitance Lout Output phase noise dBc/Hz

Note 5: Note 5: Note 5: Note 5: Note 5: Adjustable in 8 steps. Note 6: Note 6: Note 6: Note 6: Note 6: With selective resonant antennas (see: Application Notes available from http://www.integration.com). No No No No Nottttte 7 e 7 e 7 e 7 e 7::::: During this period, commands are not accepted by the chip. AC Characteristics (continued) Note 1: Note 1: Note 1: Note 1: Note 1: Not using a 10 MHz crystal is allowed but not recommended because all crystal referred timing and frequency parameters will change accordingly. Note 2: Note 2: Note 2: Note 2: Note 2: See the BER diagrams in the measurement results section for detailed information (Not available at this time). Note 3: Note 3: Note 3: Note 3: Note 3: See matching circuit parameters and antenna design guide for information. Note 4: Note 4: Note 4: Note 4: Note 4: Optimal antenna admittance/impedance: IA4420 Yantenna [S] Zantenna [Ohm] Lantenna [nH]

315 MHz

1.5E-3 - j5.14E-3 52 + j179 98.00

433 MHz

1.4E-3 - j7.1E-3 27 + j136 52.00

868 MHz

2E-3 - j1.5E-2 8.7 + j66 12.50

915 MHz

2.2E-3 - j1.55E-2 9 + j63 11.20

Minimum Value [ns] tCH Clock high time tCL Clock low time tSS Select setup time (nSEL falling edge to SCK rising edge) tSH Select hold time (SCK falling edge to nSEL rising edge) tSHI Select high time tDS Data setup time (SDI transition to SCK rising edge) tDH Data hold time (SCK rising edge to SDI transition) tOD Data delay time tBL Push-button input low time CONTROL INTERFACE Commands to the transmitter are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. All commands consist of a command code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits having no influence (don’t care) are indicated with X. The Power On Reset (POR) circuit sets default values in all control and command registers. The receiver will generate an interrupt request (IT) for the microcontroller - by pulling the nIRQ pin low - on the following events: The TX register is ready to receive the next byte (RGIT) The FIFO has received the preprogrammed amount of bits (FFIT) Power-on reset (POR) FIFO overflow (FFOV) / TX register underrun (RGUR) Wake-up timer timeout (WKUP) Negative pulse on the interrupt input pin nINT (EXT) Supply voltage below the preprogrammed value is detected (LBD) FFIT and FFOV are applicable when the FIFO is enabled. RGIT and RGUR are applicable only when the TX register is enabled. To identify the source of the IT, the status bits should be read out. Timing Specification Timing Diagram SCK SDI SDO nSEL tDS tDH tCH tCL BIT15 BIT14 BIT13 tSS BIT8 BIT7 tOD OFFS(0) FIFO OUT BIT1 BIT0 tSH tSHI FFIT FFOV ATS CRL

In general, setting the given bit to one will activate the related function. In the following tables, the POR column shows the default values of the command registers after power-on. 1. Configuration Setting Command Description of the Control Commands Bit el enables the internal data register. If the data register is used the FSK pin must be connected to logic high level. Bit ef enables the FIFO mode. If ef=0 then DATA (pin 6) and DCLK (pin 7) are used for data and data clock output. Frequency Band {MHz] 315 433 868 915 Crystal Load Capacitance [pF] 8.5 9.0 9.5 10.0 15.5 16.0 Bit POR el ef 8008h Control Command Related Parameters/Functions Related control bits Configuration Setting Command Frequency band, crystal oscillator load capacitance, baseband filter bandwidth, etc. el, ef, b1 to b0, x3 to x0 Power Management Command Receiver/Transmitter mode change, synthesizer, xtal osc, PA, wake-up timer, clock output can be enabled here er, ebb, et, es, ex, eb, ew, dc Frequency Setting Command Data frequency of the local oscillator/carrier signal f11 to f0 Data Rate Command Bit rate cs, r6 to r0 Receiver Control Command Function of pin 16, Valid Data Indicator, baseband bw, LNA gain, digital RSSI threshold p16, d1 to d0, i2 to i0, g1 to g0, r2 to Data Filter Command Data filter type, clock recovery parameters al, ml, s1 to s0, f2 to f0 FIFO and Reset Mode Command Data FIFO IT level, FIFO start control, FIFO enable and FIFO fill enable f3 to f0, s1 to s0, ff, fe Receiver FIFO Read Command RX FIFO can be read with this command AFC Command AFC parameters a1 to a0, rl1 to rl0, st, fi, oe, en TX Configuration Control Command Modulation parameters, output power, ea mp, m3 to m0, p2 to p0 Transmitter Register Write Command TX data register can be written with this command t7 to t0 Wake-Up Timer Command Wake-up time period r4 to r0, m7 to m0 Low Duty-Cycle Command Enable low duty-cycle mode. Set duty-cycle. d6 to d0, en Low Battery Detector and Microcontroller Clock Divider Command LBD voltage and microcontroller clock division ratio d2 to d0, v4 to v0 Status Read Command Status bits can be read out

1. Power Management Command The ebb, es, and ex bits are provided to optimize the TX to RX or RX to TX turnaround time. Logic connections between power control bits: Edge detector et er es ebb ex enable oscillator enable baseband circuits enable RF front end enable RF synthesizer start TX clear TX latch (If TX latch is used) (synt. must be on) (osc.must be on) enable power amplifier Bit POR er ebb et es ex eb ew dc 8208h Bit Function of the control bit Related blocks er Enables the whole receiver chain RF front end, baseband, synthesizer, oscillator ebb The receiver baseband circuit can be separately switched on Baseband et Switches on the PLL, the power amplifier, and starts the transmission (If TX register is enabled) Power amplifier, synthesizer, oscillator es Turns on the synthesizer Synthesizer ex Turns on the crystal oscillator Crystal oscillator eb Enables the low battery detector Low battery detector ew Enables the wake-up timer Wake-up timer dc Disables the clock output (pin 8) Clock output buffer

1. Frequency Setting Command Bit POR f11 f10 A680h The 12-bit parameter F (bits f11 to f0) should be in the range of 96 and 3903. When F value sent is out of range, the previous value is kept. The synthesizer center frequency f0 can be calculated as: The constants C1 and C2 are determined by the selected band as: Band [MHz] 315 433 868 915 4. Data Rate Command The actual bit rate in transmit mode and the expected bit rate of the received data stream in receive mode is determined by the 7-bit parameter R (bits r6 to r0) and bit cs. In the receiver set R according to the next function: R= (10000 / 29 / (1+cs*7) / BR) – 1, where BR is the expected bit rate in kbps. Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated with small error. Data rate accuracy requirements: Clock recovery in slow mode: ∆BR/BR < 1/(29*Nbit) Clock recovery in fast mode: ∆BR/BR < 3/(29*Nbit) BR is the bit rate set in the receiver and ∆BR is the bit rate difference between the transmitter and the receiver. Nbit is the maximal number of consecutive ones or zeros in the data stream. It is recommended for long data packets to include enough 1/0 and 0/1 transitions, and be careful to use the same division ratio in the receiver and in the transmitter. 5. Receiver Control Command Bit 10 (p16): pin16 function select Bit POR cs C623h p16 Function of pin 16 Interrupt input VDI output Bit POR p16 9080h

Bits 9-8 (d1 to d0): VDI (valid data indicator) signal response time setting: Bits 7-5 (i2 to i0): Receiver baseband bandwidth (BW) select: Response Fast Medium Slow Always on R/S FF LOGIC HIGH CR_LOCK DRSSI DQD IN0 IN1 IN2 IN3 SEL1 SEL0 Y Q CR_LOCK DQD CR_LOCK DQD DRSSI SET CLR VDI MUX FAST MEDIUM SLOW BW [kHz] reserved 400 340 270 200 134 reserved

RSSIsetth [dBm] -103 -97 -91 -85 -79 -73 -67 -61 Bits 4-3 (g1 to g0): LNA gain select: Bits 2-0 (r2 to r0): RSSI detector threshold: The RSSI threshold depends on the LNA gain, the real RSSI threshold can be calculated: RSSIth=RSSIsetth+GLNA 6. Data Filter Command Bit 7 (al): Clock recovery (CR) auto lock control, if set. CR will start in fast mode, then after locking it will automatically switch to slow mode. Bit 6 (ml): Clock recovery lock control 1: fast mode, fast attack and fast release (6 to 8 bit preamble (1010...) is recommended) 0: slow mode, slow attack and slow release (12 to 16 bit preamble is recommended) Using the slow mode requires more accurate bit timing (see Data Rate Command). Bits 4 (s): Select the type of the data filter: Digital: This is a digital realization of an analog RC filter followed by a comparator with hysteresis. The time constant is automatically adjusted to the bit rate defined by the Data Rate Command. Note: Note: Note: Note: Note: Bit rate can not exceed 115 kpbs in this mode. s Filter Type Digital filter Analog RC filter Analog RC filter: The demodulator output is fed to pin 7 over a 10 kOhm resistor. The filter cut-off frequency is set by the external capacitor connected to this pin and VSS. C = 1 / (3 * R * Bit Rate), therefore the suggested value for 9600 bps is 3.3 nF Note: Note: Note: Note: Note: If analog RC filter is selected the internal clock recovery circuit and the FIFO can not be used. Bit POR al ml s C22Ch relative to maximum [dB] -14 -20

1. FIFO and Reset Mode Command Bits 7-4 (f4 to f0): FIFO IT level. The FIFO generates IT when the number of received data bits reaches this level. Bit 2 (al): Set the input of the FIFO fill start condition: Note: Note: Note: Note: Note: Synchron pattern in microcontroller mode is 2DD4h. Bit 1 (ff): FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is cleared. Bit 0 (dr): Disables the highly sensitive RESET mode. If this bit is cleared, a 200 mV glitch in the power supply may cause a system reset. al Synchron pattern Always fill ef* Note: * For details see the Configuration Setting Command For deatils see the Power Management Command ff er FFIT nFIFO_RESET FFOV SYNCHRON PATTERN al FIFO_WRITE _EN FIFO_LOGIC No No No No Nottttte: e:e: e:e: To restart the synchron pattern recognition, bit 1 should be cleared and set. Bits 2-0 (f2 to f0): DQD threshold parameter. Note Note Note Note Note: To let the DQD report "good signal quality" the threshold parameter should be less than 4 in the case when the bitrate is close to the deviation. At higher deviation/bitrate settings higher threshold parameter can report "good signal quality" as well. Bit POR al ff dr CA80h

1. Receiver FIFO Read Command With this command, the controller can read 8 bits from the receiver FIFO. Bit 6 (ef) must be set in Configuration Setting Command. 9. AFC Command Bit 7-6 (a1 to a0): Automatic operation mode selector: fres: 315, 433 MHz bands: 2.5 kHz

868 MHz band: 5 kHz

915 MHz band: 7.5 kHz Bit POR B000h Bit 5-4 (rl1 to rl0): Range limit. Limits the value of the frequency offset register to the next values: Bit 3 (st): Strobe edge, when st goes to high, the actual latest calculated frequency error is stored into the offset register of the AFC block. Bit 2 (fi): Switches the circuit to high accuracy (fine) mode. In this case, the processing time is about twice longer, but the measurement uncertainty is about the half. Bit 1 (oe): Enables the frequency offset register. It allows the addition of the offset register to the frequency control word of the PLL. Bit 0 (en): Enables the calculation of the offset frequency by the AFC circuit. rl1 rl0 Max deviation No restriction +15 fres to -16 fres +7 fres to -8 fres +3 fres to -4 fres Auto mode off (Strobe is controlled by microcontroller) Runs only once after each power-up Keep the foffset only during receiving (VDI=high) Keep the foffset value independently from the state of the VDI signal Bit POR rl1 rl0 st fi oe en C4F7h nSEL SCK SDI SDO received bits out FFIT in RX mode / RGIT otherwise MSB LSB Note: The transceiver is in receive (RX) mode when bit er is set using the Power Management Command

Note: Note: Note: Note: Note: Lock bit is high when the AFC loop is locked, f_same bit indicates when two subsequent measuring results are the same, toggle bit changes state in every measurement cycle. In automatic operation mode (no strobe signal is needed from the microcontroller to update the output offset register) the AFC circuit is automatically enabled when the VDI indicates potential incoming signal during the whole measurement cycle and the circuit measures the same result in two subsequent cycles. There are three operation modes, example from the possible application: 1, (a1=0, a0=1) The circuit measures the frequency offset only once after power up. In this way extended TX-RX maximum distance can be achieved. Possible application: In the final application, when the user inserts the battery, the circuit measures and compensates for the frequency offset caused by the crystal tolerances. This method allows for the use of a cheaper quartz in the application and provides protection against tracking an interferer. 2a, (a1=1, a0=0) The circuit automatically measures the frequency offset during an initial effective low data rate pattern –easier to receive- (i.e.: 00110011) of the package and changes the receiving frequency accordingly. The further part of the package can be received by the corrected frequency settings. 2b, (a1=1, a0=0) The transmitter must transmit the first part of the packet with a step higher deviation and later there is a possibility to reduce it. In both cases (2a and 2b), when the VDI indicates poor receiving conditions (VDI goes low), the output register is automatically cleared. Use these settings when receiving signals from different transmitters transmitting in the same nominal frequencies. 3, (a1=1, a0=1) It’s the same as 2a and 2b modes, but suggested to use when a receiver operates with only one transmitter. After a complete measuring cycle, the measured value is kept independently of the state of the VDI signal. 10. TX Configuration Control Command oe 10MHz CLK DIGITAL AFC CORE LOGIC st fi en Parameter from Frequency control word F<11:0> VDI* a1 to a0 DIGITAL LIMITER IF IN>MaxDEV THEN OUT=MaxDEV IF IN<MinDEV THEN OUT=MinDEV ELSE OUT=IN

7 BIT

FREQ. OFFSET REGISTER CLK CLR

12 BIT

<6:0> NOTE: * VDI (valid data indicator) is an internal signal of the controller. See the Receiver Setting Command for details. ATGL: toggling in each measurement cycle * ASAME: logic high when the result is stable Corrected frequency parameter to synthesizer Fcorr<11:0> CLK FINE rl1 to rl0 RANGE LIMIT STROBE OUTPUT ENABLE AUTO OPERATION BASEBAND SIGNAL IN strobe ATGL ASAME* output enable Power-on reset (POR) singals for auto operation modes ENABLE CALCULATION MUX SEL Y Bit POR mp 9800h

1. Transmitter Register Write Command With this command, the controller can write 8 bits (t7 to t0) to the transmitter data register. Bit 7 (el) must be set in Configuration Setting Command. Bits 8-4 (mp, m3 to m0): FSK modulation parameters: Bits 2-0 (p2 to p0): Output power: The output power given in the table is relative to the maximum available power, which depends on the actual antenna impedance. (See: Antenna Application Note: IA ISM-AN1) Relative Output Power [dB] -12 -15 -18 -21 The resulting output frequency can be calculated as: fout = f0 + (-1)SIGN * (M + 1) * (15 kHz) where: f0 is the channel center frequency (see the Frequency Setting Command) M is the four bit binary number <m3 : m0> SIGN = (mp) XOR (FSK input) out f out P f fsk df fsk df mp=0 and FSK=0 mp=1 and FSK=1 mp=1 and FSK=0 mp=0 and FSK=1 or or Bit POR B8AAh 12. Wake-Up Timer Command Bit POR E196h The wake-up time period can be calculated by (m7 to m0) and (r4 to r0): Twake-up = M * 2R [ms] Note: Note: Note: Note: Note: For continual operation the et bit should be cleared and set at the end of every cycle. For future compatibility, use R in a range of 0 and 29.

1. Low Duty-Cycle Command With this command, Low Duty-Cycle operation can be set in order to decrease the average power consumption in receiver mode. The time cycle is determined by the Wake-Up Timer Command. The Duty-Cycle can be calculated by using (d6 to d0) and M. (M is parameter in a Wake-Up Timer Command.) Duty-Cycle= (D * 2 +1) / M *100% Bit POR en C80Eh Bit 0 (en): Enables the Low Duty-Cycle Mode. Wake-up timer interrupt not generated in this mode. Note: Note: Note: Note: Note: In this operation mode, bit er must be cleared and bit ew must be set in the Power Management Command. 14. Low Battery Detector and Microcontroller Clock Divider Command The 5 bit parameter (v4 to v0) represents the value V, which defines the threshold voltage Vlb of the detector: Clock divider configuration: Clock Output Frequency [ MHz] 1.25 1.66 2.5 3.33 Bit POR C000h The low battery detector and the clock output can be enabled or disabled by bits eb and dc, respectively, using the Power Management Command. Receiver On DQD Twake-up Xtal osc. enable 2.25ms Ton Twake-up Ton Twake-up Ton 2.25ms

1. Status Read Command The read command starts with a zero, whereas all other control commands start with a one. If a read command is identified, the status bits will be clocked out on the SDO pin as follows: Status Register Read Sequence with FIFO Read Example: RGIT TX register is ready to receive the next byte (Can be cleared by Transmitter Register Write Command ) FFIT The number of data bits in the RX FIFO has reached the pre-programmed limit (Can be cleared by any of the FIFO read methods) POR Power-on reset (Cleared after Status Read Command ) RGUR TX register under run, register over write (Cleared after Status Read Command ) FFOV RX FIFO overflow (Cleared after Status Read Command ) WKUP Wake-up timer overflow (Cleared after Status Read Command ) EXT Logic level on interrupt pin (pin 16) changed to low (Cleared after Status Read Command ) LBD Low battery detect, the power supply voltage is below the pre-programmed limit FFEM FIFO is empty ATS Antenna tuning circuit detected strong enough RF signal RSSI The strength of the incoming signal is above the pre-programmed limit DQD Data quality detector output CRL Clock recovery locked ATGL Toggling in each AFC cycle OFFS(6) MSB of the measured frequency offset (sign of the offset value) OFFS(3) -OFFS(0) Offset value to be added to the value of the frequency control parameter (Four LSB bits) nSEL SCK SDI SDO command LBD FFEM CRL ATGL OFFS<3> status bits out POR WKUP EXT interrupt bits out FO+1 FO+2 FIFO out OFFS<2> OFFS<1> DQD OFFS<0> FO (Sign) OFFS<6> Bits marked are internally latched, the others are only multiplexed out (Latched) (Latched) (Latched) (Latched) (Latched) FFIT* RGIT** FFOV* RGUR** RSSI* ATS** Notes: * Applicable when the transceiver is in receive (RX) mode i.e. bit er is set using the Power Management Command ** Applicable when bit er is cleared using the Power Management Command

TX REGISTER BUFFERED DATA TRANSMISSION In this operating mode (enabled by bit el, the Configuration Control Command) the TX data is clocked into one of the two 8-bit data registers. The transmitter starts to send out the data from the first register (with the given bit rate) when bit et is set with the Power Management Command. The initial value of the data registers (AAh) can be used to generate preamble. During this mode, the SDO pin can be monitored to check whether the register is ready (SDO is high) to receive the next byte from the microcontroller. TX register simplified block diagram (before transmit) TX register simplified block diagram (during transmit) Typical TX register usage Note: Note: Note: Note: Note: The content of the data registers are initialized by clearing bit et. 8 bit shift register (default: AAh) 8 bit shift register (default: AAh) CLK CLK Di Di Do Do Serial bus data et=0 (register initial fillup) TX_DATA Serial bus clk 8 bit shift register 8 bit shift register CLK CLK Di Di Do Do Bit rate Serial bus clk 1:8 Serial bus data et=1 (during TX) TX_DATA MUX MUX divider SEL SEL Y Y MUX SEL Y et bit (enable transmitter) TX data SPI commands (nSEL, SCK, SDI) enable Synthesizer / PA PA Synt. nIRQ SDO** TX latch wr TX latch wr et=1 Power Man TX byte1 TX byte2 TX byte2 TX latch wr TX byte3 TX byte3 80us TX byte1 Note: *tsp is the start-up time of the PLL ** SDO is tri-state if nSEL is logic high. et=0 Power Man Conf. cnt. el=1 tsp* Dummy byte TX latch wr Dummy TX byte

RX FIFO BUFFERED DATA READ In this operating mode, incoming data are clocked into a 16 bit FIFO buffer. The receiver starts to fill up the FIFO when the Valid Data Indicator (VDI) bit and the synchron pattern recognition circuit indicates potentially real incoming data. This prevents the FIFO from being filled with noise and overloading the external microcontroller. Polling Mode: The nFFS signal selects the buffer directly and its content can be clocked out through pin SDO by SCK. Set the FIFO IT level to 1. In this case, as long as FFIT indicates received bits in the FIFO, the controller may continue to take the bits away. When FFIT goes low, no more bits need to be taken. An SPI read command is also available. Interrupt Controlled Mode: The user can define the FIFO level (the number of received bits) which will generate the nFFIT when exceeded. The status bits report the changed FIFO status in this case. FIFO Read Example with FFIT Polling During FIFO access fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency. nSEL SCK nFFS SDO FO+1 FO+2 FIFO OUT FO+4 FO+3 FIFO read out FFIT

CRYSTAL SELECTION GUIDELINES The crystal oscillator of the IA4420 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in order to minimize the external component count. The internal load capacitance value is programmable from 8.5 pF to 16 pF in 0.5 pF steps. With appropriate PCB layout, the total load capacitance value can be 10 pF to 20 pF so a variety of crystal types can be used. When the total load capacitance is not more than 20 pF and a worst case 7 pF shunt capacitance (C0) value is expected for the crystal, the oscillator is able to start up with any crystal having less than 300 ohms ESR (equivalent series loss resistance). However, lower C0 and ESR values guarantee faster oscillator startup. The crystal frequency is used as the reference of the PLL, which generates the local oscillator frequency (fLO). Therefore fLO is directly proportional to the crystal frequency. The accuracy requirements for production tolerance, temperature drift and aging can thus be determined from the maximum allowable local oscillator frequency error. Whenever a low frequency error is essential for the application, it is possible to “pull” the crystal to the accurate frequency by changing the load capacitor value. The widest pulling range can be achieved if the nominal required load capacitance of the crystal is in the “midrange”, for example 16 pF. The “pull-ability” of the crystal is defined by its motional capacitance and C0. Maximum XTAL Tolerances Including Temperature and Aging [ppm] Bit Rate: 2.4kbps 105 120 Bit Rate: 9.6kbps 105 120 Bit Rate: 38.3kbps 105 120 don't use 100 100 don't use don't use don't use Deviation [+/- kHz] Deviation [+/- kHz] Deviation [+/- kHz]

RX-TX ALIGNMENT PROCEDURES RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To minimize these errors it is suggested to use the same crystal type and the same PCB layout for the crystal placement on the RX and TX PCBs. To verify the possible RX-TX offset it is suggested to measure the CLK output of both chips with a high level of accuracy. Do not measure the output at the XTL pin since the measurement process itself will change the reference frequency. Since the carrier frequencies are derived from the reference frequency, having identical reference frequencies and nominal frequency settings at the TX and RX side there should be no offset if the CLK signals have identical frequencies. It is possible to monitor the actual RX-TX offset using the AFC status report included in the status byte of the receiver. By reading out the status byte from the receiver the actual measured offset frequency will be reported. In order to get accurate values the AFC has to be disabled during the read by clearing the "en" bit in the AFC Control Command (bit 0). TYPICAL APPLICATIONS REPEATER DEMO (915 MHZ) Schematics 3,3V P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0/C2D /RST/C2CK VDD GND IC1 SW1 SJ1 DEBUG IC3 GND IN ON OUT POK BATTERY SDI SCK NSEL SDO NIRQ FSK/DATA/NFFS DCLK/CFIL NINT/VDI XTL/REF CLK VSS RF2 RF1 VDD ARSSI NRES IC2 TX TX RX RX SEL SEL CLK CLK IRQ IRQ SCK SCK MISO MISO MOSI MOSI FFS FFS FFE FFE INT/VDI INT/VDI ARSSI ARSSI C8051F311 GND VCC GND 820 820 820 820 Red Green Yellow Red VCC GND GND VCC 100nF GND GND 4,7nF 10MHz GND GND GND VCC GND IA2112-3.3V 100k 2,2uF 2,2uF VCC 1uF 100pF 10pF VCC GND VCC GND GND IA4420-REVC

Detail “A” Gauge Plane 0.25 Section B-B See Detail “A”

PACKAGE INFORMATION

Min. Nom. Max. Min. Nom. Max. A 1,20 0,047 0,05 0,15 0,002 0,006 0,80 0,90 1,05 0,031 0,035 0,041 b 0,19 0,30 0,007 0,012 0,19 0,22 0,25 0,007 0,009 0,010 c 0,09 0,20 0,004 0,008 0,09 0,16 0,004 0,006 D 4,90 5,00 5,10 0,193 0,197 0,201 e E 4,30 4,40 4,50 0,169 0,173 0,177 L 0,50 0,60 0,75 0,020 0,024 0,030 R 0,09 0,004 0,09 0,004 Symbol Dimensions in mm Dimensions in Inches 0.65 BSC. 0.026 BSC. 6.40 BSC. 12 REF. 12 REF. 12 REF. 12 REF. 1.00 REF. 0.252 BSC. 0.39 REF.

Integration Associates, Inc.

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Mountain View, California 94041 Tel: 650.969.4100 Fax: 650.969.4582 www.integration.com info@integration.com techsupport@integration.com P694 ©2005, Integration Associates, Inc. All rights reserved. Integration Associates and EZRadio are trademarks of Integration Associates, Inc. All other trademarks belong to their respective owners. This document may contain preliminary information and is subject to change by Integration Associates, Inc. without notice. Integration Associates assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Integration Associates or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in the direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. RELATED PRODUCTS AND DOCUMENTS IA 4420 Universal ISM Band FSK Transceiver Revision # Demo Boards and Development Kits IA ISM – DK ISM Repeater Demo IA ISM – DARP Related Resources IA ISM – AN1 Antenna Development Guide IA ISM – AN2 IA 4220/21 Universal ISM Band FSK Transmitters see http://www.integration.com for details Note: Volume orders must include chip revision to be accepted. IA 4320 Universal ISM Band FSK Receiver see http://www.integration.com for details