Logic IC

HVDA540QDSJRQ1

Texas Instruments

5-V CAN TRANSCEIVER WITH I/O LEVEL ADAPTING AND LOW-POWER MODE SUPPLY OPTIMIZATION

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SN65HVDA540-Q1,SN65HVDA541-Q1,SN65HVDA542-Q1 SN65HVDA540-5-Q1,SN65HVDA541-5-Q1,SN65HVDA542-5-Q1 www.ti.com SLLS804B –MARCH 2009–REVISED SEPTEMBER 2010 5-VCANTRANSCEIVER WITHI/OLEVELADAPTINGANDLOW-POWERMODE SUPPLYOPTIMIZATION Check for Samples: SN65HVDA540-Q1 ,SN65HVDA541-Q1 ,SN65HVDA542-Q1 ,SN65HVDA540-5-Q1 ,SN65HVDA541-5-Q1 ,SN65HVDA542-5-Q1 1FEATURES DESCRIPTION• QualifiedforAutomotive Applications

Meets or Exceeds theRequirements of The device is designed and qualifiedfor use in automotiveapplicationsand meets or exceeds theISO 11898-2and ISO 11898-5 specificationsof the ISO 11898 High Speed CAN• GIFT/ICTCompliant (ControllerArea Network) PhysicalLayer standard• ESD Protectionup to±12 kV (Human-Body (transceiver). Model) on Bus Pins FUNCTIONAL BLOCK DIAGRAM• I/OVoltageLevelAdapting – SN65HVDA54x: AdaptableI/OVoltage Range (VIO)From 3 V to5.33V – SN65HVDA54x-5: 5 V VCC Device Version
OperatingModes: – Normal Mode: AllDevices – Low Power Standby Mode (VCC not required,onlyVIO Supply Needed Saving System Power) – SN65HVDA540: No Wake Up – SN65HVDA541: RXD Wake Up Request – Silent(ReceiveOnly)Mode: SN65HVDA542
High ElectromagneticCompliance (EMC)
Package Options:SOIC and VSON
Protection – UndervoltageProtectionon VIO and VCC – Bus-FaultProtectionof–27 V to40 V – TXD Dominant StateTime Out – RXD Wake Up Request Lock Out on CAN Bus Stuck Dominant Fault(SN65HVDA541) – Thermal Shutdown Protection – Power-Up/Down Glitch-FreeBus I/O – High Bus InputImpedance When Unpowered (No Bus Load)

APPLICATIONS

SAE J2284 High-Speed CAN forAutomotive
SAE J1939 Standard Data Bus Interface A. SN65HVDA54x devices pin 5 is VIO.• GMW3122 Dual-WireCAN PhysicalLayer SN65HVDA54x-5 devicespin5 isNC and• ISO 11783 Standard Data Bus Interface VIO isinternallyconnectedtoVCC .
NMEA 2000 Standard Data Bus Interface B. SN65HVDA54x-5 devices:VIO isinternally connectedtoVCC Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2009–2010,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SN65HVDA540-Q1,SN65HVDA541-Q1,SN65HVDA542-Q1 SN65HVDA540-5-Q1,SN65HVDA541-5-Q1,SN65HVDA542-5-Q1 SLLS804B –MARCH 2009–REVISED SEPTEMBER 2010 www.ti.com This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. TERMINAL FUNCTIONS TERMINAL D DSJ TYPE DESCRIPTIONPackage PackageNAME (SOIC) (VSON) NO. NO. TXD 1 1 I CAN transmitdatainput(lowfordominantbus state,highforrecessivebus state) GND 2 2 GND Ground connection VCC 3 3 Supply Transceiver5V supplyvoltage RXD 4 4 O CAN receivedataoutput(lowindominantbus state,highinrecessivebus state) HVDA54x: Transceiverlogiclevel(IO)supplyvoltageVIO /NC 5 5 Supply HVDA54x-5: No connect CANL 6 10 I/O Low levelCAN bus line CANH 7 11 I/O HighlevelCAN bus line Mode select: STB /S 8 12 I STB, Standbymode (SN65HVDA540/541) selectpin(activehigh) S,Silentmode (SN65HVDA542) selectpin(activehigh) NC N/A 6,7,8,9 NC No connect ORDERING INFORMATION (1) TA PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING HVDA540QDRQ1 H540Q HVDA541QDRQ1 H541Q HVDA542QDRQ1 H542Q –40°C to125°C SOIC – D Reelof2500 HVDA5405QDRQ1 H5405Q HVDA5415QDRQ1 H5415Q HVDA5425QDRQ1 H5425Q HVDA540QDSJRQ1 (3) H540Q –40°C to125°C VSON – DSJ Reelof3000 HVDA541QDSJRQ1 (3) H541Q (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee theTI web siteatwww.ti.com. (2) Package drawings,thermaldata,and symbolizationareavailableatwww.ti.com/packaging. (3) ProductPreview

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B A: Normal Mode B: Low Power Standby Mode CANH CANL Recessive Dominant Recessive Time, t Typical Bus Voltage Low Power Standby Mode CANL CANH Vdiff Vdiff Normal & Silent Mode SN65HVDA540-Q1,SN65HVDA541-Q1,SN65HVDA542-Q1 SN65HVDA540-5-Q1,SN65HVDA541-5-Q1,SN65HVDA542-5-Q1 www.ti.com SLLS804B –MARCH 2009–REVISED SEPTEMBER 2010 FUNCTIONAL DESCRIPTION GeneraralDescription The devicemeets or exceeds thespecificationsoftheISO 11898 High Speed CAN (ControllerArea Network) PhysicalLayer standard(transceiver).This deviceprovidesCAN transceiverfunctions:differentialtransmit capabilityto the bus and differentialreceivecapabilityat data ratesup to 1 megabitper second (Mbps).The deviceincludesmany protectionfeaturesprovidingdeviceand CAN networkrobustness. OperatingModes The devicehas two main operatingmodes: normalmode (alldevices)and standbymode (SN65HVDA540 /541) orsilentmode (SN65HVDA542). Operatingmode selectionismade viatheSTB (SN65HVDA540 /541)ortheS (SN65HVDA542) inputpin. Table1.OperatingModes DEVICE STB /S MODE DRIVER RECEIVER RXD Pin AllDevices LOW Normal Mode Enabled(On) Enabled(On) Mirrorsbus state(1) StandbyMode (NoSN65HVDA540 HIGH Disabled(Off) Disabled(Off) Recessive(HIGH)Wake Up) StandbyMode Low power wake-up SN65HVDA541 HIGH (RXD Wake Up Disabled(Off) receiverand bus Mirrorsbus stateviawake-up filter(2) Request) monitorenabled SN65HVDA542 HIGH SilentMode Disabled(Off) Enabled(On) Mirrorsbus state(1) (1) Mirrorsbus state:LOW ifCAN bus isdominant,HIGH ifCAN bus isrecessive. (2) See Figure3 and Figure4 foroperationofthelowpower wake up receiverand bus monitorforRXD Wake Up Requestbehaviorand Table3 forthewake up receiverthresholdlevels. Bus Statesby Mode The CAN bus has threevalidstatesduringpowered operationdependingon themode ofthedevice.Innormal mode thebus may be dominant(logicLOW) where thebus linesaredrivendifferentiallyapartorrecessive(logic HIGH) where thebus linesarebiasedtoVCC /2viathehigh-ohmicinternalinputresistorsR IN ofthereceiver.The thirdstateislowpower standbymode where thebus lineswillbe biasedtoGND viathehigh-ohmicinternalinput resistorsR IN ofthereceiver. Figure1.Bus States(PhysicalBitRepresentation) Figure2.SimplifiedCommon Mode Bias and ReceiverImplementation Normal Mode Thisisthe normal operatingmode of the device.Itisselectedby settingSTB or S low.The CAN driverand receiverarefullyoperationaland CAN communicationisbi-directional.The driveristranslatinga digitalinputon TXD toa differentialoutputon CANH and CANL. The receiveristranslatingthedifferentialsignalfrom CANH and CANL toa digitaloutputon RXD. InrecessivestatetheCAN bus pins(CANH and CANL) arebiasedto0.5 × VCC .Indominantstatethebus pinsaredrivendifferentiallyapart.Logichighisequivalenttorecessiveon the bus and logiclowisequivalenttoa dominant(differential)signalon thebus. Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1

Standby Mode, STB = High <tBUS <tBUS <tBUStBUS tBUS STB RXD Bus VDiff Standby Mode, STB = High <tClear <tBUS tBUS tBUS tClear tBUS tBUS SN65HVDA540-Q1,SN65HVDA541-Q1,SN65HVDA542-Q1 SN65HVDA540-5-Q1,SN65HVDA541-5-Q1,SN65HVDA542-5-Q1 SLLS804B –MARCH 2009–REVISED SEPTEMBER 2010 www.ti.com Standby Mode (SN65HVDA540) Thisisthelow power mode ofthedevice.Itisselectedby settingSTB high.The CAN driverand receiverare turnedoffand bi-directionalCAN communicationis not possible.There is no wake up capabilityin the SN65HVDA540, the RXD pinwillremain recessive(high)whilethe deviceisinstandbymode. Thisstateis suppliedviathe VIO supply,thusthe VCC (5V)supplymay be turnedoffforadditionalpower savingsat the system level.The localprotocolcontroller(MCU) should reactivatethe deviceto normal mode to enable communicationviatheCAN bus.The 5 V (VCC )supplyneeds tobe reactivatedby thelocalprotocolcontrollerto resume normalmode ifithas been turnedoffforlow-powerstandbyoperation.The CAN bus pinsare weakly pulledtoGND, see Figure1 and Figure2. Standby Mode withRXD Wake Up-Request (SN65HVDA541) Thisisthelow power mode ofthedevice.Itisselectedby settingSTB high.The CAN driverand main receiver are turnedoffand bi-directionalCAN communicationisnotpossible.The low power receiverand bus monitor, bothsuppliedviatheVIO supply,areenabledtoallowforRXD wake up requestsviatheCAN bus.The VCC (5V) supplymay be turnedoffforadditionalpower savingsatthesystem level.A wake up requestwillbe outputto RXD (drivenlow)forany dominantbus transmissionslongerthanthefiltertimetBUS .The localprotocolcontroller (MCU) shouldmonitorRXD fortransitionsand thenreactivatethedevicetonormalmode based on thewake up request.The 5 V (VCC )supplyneeds tobe reactivatedby thelocalprotocolcontrollertoresume normalmode ifit has been turnedoffforlow-powerstandbyoperation.The CAN bus pinsareweaklypulledtoGND, see Figure1 and Figure2. RXD Wake Up Request Lock Out forBus Stuck Dominant Fault(SN65HVDA541) Ifthebus has a faultconditionwhere itisstuckdominantwhiletheSN65HVDA541 isplacedintostandbymode viatheSTB pin,thedevicelocksouttheRXD wake up requestuntilthefaulthas been removed topreventfalse wake up signalsinthesystem. Figure3. SN65HVDA541 RXD Wake Up Request With No Bus FaultCondition Figure4. SN65HVDA541 RXD Wake Up Request Lock Out When Bus Dominant FaultCondition Silent(ReceiveOnly)Mode (SN65HVDA542) Thisisthesilent(receiveonly)mode ofthedevice.Itisselectedby settingS high.The CAN driveristurnedoff whilethereceiverremainsactiveand RXD willoutputthereceivedbus state.There isno low power mode inthe SN65HVDA542 exceptforVCC and VIO supplyundervoltageconditions(seeUndervoltageLockout/Unpowered Devicesectionofthedatasheet).

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SN65HVDA540-Q1,SN65HVDA541-Q1,SN65HVDA542-Q1 SN65HVDA540-5-Q1,SN65HVDA541-5-Q1,SN65HVDA542-5-Q1 www.ti.com SLLS804B –MARCH 2009–REVISED SEPTEMBER 2010 Driverand ReceiverFunctionTables Table2.DriverFunctionTable INPUTS OUTPUTS DRIVEN BUS STATEDEVICE STB /S (1) TXD (1) CANH (1) CANL (1) AllDevices L L H L Dominant L H Z Z Recessive L Open Z Z Recessive SN65HVDA540/541 (2) H X Y Y Recessive SN65HVDA542 (3) H X Z Z Recessive (1) H = highlevel,L = lowlevel,X = irrelevant,Y = common mode biastoGND, Z = common mode bias toVCC /2.See Figure1 and Figure2 forcommon mode biasinformation. (2) SN65HVDA540/541 have internalpullup toVIO on STB pin.IfSTB pinisopen thepinwillbe pulled highand thedevicewillbe instandbymode. (3) SN65HVDA542 has internalpulldown toGND on S pin.IfS pinisopen thepinwillbe pulledlowand thedevicewillbe innormalmode. Table3.ReceiverFunctionTable CAN DIFFERENTIAL INPUTSDEVICE MODE BUS STATE RXD PIN(1) VID = V(CANH) – V(CANL) STANDBY X X H (SN65HVDA540) (2) STANDBY WITH VID ≥ 1.15V DOMINANT L RXD WAKE UP 0.4V < VID < 1.15V ? ?REQUEST VID ≤ 0.4V RECESSIVE H(SN65HVDA541) (3) NORMAL OR VID ≥ 0.9V DOMINANT L SILENT 0.5V < VID < 0.9V ? ? VID ≤ 0.5V RECESSIVE H ANY Open N/A H (1) H = highlevel,L = lowlevel,X = irrelevant,? = indeterminate. (2) WhileSTB ishigh(standbymode) theRXD outputoftheSN65HVDA540 isalwayshigh(recessive) because ithas no wake-up receiver. (3) WhileSTB ishigh(standbymode) theRXD outputoftheSN65HVDA541 functionsaccordingtothe levelsabove and thewake-up conditionsshown inFigure3 and Figure4. DigitalInputsand Outputs The SN65HVDA54x deviceshave an I/Osupplyvoltageinputpin(VIO)toratiometricallylevelshiftthedigitallogic inputand outputlevelswithrespecttoVIO forcompatibilitywithprotocolcontrollershavingI/Osupplyvoltages between 3 V and 5.33V. The SN65HVDA54x-5 deviceshave a singleVCC supply(5V).The digitallogicinputand outputlevelsforthese devicesare withrespectto VCC forcompatibilitywithprotocolcontrollershavingI/Osupplyvoltagesbetween 4.68V and 5.33V. Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1

SN65HVDA540-Q1,SN65HVDA541-Q1,SN65HVDA542-Q1 SN65HVDA540-5-Q1,SN65HVDA541-5-Q1,SN65HVDA542-5-Q1 SLLS804B –MARCH 2009–REVISED SEPTEMBER 2010 www.ti.com ProtectionFeatures TXD Dominant StateTime Out Duringnormalmode, theonlymode where theCAN driverisactive,theTXD dominanttimeoutcircuitprevents thetransceiverfrom blockingnetworkcommunicationineventofa hardwareor softwarefailurewhere TXD is helddominantlongerthanthetimeoutperiodt(DOM) .The dominanttimeoutcircuitistriggeredby a fallingedge on TXD. Ifno risingedge isseen beforethetimeoutconstantofthecircuitexpires(t(DOM) )theCAN bus driveris disabledfreeingthebus forcommunicationbetween othernetworknodes.The CAN driverisre-activatedwhen a recessivesignalisseen on TXD pin,thusclearingthedominantstatetimeout.The CAN bus pinswillbe biased torecessivelevelduringa TXD dominantstatetimeout. APPLICATION NOTE: The maximum dominantTXD timeallowedby theTXD Dominant statetimeoutlimitsthe minimum possibledatarateofthedevice.The CAN protocolallowsa maximum ofelevensuccessivedominant bits(on TXD) forthe worstcase,where fivesuccessivedominant bitsare followedimmediatelyby an error frame.This,alongwiththet(DOM) minimum, limitstheminimum bitrate.The minimum bitratemay be calculated by:Minimum BitRate = 11/t(DOM) Thermal Shutdown Ifthe junctiontemperatureof the deviceexceeds the thermalshutdown thresholdthe devicewillturnoffthe CAN drivercircuits.This conditionis clearedonce the temperaturedrops below the thermalshut down temperatureofthedevice.The CAN bus pinswillbe biasedtorecessivelevelduringa thermalshutdown. UndervoltageLockout /Unpowered Device Both ofthesupplypinshave undervoltagedetectionwhich placethedeviceinforcedstandbymode toprotect thebus duringan undervoltageeventon eithertheVCC orVIO supplypins.IfVIO isundervoltagetheRXD pinis tri-statedand thedevicedoes notpass any wake-up signalsfrom thebus totheRXD pin.Sincethedeviceis placedintoforcedstandbymode theCAN bus pinshave a common mode biastoground protectingtheCAN network,see Figure1 and Figure2. The deviceisdesignedtobe an "idealpassive" loadtotheCAN bus ifitisunpowered.The bus pins(CANH, CANL) have extremelylow leakagecurrentswhen thedeviceisun-poweredso theywillnotloaddown thebus butratherbe "no load".Thisiscritical,especiallyifsome nodes ofthenetworkwillbe unpowered whiletherest ofthenetworkremainsinoperation. APPLICATION NOTE: Once an undervoltageconditionisclearedand theVCC and VIO have returnedtovalid levelsthedevicewilltypicallyneed 300 µs totransitiontonormaloperation. Table4.UndervoltageProtection DEVICE VCC VIO DEVICE STATE BUS RXD Common modeSN65HVDA540 ForcedStandbyMode HIGH (Recessive)biastoGND (1) Common mode Mirrorsbus stateviawake-upSN65HVDA541 Bad Good ForcedStandbyMode biastoGND (1) filter(2) Common modeSN65HVDA542 ForcedStandbyMode HIGH (Recessive)biastoGND (1) Common modeSN65HVDA54x Good Bad ForcedStandbyMode (3) tri-statebiastoGND (1) Common modeSN65HVDA54x-5 Bad N/A ForcedStandbyMode HIGH (Recessive)ortri-statebiastoGND (1) AllDevices Unpowered Unpowered No Load HighZ (1) See Figure1 and Figure2 forcommon mode biasinformation. (2) See Figure3 and Figure4 foroperationofthelowpower wake up receiverand bus monitorforRXD Wake Up Requestbehaviorand Table3 forthewake up receiverthresholdlevels. (3) When VIO isundervoltage,thedeviceisforcedintostandbymode withrespecttotheCAN bus sincethereisnota validdigitalreference todeterminethedigitalI/Ostatesorpower thewake-up receiver.

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SN65HVDA540-Q1,SN65HVDA541-Q1,SN65HVDA542-Q1 SN65HVDA540-5-Q1,SN65HVDA541-5-Q1,SN65HVDA542-5-Q1 www.ti.com SLLS804B –MARCH 2009–REVISED SEPTEMBER 2010 FloatingPins The devicehas integratedpullup and pulldowns on criticalpinstoplacethedeviceintoknown statesifthepins float.The TXD pinispulledup toVIO toforcea recessiveinputlevelifthepinfloats.The STB ispulledup tothe IO supplypin,VIO(SN65HVDA540 and SN65HVDA541), or VCC (SN65HVDA540-5 and SN65HVDA541-5) to forcethe deviceinstandbymode (lowpower) ifthe pinfloats.The S pinispulleddown to GND to forcethe deviceintonormalmode ifthepinfloats(SN65HVDA542 and SN65HVDA542-5). CAN Bus ShortCircuitCurrentLimiting The devicehas severalprotectionfeaturesthatlimitthe shortcircuitcurrentwhen a CAN bus lineisshorted. These includeCAN drivercurrentlimiting(dominantand recessive)and TXD dominantstatetimeouttoprevent continuouslydrivingdominant.DuringCAN communicationthe bus switchesbetween dominantand recessive states,thusthe shortcircuitcurrentmay be viewed eitheras the currentduringeach bus stateor as a DC average current.For system currentand power considerationsin terminationresistanceand common mode choke ratingsthe average shortcircuitcurrentshouldbe used.The devicehas TXD dominantstatetimeout whichpreventspermanentlyhavingthehighershortcircuitcurrentofdominantstate.The CAN protocolalsohas forcedstatechanges and recessivebitssuch as bitstuffing,controlfields,and interframespace.These ensure thereisa minimum recessiveamount of timeon the bus even ifthe data fieldcontainsa highpercentageof dominantbits. APPLICATION NOTE: The shortcircuitcurrentofthebus depends on theratioofrecessivetodominantbitsand theirrespectiveshortcircuitcurrents.The average shortcircuitcurrentmay be calculatedwiththe following formula: IOS(AVG) = %Transmit*[(%REC_Bits*IOS(SS)_REC )+ (%DOM_Bits *IOS(SS)_DOM )]+ [%Receive*IOS(SS)_REC ] Where IOS(AVG) istheaverageshortcircuitcurrent,%Transmitisthepercentagethenode istransmittingCAN messages, %Receive isthepercentagethenode isreceivingCAN messages, %REC_Bits isthepercentage ofrecessivebitsinthetransmittedCAN messages, %DOM_Bits isthepercentageofdominantbitsinthe transmittedCAN messages, IOS(SS)_REC istherecessivesteadystateshortcircuitcurrentand IOS(SS)_DOM is thedominantsteadystateshortcircuitcurrent. PCB and Thermal ConsiderationsforVSON Package The VSON package versonofthisdevicehas an exposed thermalpad whichshouldbe connectedwithviastoa thermalplane.Even thoughthispad isnotelectricallyconnectedinternallyitisrecommended thattheexposed pad be connectedtotheGND plane.Pleaserefertothemechanicalinformationon thepackage attheend of thisdatasheetand applicationreportSLUA271 "QFN/SON PCB Attachement" formore informationon proper use ofthispackage. Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1

SN65HVDA540-Q1,SN65HVDA541-Q1,SN65HVDA542-Q1 SN65HVDA540-5-Q1,SN65HVDA541-5-Q1,SN65HVDA542-5-Q1 SLLS804B –MARCH 2009–REVISED SEPTEMBER 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS (1)(2) 1.1 VCC Supplyvoltagerange –0.3V to6 V 1.2 VIO I/Osupplyvoltagerange –0.3V to6 V Voltagerangeatbus terminals(CANH,1.3 –27 V to40 VCANL)

1.4 IO Receiveroutputcurrent(RXD) 20 mA

SN65HVDA54x –0.3V to6 V and VI≤ VIO + 0.3V

1.5 VI Voltageinputrange(TXD,STB, S)

SN65HVDA54x-5 –0.3V to6 V Operatingvirtual-junctiontemperature1.6 TJ –40°C to150°Crange Lead temperature(soldering,101.7 TLEAD 260°Cseconds) (1) Stressesbeyond thoselistedunder"absolutemaximum ratings"may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder"recommended operating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) Allvoltagevalues,exceptdifferentialI/Obus voltages,arewithrespecttogroundterminal. ELECTROSTATIC DISCHARGE AND TRANSIENT PROTECTION (1) PARAMETER TEST CONDITIONS VALUE

2.1 CANH and CANL (3) ±12 kV

Human-Body Model(2)

2.2 Allpins ±4 kV

2.3 Charged-DeviceModel(4) Allpins ±1 kVElectrostaticDischarge

2.4 Machine Model(5) ±200 V

IEC 61000-4-2accordingtoIBEE CAN ±7 kV2.5 CANH and CANL pinstoGNDEMC TestSpecification(6)

2.6 Pulse1 -100V

2.7 Pulse2a +75 VISO7637 transientsaccordingtoIBEEISO 7637 Transients CAN EMC TestSpecification(7)

2.8 Pulse3a -150V

2.9 Pulse3b +100 V

(1) Stressesbeyond thoselistedunder"electrostaticdischargeand transientprotection"may cause permanentdamage tothedevice. These arestressratingsonly,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder "recommended operatingconditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affect devicereliability. (2) HBM TestedinaccordancewithAEC-Q100-002. (3) HBM testmethod based on AEC-Q100-002, CANH and CANL bus pinsstressedwithrespecttoeach otherand GND. (4) CDM TestedinaccordancewithAEC-Q100-011. (5) MM TestedinaccordancewithAEC-Q100-003. (6) IEC 61000-4-2isa systemlevelESD test.ResultsgivenherearespecifictotheIBEE CAN EMC Testspecificationconditions.Different systemlevelconfigurationswillleadtodifferentresults. (7) ISO 7637 isa systemleveltransienttest.ResultsgivenherearespecifictotheIBEE CAN EMC Testspecificationconditions.Different systemlevelconfigurationswillleadtodifferentresults. RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT 3.1 VCC Supplyvoltage 4.68 5.33 V 3.2 VIO I/Osupplyvoltage 3 5.33 V

3.3 VIorVIC Voltageatany bus terminal(separatelyorcommon mode) –12 12 V

3.4 VIH High-levelinputvoltage TXD, STB, S(forSN65HVD54x-5: VIO = VCC ) 0.7× VIO VIO V 3.5 VIL Low-levelinputvoltage TXD, STB, S (forSN65HVD54x-5: VIO = VCC ) 0 0.3× VIO V

3.6 VID Differentialinputvoltage,bus Between CANH and CANL –6 6 V

3.7 IOH High-leveloutputcurrent RXD –2 mA

3.8 IOL Low-leveloutputcurrent RXD 2 mA

Operatingambientfree-air3.9 TA See ThermalCharacteristicstable -40 125 °Ctemperature

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ELECTRICAL CHARACTERISTICS

overrecommended operatingconditions,TJ = –40°C to150°C (unlessotherwisenoted),SN65HVDA54x-5 devicesVIO = VCC PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT Supply Characteristics(SN65HVDA54x) Standby mode STB atVIO,VCC = 5.33V,VIO = 3 V,4.1 (SN65HVDA 5 µATXD atVIO (2) Only) Normal mode TXD at0 V,60-Ω load,STB /S at04.2 50 70ICC 5-V supplycurrent (Dominant) V Normal mode TXD atVIO,No load,STB /S at0 V4.3 5.5 10(Recessive) orS atVIO mA SilentMode TXD atVIO,No load,STB /S at0 V4.4 (SN65HVDA 5.5 10orS atVIO542 only) Standby mode STB atVIO ,VCC = 5.33V or0 V,4.5 (SN65HVDA 7 15RXD floating,TXD atVIO540/541 Only) Normal modeIIO I/Osupplycurrent µA

542 Only)

Undervoltagedetectionon VCC for4.7 UV VCC 3.2 3.6 4 Vforcedstandbymode Hysteresisvoltagefor

4.8 VHYS(UVVCC) undervoltagedetectionon UV VCC 200 mV

Undervoltagedetectionon VIO for4.9 UV VIO 1.9 2.45 2.95 Vforcedstandbymode Hysteresisvoltagefor

4.10 VHYS(UVVIO) undervoltagedetectionon UV VIO 130 mV

Supply Characteristics(SN65HVDA54x-5) Standby mode STB atVCC ,VCC = 5.33V,4.1-5 (SN65HVDA 20 µATXD atVCC (2) 540-5/541-5 Only) Normal mode TXD at0 V,60-Ω load,STB /S at04.2-5 50 70ICC 5-V supplycurrent (Dominant) V Normal mode TXD atVIO,No load,STB /S at0 V4.3-5 5.5 10(Recessive) orS atVIO mA SilentMode TXD atVIO,No load,STB /S at0 V4.4-5 (SN65HVDA 5.5 10orS atVIO542 only) Undervoltagedetectionon VCC for4.7-5 UV VCC 3.2 3.6 4 Vforcedstandbymode Hysteresisvoltagefor 4.8-5 VHYS(UVVCC) undervoltagedetectionon UV VCC 240 mV forstandbymode (1) Alltypicalvaluesareat25°C and supplyvoltagesofVCC = 5 V and VIO = 3.3V. (2) The VCC supplyisnotneeded duringstandbymode so intheapplicationICC instandbymode may be zero.IftheVCC supplyremains, thenICC isperspecificationwithVCC . Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1

SN65HVDA540-Q1,SN65HVDA541-Q1,SN65HVDA542-Q1 SN65HVDA540-5-Q1,SN65HVDA541-5-Q1,SN65HVDA542-5-Q1 SLLS804B –MARCH 2009–REVISED SEPTEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) overrecommended operatingconditions,TJ = –40°C to150°C (unlessotherwisenoted),SN65HVDA54x-5 devicesVIO = VCC PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT Device SwitchingCharacteristics:PropagationTime (Loop Time TXD toRXD) Totalloopdelay,driverinput 5.1 tPROP(LOOP1) (TXD) toreceiveroutput(RXD), 70 230 recessivetodominant Figure12,STB at0 V ns Totalloopdelay,driverinput 5.2 tPROP(LOOP2) (TXD) toreceiveroutput(RXD), 70 230 dominanttorecessive DriverElectricalCharacteristics VI= VIO,VIO = 3 V,STB at0 V orS 6.3 VO(R) Bus outputvoltage(recessive) atX (3),R L = 60 Ω,See Figure5 and 2 2.5 3 V Figure1 Bus outputvoltage,standbymode STB /S atVIO,R L = 60 Ω,6.4 VO(STBY) (SN65HVDA540, SN65HVDA541 –0.1 0.1 VSee Figure5 and Figure1only) VI= 0 V,R L = 60 Ω,STB /S at0 V,6.5 1.5 3See Figure5,Figure1,and Figure6DifferentialoutputvoltageVOD(D) V(dominant) VI= 0 V,R L = 45 Ω,STB /S at0 V,6.6 1.4 3See Figure5,Figure1,and Figure6 VI= 3 V,STB /S at0 V,R L = 60 Ω,6.7 –0.012 0.012Differentialoutputvoltage See Figure5 and Figure1VOD(R) V(recessive) 6.8 VI= 3 V,STB /S at0 V,No load –0.5 0.05 Outputsymmetry (dominantor STB /S at0 V,R L = 60 Ω,6.9 VSYM 0.9VCC VCC 1.1VCC Vrecessive)(VO(CANH) + VO(CANL) ) See Figure15 Steady-statecommon-mode STB /S at0 V,R L = 60 Ω,6.10 VOC(SS) 2 2.5 3 Voutputvoltage See Figure11 Change insteady-state STB /S at0 V,R L = 60 Ω,6.11 ΔVOC(SS) 40 mVcommon-mode outputvoltage See Figure11 VCANH = 0 V,CANL open,TXD = 6.12 low, -100 Short-circuitsteady-stateoutput See Figure14IOS(SS)_DOM mAcurrent,Dominant VCANL = 32 V,CANH open,TXD =6.13 100low,See Figure14 –20 V ≤ VCANH ≤ 32 V,CANL open,6.14 -10 10TXD = high,See Figure14Short-circuitsteady-stateoutputIOS(SS)_REC mAcurrent,Recessive –20 V ≤ VCANL ≤ 32 V,CANH open,6.15 -10 10TXD = high,See Figure14

6.16 C O Outputcapacitance See receiverinputcapacitance

(3) FortheSN65HVDA542 devicethebus outputvoltage(recessive)willbe thesame ifthedeviceisinnormalmode withS pinat0 V orif thedeviceisinsilentmode withtheS pinatHIGH.

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ProductFolderLink(s):SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1

SN65HVDA540-Q1,SN65HVDA541-Q1,SN65HVDA542-Q1 SN65HVDA540-5-Q1,SN65HVDA541-5-Q1,SN65HVDA542-5-Q1 www.ti.com SLLS804B –MARCH 2009–REVISED SEPTEMBER 2010 ELECTRICAL CHARACTERISTICS (continued) overrecommended operatingconditions,TJ = –40°C to150°C (unlessotherwisenoted),SN65HVDA54x-5 devicesVIO = VCC PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT DriverSwitchingCharacteristics Propagationdelaytime,7.1 tPLH STB /S at0 V,See Figure7 65 nslow-to-highleveloutput Propagationdelaytime,7.2 tPHL STB /S at0 V,See Figure7 50 nshigh-to-lowleveloutput 7.3 tR Differentialoutputsignalrisetime STB /S at0 V,See Figure7 25 ns 7.4 tF Differentialoutputsignalfalltime STB /S at0 V,See Figure7 55 ns Enabletimefromstandbyorsilent7.5 tEN See Figure10 20 µsmode tonormalmode dominant 7.6 t(DOM) (4) Dominanttimeout See Figure13 300 400 700 µs ReceiverElectricalCharacteristics Positive-goinginputthreshold8.1 VIT+ STB /S at0 V,See Table5 800 900 mVvoltage,normalmode Negative-goinginputthreshold8.2 VIT– STB /S at0 V,See Table5 500 650 mVvoltage,normalmode

8.3 Vhys Hysteresisvoltage(VIT+ – VIT–) 100 125 mV

Inputthresholdvoltage,

8.4 VIT(STBY) standbymode (SN65HVDA541 STB atVIO 400 1150 mV

only) Power-off(unpowered)bus input CANH = CANL = 5 V,VCC at0 V,8.5 II(OFF_LKG) 3 µAleakagecurrent VIO at0 V,TXD at0 V SN65HVDA54x: TXD atVIO,VIO at Inputcapacitancetoground 3.3V.8.6 C I 13 pF(CANH orCANL) SN65HVDA54x-5: TXD atVCC VI= 0.4sin(4E6pt)+ 2.5V SN65HVDA54x: TXD atVIO,VIO at 3.3V.8.7 C ID Differentialinputcapacitance 5 pFSN65HVDA54x-5: TXD atVCC VI= 0.4sin(4E6pt)

8.8 R ID Differentialinputresistance SN65HVDA54x: TXD atVIO,VIO = 29 80 kΩ

3.3V,STB at0 V SN65HVDA54x-5: TXD atVCC ,8.9 R IN Inputresistance(CANH orCANL) 14.5 25 40 kΩ STB at0 V Inputresistancematching8.10 R I(M) V(CANH) = V(CANL) –3 0 3 %[1– ® IN(CANH)/RIN(CANL))]× 100% ReceiverSwitchingCharacteristics Propagationdelaytime,9.1 tPLH STB /S at0 V ,See Figure9 95 nslow-to-high-leveloutput Propagationdelaytime,9.2 tPHL STB /S at0 V ,See Figure9 60 nshigh-to-low-leveloutput 9.3 tR Outputsignalrisetime STB /S at0 V ,See Figure9 13 ns 9.4 tF Outputsignalfalltime STB /S at0 V ,See Figure9 10 ns Dominanttimerequiredon bus for 9.5 tBUS wake-up fromstandby 1.5 5 µs (SN65HVDA541 only) STB atVIO,See Figure3 andRecessivetimeon thebus toclear Figure4thestandbymode receiveroutput 9.6 tCLEAR (RXD) ifstandbymode isentered 1.5 5 µs whilebus isdominant (SN65HVDA541 only) (4) The TXD dominanttimeout(t(DOM) )disablesthedriverofthetransceiveronce theTXD has been dominantlongerthant(DOM) ,which releasesthebus linestorecessive,preventinga localfailurefromlockingthebus dominant.The drivermay onlytransmitdominant againafterTXD has been returnedHIGH (recessive).Whilethisprotectsthebus fromlocalfaults,lockingthebus dominant,itlimitsthe minimum dataratepossible.The CAN protocolallowsa maximum ofelevensuccessivedominantbits(onTXD) fortheworstcase, where fivesuccessivedominantbitsarefollowedimmediatelyby an errorframe.This,alongwiththet(DOM) minimum, limitsthe minimum bitrate.The minimum bitratemay be calculatedby:Minimum BitRate = 11/t(DOM) = 11 bits/300 µs = 37 kbps Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1

10.4 IIL Low-levelinputcurrent TXD at0 V –100 -7 µA

IO = –2 mA, See Figure911.1 VOH High-leveloutputvoltage 0.8× VIO VSN65HVD54x-5: VIO = VCC IO = 2 mA, See Figure911.2 VOL Low-leveloutputvoltage 0.2× VIO VSN65HVD54x-5: VIO = VCC STB Pin Characteristics(SN65HVDA540 and SN65HVDA541 Only) 12.1 VIH High-levelinputvoltage SN65HVD54x-5: VIO = VCC 0.7× VIO V 12.2 VIL Low-levelinputvoltage SN65HVD54x-5: VIO = VCC 0.3× VIO V SN65HVDA54x: STB atVIO12.3 IIH High-levelinputcurrent –2 2 µASN65HVDA54x-5: STB atVCC

12.4 IIL Low-levelinputcurrent STB at0 V –20 µA

S Pin Characteristics(SN65HVDA542 Only) 13.1 VIH High-levelinputvoltage SN65HVD54x-5: VIO = VCC 0.7× VIO V 13.2 VIL Low-levelinputvoltage SN65HVD54x-5: VIO = VCC 0.3× VIO V SN65HVDA54x: S atVIO13.3 IIH High-levelinputcurrent 30 µASN65HVDA54x-5: S atVCC

13.4 IIL Low-levelinputcurrent S at0 V –2 2 µA

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ProductFolderLink(s):SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1

SN65HVDA540-Q1,SN65HVDA541-Q1,SN65HVDA542-Q1 SN65HVDA540-5-Q1,SN65HVDA541-5-Q1,SN65HVDA542-5-Q1 www.ti.com SLLS804B –MARCH 2009–REVISED SEPTEMBER 2010 THERMAL CHARACTERISTICS overrecommended operatingconditions,TJ = –40°C to150°C (unlessotherwisenoted),SN65HVDA54x-5 devicesVIO = VCC THERMAL METRIC (1)(2) TEST CONDITIONS MIN TYP MAX UNIT THERMAL METRIC -SOIC 'D 'PACKAGE 14.1-D Low-K thermalresistance(3) 140Junction-to-airthermalqJA resistance14.2-D High-Kthermalresistance(4) 112 Junction-to-boardthermal14.3-D qJB 50resistance(5) Junction-to-case(top)thermal14.4-D qJC(TOP) 56resistance(6) °C/W Junction-to-case(bottom)14.5-D qJC(BOTTOM) N/Athermalresistance(7) Junction-to-top14.6-D ΨJT 13characterizationparameter(8) Junction-to-board14.7-D ΨJB 55characterizationparameter(9) THERMAL METRIC -VSON 'DSJ 'PACKAGE 14.1-DSJ Low-K thermalresistance(3) 290 Junction-to-airthermalqJA High-Kthermalresistance(withthermalresistance14.2-DSJ 52vias)(4) Junction-to-boardthermal14.3-DSJ qJB 14resistance(5) Junction-to-case(top)thermal14.4-DSJ qJC(TOP) 56resistance(6) °C/W Junction-to-case(bottom)14.5-DSJ qJC(BOTTOM) 4.5thermalresistance(7) Junction-to-top14.6-DSJ ΨJT 6characterizationparameter(8) Junction-to-board14.7-DSJ ΨJB 19characterizationparameter(9) AVERAGE POWER DISSIPATION AND THERMAL SHUTDOWN VCC = 5 V,VIO = VCC ,TJ = 27°C, R L = 60

14.8 STB at0 V,InputtoTXD at500 kHz, 140

50% dutycyclesquarewave, C L atRXD = 15 pF PD Averagepower dissipation mW VCC = 5.33V,VIO = VCC ,TJ = 130°C, R L = 60 Ω,STB at0 V,

14.9 InputtoTXD at500 kHz, 215

50% dutycyclesquarewave, C L atRXD = 15 pF Thermalshutdown 18514.10 °Ctemperature (1) Formore informationabouttraditionaland new thermalmetrics,see theIC Package ThermalMetricsapplicationreport,SPRA953 . (2) The junctiontemperature(TJ)iscalculatedusingthefollowingTJ = TA + (PD × qJA).qJAisPCB dependent,bothJEDEC-standardLow-K and High-Kvaluesaregivenas referencepointstostandardizedreferenceboards. (3) The junction-to-ambientthermalresistanceundernaturalconvectionisobtainedina simulationon a JEDEC-standard,Low-K board,as specifiedinJESD51-3,inan environmentdescribedinJESD51-2a. (4) The junction-to-ambientthermalresistanceundernaturalconvectionisobtainedina simulationon a JEDEC-standard,High-Kboard,as specifiedinJESD51-7,inan environmentdescribedinJESD51-2a. (5) The junction-to-boardthermalresistanceisobtainedby simulatinginan environmentwitha ringcoldplatefixturetocontrolthePCB temperature,as describedinJESD51-8. (6) The junction-to-case(top)thermalresistanceisobtainedby simulatinga coldplateteston thepackage top.No specific JEDEC-standardtestexists,buta closedescriptioncan be foundintheANSI SEMI standardG30-88. (7) The junction-to-case(bottom)thermalresistanceisobtainedby simulatinga coldplateteston theexposed (power)pad.No specific JEDEC standardtestexists,buta closedescriptioncan be foundintheANSI SEMI standardG30-88. (8) The junction-to-topcharacterizationparameter,ΨJT,estimatesthejunctiontemperatureofa deviceina realsystemand isextracted fromthesimulationdataforobtainingqJA,usinga proceduredescribedinJESD51-2a (sections6 and 7). (9) The junction-to-boardcharacterizationparameter,ΨJB estimatesthejunctiontemperatureofa deviceina realsystemand isextracted fromthesimulationdataforobtainingqJA ,usinga proceduredescribedinJESD51-2a (sections6 and 7). Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1

SN65HVDA540-Q1,SN65HVDA541-Q1,SN65HVDA542-Q1 SN65HVDA540-5-Q1,SN65HVDA541-5-Q1,SN65HVDA542-5-Q1 SLLS804B –MARCH 2009–REVISED SEPTEMBER 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION Figure5. DriverVoltage,Current,and TestDefinition Figure6. DriverVOD TestCircuit A. The inputpulseissuppliedby a generatorhavingthe followingcharacteristics:PRR ≤ 125 kHz, 50% dutycycle, tr ≤ 6 ns,tf≤ 6 ns,ZO = 50 Ω. B. C L includesinstrumentationand fixturecapacitancewithin±20%. C. ForSN65HVDA54x-5 deviceversions,VIO = VCC . Figure7. DriverTestCircuitand VoltageWaveforms Figure8. ReceiverVoltageand CurrentDefinitions

ProductFolderLink(s):SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1

SN65HVDA540-Q1,SN65HVDA541-Q1,SN65HVDA542-Q1 SN65HVDA540-5-Q1,SN65HVDA541-5-Q1,SN65HVDA542-5-Q1 www.ti.com SLLS804B –MARCH 2009–REVISED SEPTEMBER 2010 PARAMETER MEASUREMENT INFORMATION (continued) A. The inputpulseissuppliedby a generatorhavingthe followingcharacteristics:PRR ≤ 125 kHz, 50% dutycycle, tr ≤ 6 ns,tf≤ 6 ns,ZO = 50 Ω. B. C L includesinstrumentationand fixturecapacitancewithin±20%. C. C. ForSN65HVDA54x-5 deviceversionsVIO = VCC . Figure9. ReceiverTestCircuitand VoltageWaveforms Table5.DifferentialInputVoltageThresholdTest INPUT OUTPUT VCANH VCANL |VID| R –11.1V –12 V 900 mV L 12 V 11.1V 900 mV L VOL –6 V –12 V 6 V L

12 V 6 V 6 V L

–11.5V –12 V 500 mV H 12 V 11.5V 500 mV H –12 V –6 V 6 V H VOH

6 V 12 V 6 V H

A. C L = 100 pF includesinstrumentationand fixturecapacitancewithin±20%. B. AllVI inputpulsesarefrom0 V toVIO and suppliedby a generatorhavingthefollowingcharacteristics:tr ortf ≤ 6 ns. PulseRepetitionRate (PRR) = 25 kHz,50% dutycycle. C. C. ForSN65HVDA54x-5 deviceversionsVIO = VCC . Figure10. tEN TestCircuitand Waveforms Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1

SN65HVDA540-Q1,SN65HVDA541-Q1,SN65HVDA542-Q1 SN65HVDA540-5-Q1,SN65HVDA541-5-Q1,SN65HVDA542-5-Q1 SLLS804B –MARCH 2009–REVISED SEPTEMBER 2010 www.ti.com A. AllVI inputpulsesarefrom0 V toVIO and suppliedby a generatorhavingthefollowingcharacteristics:tr ortf ≤ 6 ns. PulseRepetitionRate (PRR) = 125 kHz,50% dutycycle. Figure11. Common-Mode Output VoltageTestand Waveforms A. C L = 100 pF includesinstrumentationand fixturecapacitancewithin±20%. B. AllVI inputpulsesarefrom0 V toVIO and suppliedby a generatorhavingthefollowingcharacteristics:tr ortf ≤ 6 ns. PulseRepetitionRate (PRR) = 125 kHz,50% dutycycle. C. ForSN65HVDA54x-5 deviceversions,VIO = VCC . Figure12. tPROP(LOOP) TestCircuitand Waveform A. C L = 100 pF includesinstrumentationand fixturecapacitancewithin±20%. B. AllVI inputpulsesarefrom0 V toVIO and suppliedby a generatorhavingthefollowingcharacteristics:tr ortf ≤ 6 ns. PulseRepetitionRate (PRR) = 500 Hz,50% dutycycle. C. ForSN65HVDA54x-5 deviceversions,VIO = VCC . Figure13. TXD Dominant Time Out TestCircuitand Waveforms

ProductFolderLink(s):SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1

SN65HVDA540-Q1,SN65HVDA541-Q1,SN65HVDA542-Q1 SN65HVDA540-5-Q1,SN65HVDA541-5-Q1,SN65HVDA542-5-Q1 www.ti.com SLLS804B –MARCH 2009–REVISED SEPTEMBER 2010 A. A.ForSN65HVDA54x-5 deviceversionsVIO = VCC . Figure14. DriverShort-CircuitCurrentTestand Waveforms A. AllVI inputpulsesare from 0 V toVIO and suppliedby a generatorhavingthefollowingcharacteristics:tr/tf ≤ 6 ns, PulseRepetitionRate (PRR) = 250 kHz,50% dutycycle. Figure15. DriverOutput Symmetry TestCircuit Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1

(e.g. TMS 470) SN65HVDA540 or SN65HVDA541 CAN Transceiver STB RXD TXD CANH CANL VIO Port x RXD TXD VIO 5 7 3 6 3.3-V Voltage Regulator (e.g. TPSxxxx) VIN VBATTERY VOUT GND 5-V Voltage Regulator (e.g. TPSxxxx) VIN VCC VOUT EN Port y VCORE VCORE MCU (e.g. TMS 470) SN65HVDA542 CAN Transceiver S RXD TXD CANH CANL VIO Port x RXD TXD VIO 5 7 3 6 3.3-V Voltage Regulator (e.g. TPSxxxx) VIN VIGNITION VOUT GND 5-V Voltage Regulator (e.g. TPSxxxx) VIN VCC VOUT VCORE VCORE SN65HVDA540-Q1,SN65HVDA541-Q1,SN65HVDA542-Q1 SN65HVDA540-5-Q1,SN65HVDA541-5-Q1,SN65HVDA542-5-Q1 SLLS804B –MARCH 2009–REVISED SEPTEMBER 2010 www.ti.com

APPLICATION INFORMATION

Figure16. TypicalApplicationUsing 3.3-VI/OVoltageLeveland Low-Power Mode (5-VVCC Not Needed inLow-Power Mode) Figure17. TypicalApplicationUsing 3.3-VI/OVoltageLeveland No Low-Power Mode

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SN65HVDA540-Q1,SN65HVDA541-Q1,SN65HVDA542-Q1 SN65HVDA540-5-Q1,SN65HVDA541-5-Q1,SN65HVDA542-5-Q1 www.ti.com SLLS804B –MARCH 2009–REVISED SEPTEMBER 2010 Figure18. TypicalApplicationUsing 5-V MCU and Low-Power Mode Figure19. TypicalApplicationUsing 5-V MCU and No Low-Power Mode Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1

www.ti.com 5-Sep-2011 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) HVDA5405QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM HVDA540QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM HVDA540QDSJRQ1 PREVIEW VSON DSJ 12 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR HVDA5415QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM HVDA541QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM HVDA541QDSJRQ1 PREVIEW VSON DSJ 12 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR HVDA5425QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM HVDA542QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

www.ti.com 5-Sep-2011 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN65HVDA540-Q1 :

Catalog: SN65HVDA540 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) HVDA5405QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA5405QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA540QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA540QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA5415QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA5415QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA541QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA541QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA5425QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA5425QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA542QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA542QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2

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Product Information

HVDA540QDSJRQ1 specifications and overview.

Summary

5-V CAN TRANSCEIVER WITH I/O LEVEL ADAPTING AND LOW-POWER MODE SUPPLY OPTIMIZATION

Description

5-V CAN TRANSCEIVER WITH I/O LEVEL ADAPTING AND LOW-POWER MODE SUPPLY OPTIMIZATION

Source title HVDA540QDSJRQ1 Datasheet(PDF) - Texas Instruments

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HVDA540QDSJRQ1

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SN65HVDA540-5-Q1 TI1 | Alldatasheet

Document overview

Technical content

APPLICATIONS

2 SubmitDocumentationFeedback Copyright© 2009–2010,Texas InstrumentsIncorporated

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1.4 IO Receiveroutputcurrent(RXD) 20 mA

1.5 VI Voltageinputrange(TXD,STB, S)

2.1 CANH and CANL (3) ±12 kV

2.2 Allpins ±4 kV

2.3 Charged-DeviceModel(4) Allpins ±1 kVElectrostaticDischarge

2.4 Machine Model(5) ±200 V

2.6 Pulse1 -100V

2.7 Pulse2a +75 VISO7637 transientsaccordingtoIBEEISO 7637 Transients CAN EMC TestSpecification(7)

2.8 Pulse3a -150V

2.9 Pulse3b +100 V

3.3 VIorVIC Voltageatany bus terminal(separatelyorcommon mode) –12 12 V

3.6 VID Differentialinputvoltage,bus Between CANH and CANL –6 6 V

3.7 IOH High-leveloutputcurrent RXD –2 mA

3.8 IOL Low-leveloutputcurrent RXD 2 mA

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ELECTRICAL CHARACTERISTICS

542 Only)

4.8 VHYS(UVVCC) undervoltagedetectionon UV VCC 200 mV

4.10 VHYS(UVVIO) undervoltagedetectionon UV VIO 130 mV

6.16 C O Outputcapacitance See receiverinputcapacitance

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8.3 Vhys Hysteresisvoltage(VIT+ – VIT–) 100 125 mV

8.4 VIT(STBY) standbymode (SN65HVDA541 STB atVIO 400 1150 mV

8.8 R ID Differentialinputresistance SN65HVDA54x: TXD atVIO,VIO = 29 80 kΩ

10.4 IIL Low-levelinputcurrent TXD at0 V –100 -7 µA

12.4 IIL Low-levelinputcurrent STB at0 V –20 µA

13.4 IIL Low-levelinputcurrent S at0 V –2 2 µA

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14.8 STB at0 V,InputtoTXD at500 kHz, 140

14.9 InputtoTXD at500 kHz, 215

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12 V 6 V 6 V L

6 V 12 V 6 V H

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APPLICATION INFORMATION

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HVDA540QDSJRQ1 specifications and overview.

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