HVD75

SN55HVD75-EP TI1 | Alldatasheet

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R A B R RE DE D D R A B R RE DE D D R D R RE DE D A B R D R RE DE D A B Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community SN55HVD75-EP SLOS913 –OCTOBER 2015 SN55HVD75-EP3.3-VSupplyRS-485WithIECESDProtection

1 Features 2 Applications

1• Bus I/O Protection • Factory Automation

• Telecommunications Infrastructure– >±15 kV HBM Protection
• Motion Control– >±12 kV IEC 61000-4-2 Contact Discharge – >±4 kV IEC 61000-4-4 Fast Transient Burst

3 Description• Extended Industrial Temperature Range

These devices have robust 3.3-V drivers and–55°C to 125°C receivers in a small package for demanding industrial

• Large Receiver Hysteresis (80 mV) for Noise applications. The bus pins are robust to ESD events Rejection with high levels of protection to human-body model and IEC contact discharge specifications.• Low Unit-Loading Allows Over 200 Connected Nodes Each of these devices combines a differential driver
• Low Power Consumption and a differential receiver which operate from a single 3.3-V power supply. The driver differential outputs– Low Standby Supply Current: < 2 µA and the receiver differential inputs are connected– ICC < 1 mA Quiescent During Operation internally to form a bus port suitable for half-duplex
• 5-V Tolerant Logic Inputs Compatible With (two-wire bus) communication. These devices feature a wide common-mode voltage range making the3.3-V or 5-V Controllers devices suitable for multi-point applications over long• Signaling Rate Options Optimized for: cable runs. These devices are characterized from250 kbps, 20 Mbps, 50 Mbps –55°C to 125°C.
• Available in a Small VSON Package Device Information(1)
• Supports Defense, Aerospace, and Medical PART NUMBER PACKAGE BODY SIZE (NOM)Applications: SN55HVD75-EP VSON (8) 3.00 mm × 3.00 mm– Controlled Baseline (1) For all available packages, see the orderable addendum at– One Assembly/Test Site the end of the data sheet.– One Fabrication Site – Available in Extended (–55°C to 125°C) Temperature Range – Extended Product Life Cycle – Extended Product-Change Notification – Product Traceability Typical Application Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SLOS913 –OCTOBER 2015 www.ti.com Table of Contents

4 Revision History

October 2015 * Initial release.

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R RE DE D VCC B A GND SN55HVD75-EP www.ti.com SLOS913 –OCTOBER 2015

5 Pin Configuration and Functions

NAME NO. A 6 Bus I/O Driver output or receiver input (complementary to B) B 7 Bus I/O Driver output or receiver input (complementary to A) D 4 Digital input Driver data input DE 3 Digital input Active-high driver enable GND 5 Reference potential Local device ground R 1 Digital output Receive data output RE 2 Digital input Active-low receiver enable VCC 8 Supply 3-V to 3.6-V supply

6 Specifications

6.1 Absolute Maximum Ratings

over recommended operating range (unless otherwise specified) (1) MIN MAX UNIT Supply voltage, VCC –0.5 5.5 V Voltage at A or B inputs –13 16.5 V Input voltage at any logic pin –0.3 5.7 V Voltage input, transient pulse, A and B, through 100 Ω –100 100 V Receiver output current –24 24 mA Junction temperature, TJ 170 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) All pins ±8000 Charged device model (CDM), per JEDEC specification All pins ±1500 JESD22-C101(2) JEDEC standard 22, test method A115 (machine model) All pins ±300ElectrostaticV(ESD) Vdischarge IEC 61000-4-2 ESD (air-gap discharge)(3) Pins 5 to 7 ±12000 IEC 61000-4-2 ESD (contact discharge) Pins 5 to 7 ±12000 IEC 61000-4-4 EFT (fast transient or burst) Pins 5 to 7 ±4000 IEC 60749-26 ESD HBM Pins 5 to 7 ±15000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. (3) By inference from contact discharge results, see Application and Implementation. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: SN55HVD75-EP

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6.3 Recommended Operating Conditions

VCC Supply voltage 3 3.3 3.6 V VI Input voltage at any bus terminal (separately or common mode)(1) –7 12 V VIH High-level input voltage (driver, driver enable, and receiver enable inputs) 2 VCC V VIL Low-level input voltage (driver, driver enable, and receiver enable inputs) 0 0.8 V VID Differential input voltage –12 12 V IO Output current, driver –60 60 mA IO Output current, receiver –8 8 mA RL Differential load resistance 54 60 Ω CL Differential load capacitance 50 pF 1/tUI Signaling rate 20 Mbps TA(2) Operating free-air temperature (see Thermal Information) –55 125 °C TJ Junction temperature –55 150 °C (1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet. (2) Operation is specified for internal (junction) temperatures up to 150°C. Self-heating due to internal power dissipation should be considered for each application. Maximum junction temperature is internally limited by the thermal shutdown (TSD) circuit which disables the driver outputs when the junction temperature reaches 170°C.

6.4 Thermal Information

THERMAL METRIC(1) DRB (VSON) UNIT

8 PINS

RθJA Junction-to-ambient thermal resistance 40.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 49.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 3.9 °C/W RθJB Junction-to-board thermal resistance 15.5 °C/W ψJT Junction-to-top characterization parameter 0.6 °C/W ψJB Junction-to-board characterization parameter 15.7 °C/W TTSD Thermal shutdown junction temperature — °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

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6.5 Electrical Characteristics

over recommended operating range (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RL = 60 Ω, 375 Ω on each output to See 1.5 2–7 V to 12 V Figure 6 Driver differential output|VOD| RL = 54 Ω (RS-485) 1.5 2 Vvoltage magnitude RL = 100 Ω (RS-422), TJ ≥ 0°C 2 2.5VCC ≥ 3.2 V Change in magnitude of Δ|VOD| driver differential output RL = 54 Ω, CL = 50 pF –50 0 50 mV voltage SeeSteady-state common-VOC(SS) 1 VCC/2 3 VFigure 7mode output voltage Change in differential ΔVOC driver output common- –50 0 50Center of two 27-Ω load resistorsmode voltage mV Peak-to-peak driver VOC(PP) common-mode output 200 voltage Differential outputCOD 15 pFcapacitance Positive-going receiver VIT+ differential input voltage See (1) –70 –20 mV threshold Negative-going receiver VIT– differential input voltage –200 –150 See (1) mV threshold Receiver differential VHYS input voltage threshold 50 80 mV hysteresis (VIT+ – VIT–) Receiver high-levelVOH IOH = –8 mA 2.4 VCC – 0.3 Voutput voltage Receiver low-levelVOL IOL = 8 mA 0.2 0.4 Voutput voltage Driver input, driver II enable, and receiver –2.75 2.75 µA enable input current Receiver output high-IOZ VO = 0 V or VCC, RE at VCC –1 1 µAimpedance current Driver short-circuitIOS –165 165 mAoutput current VCC = 3 to 3.6 V or VI = 12 V 75 150Bus input currentII VCC = 0 V µA(disabled driver) VI = –7 V –100 –40DE at 0 V Driver and receiver DE = VCC, RE = GND 750 950enabled No load Driver enabled, DE = VCC, RE = VCC 300 500receiver disabled No loadSupply currentICC µA(quiescent) Driver disabled, DE = GND, RE = GND 600 800receiver enabled No load Driver and receiver DE = GND, D = open 0.1 2disabled RE = VCC, No load Supply current See Typical Characteristics(dynamic) (1) Under any specific conditions, VIT+ is assured to be at least VHYS higher than VIT–. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: SN55HVD75-EP

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6.6 Switching Characteristics: 20 Mbps Device, Bit Time ≥50 ns

over recommended operating conditions PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DRIVER Driver differential output rise ortr, tf 1 7 14 nsfall time RL = 54 Ω See Figure 8tPHL, tPLH Driver propagation delay CL = 50 pF 6 11 17 ns tSK(P) Driver pulse skew, |tPHL – tPLH| 0 2 ns tPHZ, tPLZ Driver disable time 12 50 ns See Figure 9 andReceiver enabled 10 20 nsFigure 10tPZH, tPZL Driver enable time Receiver disabled 3 7 µs RECEIVER tr, tf Receiver output rise or fall time 5 10 ns tPHL, tPLH Receiver propagation delay time CL = 15 pF See Figure 11 60 70 ns tSK(P) Receiver pulse skew, |tPHL – tPLH| 0 6 ns tPLZ, tPHZ Receiver disable time 15 30 ns Driver enabled See Figure 12 10 50 nstpZL(1), tPZH(1), Receiver enable timetPZL(2), tPZH(2) Driver disabled See Figure 13 3 8 µs

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6.7 Typical Characteristics

Figure 1. Driver Output Voltage vs Driver Output Current Figure 2. Driver Differential Output Voltage vs Driver Output Figure 4. Supply Current vs Signal RateFigure 3. Driver Output Current vs Supply Voltage Figure 5. Receiver Output vs Input

7 Parameter Measurement Information

Input generator rate is 100 kbps, 50% duty cycle, rise or fall time is less than 6 ns, output impedance is 50 Ω. Figure 6. Measurement of Driver Differential Output Voltage With Common-Mode Load Figure 7. Measurement of Driver Differential and Common-Mode Output With RS-485 Load Figure 8. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays D at 3 V to test non-inverting output, D at 0 V to test inverting output. Figure 9. Measurement of Driver Enable and Disable Times With Active High Output and Pulldown Load

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3 V VO

D at 0 V to test non-inverting output, D at 3 V to test inverting output. Figure 10. Measurement of Driver Enable and Disable Times With Active Low Output and Pullup Load Figure 11. Measurement of Receiver Output Rise and Fall Times and Propagation Delays

0 V or 3 V

Figure 12. Measurement of Receiver Enable and Disable Times With Driver Enabled

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1.5 V or 0 V C = 15 pF 20%/c177L

Figure 13. Measurement of Receiver Enable Times With Driver Disabled

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8 Detailed Description

8.1 Overview

The SN55HVD75-EP is a low-power, half-duplex RS-485 transceiver available in a speed grade suitable for data transmission up to 20 Mbps. This device has active-high driver enables and active-low receiver enables. A standby current of less than 2 µA can be achieved by disabling both driver and receiver.

8.2 Functional Block Diagram

8.3 Feature Description

Internal ESD protection circuits protect the transceiver against electrostatic discharges (ESD) according to IEC 61000-4-2 of up to ±12 kV, and against electrical fast transients (EFT) according to IEC 61000-4-4 of up to ±4 kV. The SN55HVD75-EP half-duplex family provides internal biasing of the receiver input thresholds in combination with large input threshold hysteresis. At a positive input threshold of VIT+ = –20 mV and an input hysteresis of VHYS = 50 mV, the receiver output remains logic high under a bus-idle or bus-short condition even in the presence of 140-mVPP differential noise without the need for external failsafe biasing resistors. Device operation is specified over a wide ambient temperature range from –55°C to 125°C.

8.4 Device Functional Modes

When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is negative. When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin has an internal pulldown resistor to ground; thus, when left open, the driver is disabled (high-impedance) by default. The D pin has an internal pullup resistor to VCC; thus, when left open while the driver is enabled, output A turns high and B turns low. Table 1. Driver Function Table

DESCRIPTION

H H H L Actively drive bus high L H L H Actively drive bus low X L Z Z Driver disabled X OPEN Z Z Driver disabled by default OPEN H H L Actively drive bus high by default

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A Receiver Inputs Vcc B R Vcc 16 V A B Driver Outputs Vcc 9 V R Output R Vcc 9 V DE Input DE Vcc 9 V D and RE Inputs D, RE 1.5 k1.5 k 1 M 3 M SN55HVD75-EP www.ti.com SLOS913 –OCTOBER 2015 When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R, turns high. When VID is negative and lower than the negative input threshold, VIT–, the receiver output turns low. If VID is between VIT+ and VIT–, the output is indeterminate. When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven (idle bus). Table 2. Receiver Function Table VID = VA – VB RE R VIT+ < VID L H Receive valid bus high VIT– < VID < VIT+ L ? Indeterminate bus state VID < VIT– L L Receive valid bus low X H Z Receiver disabled X OPEN Z Receiver disabled by default Open-circuit bus L H Failsafe high output Short-circuit bus L H Failsafe high output Idle (terminated) bus L H Failsafe high output Figure 14. Equivalent Input and Output Circuit Diagrams

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SN55HVD75-EP is a half-duplex RS-485 transceiver commonly used for asynchronous data transmission. The driver and receiver enable pins allow for the configuration of different operating modes. Figure 15. Transceiver Configurations into the bus traffic, whether the driver is transmitting data or not. Combining the enable signals simplifies the interface to the controller by forming a single direction-control signal. when the direction-control line is low. sends and can verify that the correct data have been transmitted.

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9.2 Typical Application

Figure 16. Typical RS-485 Network With SN55HVD75-EP Transceivers RS-485 cable with Z0 = 120 Ω. Typical cable sizes are AWG 22 and AWG 24.

9.2.1 Design Requirements

applications with varying requirements, such as distance, data rate, and number of nodes.

9.2.1.1 Data Rate and Bus Length

small signal jitter of up to 5 or 10%. Figure 17. Cable Length vs Data Rate Characteristic

9.2.1.2 Stub Length

• tr is the 10/90 rise time of the driver
• c is the speed of light (3 × 108 m/s)
• v is the signal velocity of the cable or trace as a factor of c (1) Per Equation 1, Table 3 shows the maximum cable-stub lengths for the minimum driver output rise times of the SN55HVD75-EP half-duplex transceiver for a signal velocity of 78%.

Table 3. Maximum Stub Length

9.2.1.3 Bus Loading

213 transceivers should be connected to the bus.

9.2.1.4 Receiver Failsafe

• Open bus conditions such as a disconnected connector
• Shorted bus conditions such as cable damage shorting the twisted-pair together, or
• Idle bus conditions that occur when no driver on the bus is actively driving In any of these cases, the differential receiver will output a failsafe logic high so that the output of the receiver is not indeterminate. Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input-indeterminate range does not include 0-V differential. To comply with the RS-422 and RS-485 standards, the receiver output must output a high when the differential input VID is more positive than 200 mV, and must output a low when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are VIT+, VIT–, and VHYS (the separation between VIT+ and VIT–). As shown in Electrical Characteristics, differential signals more negative than –200 mV will always cause a low receiver output, and differential signals more positive than 200 mV will always cause a high receiver output. When the differential input signal is close to zero, it is still above the maximum VIT+ threshold of –20 mV, and the receiver output will be high. Only when the differential input is more than VHYS below VIT+ will the receiver output transition to a low state. Therefore, the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis value, VHYS, as well as the value of VIT+.

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Figure 18. Noise Immunity

9.2.1.5 Transient Protection

model produce significantly higher discharge currents than the HBM-model. Figure 19. HBM and IEC-ESD Models and Currents in Comparison (HBM Values in Parenthesis) protection against longer duration transients, typically referred to as surge transients. encountered in industrial environments, such as factory automation and power-grid systems. representative of events that may occur in factory environments in industrial and process automation. transient. 6-kV surge transients are most likely to occur in power generation and power-grid systems.

Figure 20. Power Comparison of ESD, EFT, and Surge Transients is converted into thermal energy which heats and destroys the protection cells, thus destroying the transceiver. for an EFT pulse train, commonly applied during compliance testing. Figure 21. Comparison of Transient Energies

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9.2.2 Detailed Design Procedure

9.2.2.1 External Transient Protection

addition to ESD and EFT transients. Table 4 presents the associated bill of materials. Table 4. Bill of Materials Figure 22. Transient Protections against ESD, EFT, and Surge Transients withstand surge transients of up to 5 kV.

9.2.2.2 Isolated Bus Node Design

bus transceiver via a multi-channel, digital isolator (Figure 23). Figure 23. Isolated Bus Node with Transient Protection Power isolation is accomplished using the push-pull transformer driver SN6501 and a low-cost LDO, TLV70733. pulled up via 4.7 kΩ resistors to limit their input currents during transient events. used to divert transient energy from the floating RS-485 common further toward Protective Earth (PE) ground. This is necessary as noise transients on the bus are usually referred to Earth potential. prevent charging of the floating ground to dangerous potentials during normal operation. might charge CHV to high-potentials. connecting this island to PE ground at the entrance of the power supply unit (PSU). connecting to the chassis at the other end.

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9.2.3 Application Curve

Figure 24. 20 Mbps

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10 Power Supply Recommendations

To assure reliable operation at all data rates and supply voltages, each supply should be buffered with a 100-nF ceramic capacitor located as close to the supply pins as possible. The TPS76333 is a linear voltage regulator suitable for the 3.3-V supply. See the SN6501 device data sheet (SLLSEA0) for isolated power supply designs.

11 Layout

11.1 Layout Guidelines

On-chip IEC ESD protection is sufficient for laboratory and portable equipment but often insufficient for EFT and surge transients occurring in industrial environments. Therefore, robust and reliable bus node design requires the use of external transient protection devices. Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high- frequency layout techniques must be applied during PCB design. For a successful PCB design, start with the design of the protection circuit in mind.

• Place the protection circuitry close to the bus connector to prevent noise transients from entering the board.
• Use VCC and ground planes to provide low-inductance. Note that high-frequency currents follow the path of least inductance and not the path of least impedance.
• Design the protection components into the direction of the signal path. Do not force the transients currents to divert from the signal path to reach the protection device.
• Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC pins of transceiver, UART, and controller ICs on the board.
• Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to minimize effective via-inductance.
• Use 1-kΩ to 10-kΩ pullup or pulldown resistors for enable lines to limit noise currents in these lines during transient events.
• Insert pulse-proof series resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the transceiver and prevent it from latching up.
• While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient blocking units (TBUs) that limit transient current to 200 mA.

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11.2 Layout Example

Figure 25. SN55HVD75-EP Half-Duplex Layout Example

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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www.ti.com 3-Mar-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN55HVD75DRBREP ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 HVD75M V62/15608-01XE ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 HVD75M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 3-Mar-2016 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 15-Oct-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN55HVD75DRBREP SON DRB 8 3000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 15-Oct-2015 Pack Materials-Page 2

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