SN54LVC08A_17 TI1 | Alldatasheet
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A B Y Y /C0043A • B or Y/C0043A /C0041B Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community SN54LVC08A,SN74LVC08A SCAS283S –JANUARY 1993–REVISED AUGUST 2015 SN74LVC08AQuadruple2-InputPositive-ANDGates
1 Features 2 Applications
1• Operate From 1.65 V to 3.6 V • Servers
- Specified From –40°C to 85°C, –40°C to 125°C, • LED Displays and –55°C to 125°C • Network Switches
- Inputs Accept Voltages to 5.5 V • I/O expanders
- Max tpd of 4.1 ns at 3.3 V • Base station processor board
- Typical VOLP (Output Ground Bounce) 3 Description<0.8 V at VCC = 3.3 V, TA = 25°C The SN54LVC08A quadruple 2-input positive-AND• Typical VOHV (Output VOH Undershoot) gate is designed for 2.7-V to 3.6-V VCC operation, and>2 V at VCC = 3.3 V, TA = 25°C the SN74LVC08A quadruple 2-input positive-AND• Ioff Support Live Insertion, Partial-Power-Down gate is designed for 1.65-V to 3.6-V VCC operation.Mode and Back-Drive Protection The LVC08A devices perform the Boolean function• Latch-Up Performance Exceeds 250 mA in positive logic.Per JESD 17
- ESD Protection Exceeds JESD 22 Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as– 2000-V Human-Body Model (A114-A) translators in a mixed 3.3-V/5-V system environment.– 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM)– On Products Compliant to MIL-PRF-38535, All Parameters Are Tested Unless Otherwise CFP (14) 9.21 mm × 5.97 mm Noted. On All Other Products, Production SNJ54LVC08A CDIP (14) 19.56 mm × 6.92 mm Processing Does Not Necessarily Include LCCC (20) 8.89 mm × 8.89 mm Testing of All Parameters. VQFN (14) 3.50 mm × 3.50 mm TSSOP (14) 5.00 mm × 4.40 mm SN74LVC08A SOP (14) 10.30 mm × 5.30 mm SOIC (14) 8.65 mm × 3.91 mm SSOP (14) 6.20 mm × 5.30 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram, Each Gate (Positive Logic) An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54LVC08A,SN74LVC08A SCAS283S –JANUARY 1993–REVISED AUGUST 2015 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision R (June 2015) to Revision S Page Changes from Revision Q (November 2010) to Revision R Page
- Added Applications, Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
2 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated
Product Folder Links: SN54LVC08A SN74LVC08A
SN54LVC08A,SN74LVC08A www.ti.com SCAS283S –JANUARY 1993–REVISED AUGUST 2015
5 Device Options
PART NUMBER PACKAGE BODY SIZE SNJ54LVC08AW CFP (14) 9.21 mm × 5.97 mm SNJ54LVC08AJ CDIP (14) 19.56 mm × 6.92 mm SNJ54LVC08AFK LCCC (20) 8.89 mm × 8.89 mm SN74LVC08ARGYR VQFN (14) 3.50 mm × 3.50 mm SN74LVC08APW SN74LVC08APWT TSSOP (14) 5.00 mm × 4.40 mm SN74LVC08APWG3 SN74LVC08ANSR SOP (14) 10.30 mm × 5.30 mm SN74LVC08AD SN74LVC08ADT SOIC (14) 8.65 mm × 3.91 mm SN74LVC08ADRG3 SN74LVC08ADBR SSOP (14) 6.20 mm × 5.30 mm Copyright © 1993–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: SN54LVC08A SN74LVC08A
V GND CC 1 1 GND VCC SN54LVC08A,SN74LVC08A SCAS283S –JANUARY 1993–REVISED AUGUST 2015 www.ti.com
6 Pin Configuration and Functions
D, DB, NS, J, W, or PW Package RGY Package14-Pin SOIC, SSOP, SOP, CDIP, or TSSOP 14-Pin VQFNTop View Top View 20-Pin LCCC Top View Pin Functions PIN SOIC, SSOP, TYPE DESCRIPTION NAME SOP, CDIP, LCCC or TSSOP 1A 1 2 I AND Gate Input 1B 2 3 I AND Gate Input 1Y 3 4 O AND Gate Output 2A 4 6 I AND Gate Input 2B 5 8 I AND Gate Input 2Y 6 9 O AND Gate Output GND 7 10 Ground Ground pin for the device 3Y 8 12 O AND Gate Output 3A 9 13 I AND Gate Input 3B 10 14 I AND Gate Input 4Y 11 16 O AND Gate Output 4A 12 18 I AND Gate Input 4B 13 19 I AND Gate Input VCC 14 20 Power Power pin for the device
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Product Folder Links: SN54LVC08A SN74LVC08A
SN54LVC08A,SN74LVC08A www.ti.com SCAS283S –JANUARY 1993–REVISED AUGUST 2015 Pin Functions (continued) PIN SOIC, SSOP, TYPE DESCRIPTION NAME SOP, CDIP, LCCC or TSSOP NC(1) — — No connect (1) NC – No internal connection
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage –0.5 6.5 V VI Input voltage(2) –0.5 6.5 V VO Output voltage(2)(3) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through VCC or GND ±100 mA Ptot Power dissipation(4)(5) TA = –40°C to 125°C 500 mW TJ Junction temperature –65 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The value of VCC is provided in the Recommended Operating Conditions table. (4) For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K. (5) For the DB, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K.
7.2 ESD Ratings
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge VCharged-device model (CDM), per JEDEC specification JESD22- ±1000C101(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions for SN54LVC08A(1)
–55°C to 125°C UNIT MIN MAX Operating 2 3.6 VCC Supply voltage V Data retention only 1.5 VIH High-level input voltage VCC = 2.7 V to 3.6 V 2 V VIL Low-level input voltage VCC = 2.7 V to 3.6 V 0.8 V (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. Copyright © 1993–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: SN54LVC08A SN74LVC08A
SN54LVC08A,SN74LVC08A SCAS283S –JANUARY 1993–REVISED AUGUST 2015 www.ti.com Recommended Operating Conditions for SN54LVC08A(1) (continued) SN54LVC08A –55°C to 125°C UNIT MIN MAX VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 2.7 V –12 IOH High-level output current mA VCC = 3 V –24 VCC = 2.7 V 12 IOL Low-level output current mA VCC = 3 V 24 Δt/Δv Input transition rise or fall rate 8 ns/V
7.4 Recommended Operating Conditions for SN74LVC08A(1)
TA = 25°C –40°C to 85°C –40°C to 125°C UNIT MIN MAX MIN MAX MIN MAX VCC Supply voltage V Data retention only 1.5 1.5 1.5 VCC = 2.7 V to 3.6 V 2 2 2 VI Input voltage 0 5.5 0 5.5 0 5.5 V VO Output voltage 0 VCC 0 VCC 0 VCC V VCC = 1.65 V –4 –4 –4 VCC = 2.3 V –8 –8 –8High-levelIOH mAoutput current VCC = 2.7 V –12 –12 –12 VCC = 3 V –24 –24 –24 VCC = 1.65 V 4 4 4 VCC = 2.3 V 8 8 8Low-levelIOL mAoutput current VCC = 2.7 V 12 12 12 VCC = 3 V 24 24 24 Δt/Δv Input transition rise or fall rate 8 8 8 ns/V (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004.
7.5 Thermal Information
D (SOIC) DB (SSOP) NS (SOP) PW RGYTHERMAL METRIC(1) UNIT(TSSOP) (LCCC)
14 PINS 14 PINS 14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 86 96 76 113 47 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
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Product Folder Links: SN54LVC08A SN74LVC08A
SN54LVC08A,SN74LVC08A www.ti.com SCAS283S –JANUARY 1993–REVISED AUGUST 2015
7.6 Electrical Characteristics for SN54LVC08A
over recommended operating free-air temperature range (unless otherwise noted) SN54LVC08A PARAMETER TEST CONDITIONS VCC –55°C to 125°C UNIT MIN TYP(1) MAX IOH = –100 μA 2.7 V to 3.6 V VCC – 0.2 2.7 V 2.2 VOH IOH = –12 mA V 3 V 2.4 IOH = –24 mA 3 V 2.2 IOL = 100 μA 2.7 V to 3.6 V 0.2 VOL IOL = 12 mA 2.7 V 0.4 V IOL = 24 mA 3 V 0.55 II VI = 5.5 V or GND 3.6 V ±5 μA ICC VI = VCC or GND, IO = 0 3.6 V 10 μA ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V 500 μA Ci VI = VCC or GND 3.3 V 5 pF (1) TA = 25°C
7.7 Electrical Characteristics for SN74LVC08A
over recommended operating free-air temperature range (unless otherwise noted) SN74LVC08A PARAMETER TEST CONDITIONS VCC TA = 25°C –40°C to 85°C –40°C to 125°C UNIT MIN TYP MAX MIN MAX MIN MAX IOH = –4 mA 1.65 V 1.29 1.2 1.05 IOH = –8 mA 2.3 V 1.9 1.7 1.55 VOH V 2.7 V 2.2 2.2 2.05 IOH = –12 mA 3 V 2.4 2.4 2.25 IOH = –24 mA 3 V 2.3 2.2 2 IOL = 4 mA 1.65 V 0.24 0.45 0.6 VOL IOL = 8 mA 2.3 V 0.3 0.7 0.75 V IOL = 12 mA 2.7 V 0.4 0.4 0.6 IOL = 24 mA 3 V 0.55 0.55 0.8 II VI = 5.5 V or GND 3.6 V ±1 ±5 ±20 μA ICC VI = VCC or GND, IO = 0 3.6 V 1 10 40 μA One input at VCC – 0.6 V,ΔICC 2.7 V to 3.6 V 500 500 5000 μAOther inputs at VCC or GND Ci VI = VCC or GND 3.3 V 5 pF
7.8 Switching Characteristics for SN54LVC08A
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) SN54LVC08A FROM TOPARAMETER VCC –55°C to 125°C UNIT(INPUT) (OUTPUT) MIN MAX 2.7 V 4.8 tpd A or B Y ns 3.3 V ± 0.3 V 1 4.1 Copyright © 1993–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: SN54LVC08A SN74LVC08A
7.9 Switching Characteristics for SN74LVC08A
7.10 Operating Characteristics
1.8 V 7
3.3 V 10
7.11 Typical Characteristics
Figure 1. Propagation Delay (Low to High Transition) Figure 2. Propagation Delay (High to Low Transition)
8 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated
NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low , except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. t PLZ and tPHZ are the same as tdis. F. t PZL and tPZH are the same as ten. G. t PLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices.
8 Parameter Measurement Information
Figure 3. Load Circuit and Voltage Waveforms
9 Detailed Description
9.1 Overview
Y= A ·B. This device is useful when multiple AND function is used in the system.
9.2 Functional Block Diagram
Figure 4. Logic Diagram, Each Gate (Positive Logic)
9.3 Feature Description
The device can operate from 1.65 V to 3.6 V, allowing to be used in low voltage systems. The maximum tpd of 4.1 ns at 3.3 V is beneficial for use in high speed applications. The device has a Ioff support live insertion, a partial-power-down mode, and a back-drive protection.
9.4 Device Functional Modes
Table 1 lists the functional modes for the SN54LVC08A and SN74LVC08A devices. Table 1. Truth Table
10 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.2 Typical Application
Figure 5. Three Input AND Gate Implementation and Driving LED
10.2.1 Design Requirements
so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
10.2.3 Application Curves
Figure 6. Output Drive Current (IOL) Figure 7. Output Drive Current (IOH)
11 Power Supply Recommendations
the Recommended Operating Conditions table. should be installed as close to the power pin as possible for best results.
12 Layout
12.1 Layout Guidelines
whichever make more sense or is more convenient.
12.2 Layout Examples
Figure 8. Layout Examples
12 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated
13 Device and Documentation Support
13.1 Related Links
resources, tools and software, and quick access to sample or buy. Table 2. Related Links
13.2 Community Resources
solve problems with fellow engineers. contact information for technical support.
13.3 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
this document. For browser based versions of this data sheet, refer to the left hand navigation.
www.ti.com 15-Apr-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 5962-9753401Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9753401Q2A SNJ54LVC 08AFK 5962-9753401QCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9753401QC A SNJ54LVC08AJ 5962-9753401QDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9753401QD A SNJ54LVC08AW HVAL02231ARGYR ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LC08A SN74LVC08AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A SN74LVC08ADBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08ADBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A SN74LVC08ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A SN74LVC08ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LVC08A SN74LVC08ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A SN74LVC08ADRG3 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LVC08A SN74LVC08ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A SN74LVC08ADT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A
www.ti.com 15-Apr-2017 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN74LVC08ANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A SN74LVC08ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A SN74LVC08APW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08APWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08APWRG3 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08APWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08ARGYR ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LC08A SN74LVC08ARGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LC08A SNJ54LVC08AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9753401Q2A SNJ54LVC 08AFK SNJ54LVC08AJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9753401QC A SNJ54LVC08AJ SNJ54LVC08AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9753401QD A SNJ54LVC08AW
www.ti.com 15-Apr-2017 Addendum-Page 3 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54LVC08A, SN74LVC08A :
- Catalog: SN74LVC08A
- Automotive: SN74LVC08A-Q1 , SN74LVC08A-Q1
www.ti.com 15-Apr-2017 Addendum-Page 4
- Enhanced Product: SN74LVC08A-EP , SN74LVC08A-EP
- Military: SN54LVC08A NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
- Enhanced Product - Supports Defense, Aerospace and Medical Applications
- Military - QML certified for Military and Defense Applications
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2016 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC08ADBR SSOP DB 14 2000 367.0 367.0 38.0 SN74LVC08ADR SOIC D 14 2500 367.0 367.0 38.0 SN74LVC08ADR SOIC D 14 2500 333.2 345.9 28.6 SN74LVC08ADR SOIC D 14 2500 364.0 364.0 27.0 SN74LVC08ADRG3 SOIC D 14 2500 364.0 364.0 27.0 SN74LVC08ADRG4 SOIC D 14 2500 367.0 367.0 38.0 SN74LVC08ADRG4 SOIC D 14 2500 333.2 345.9 28.6 SN74LVC08ADT SOIC D 14 250 367.0 367.0 38.0 SN74LVC08ANSR SO NS 14 2000 367.0 367.0 38.0 SN74LVC08APWR TSSOP PW 14 2000 364.0 364.0 27.0 SN74LVC08APWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74LVC08APWRG3 TSSOP PW 14 2000 364.0 364.0 27.0 SN74LVC08APWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 SN74LVC08APWT TSSOP PW 14 250 367.0 367.0 35.0 SN74LVC08ARGYR VQFN RGY 14 3000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2016 Pack Materials-Page 2
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01
28 PINS SHOWN
8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150
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