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Document overview
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Technical content
Features
- 5V Logic and 12V Supply Rail
- Up to +200V Output Voltage
- Low-power Level Shifting
- 50 mA Minimum Source and Sink Currents
- 40 MHz Equivalent Data Rate
- Latched Data Outputs
- Forward and Reverse Shifting Options (DIR Pin)
- Chip Select
- Polarity Function
Applications
- Display Driver
- Print Head Driver
- MEMS Applications General Description The HV7620 is a low-voltage serial-to-high-voltage pa rallel converter with push- pull outputs. This device has been designed for use as a driver for color AC plasma displays. The device has four parallel 8-bit shift registers pe rmitting data rates four times the speed of one. The data is clocked in simultaneously on all four data inputs with a single clock. Data is shifted in on a low-to-high transition of the clock. The latches and control logic perform the output enable function. The DIR pin causes clockwise (CW) shifting of the data whe n connected to VDD1 and counterclockwise (CCW) shifting when connected to LVGND. Operation of the shift register is not affected by the LE (latch enable) input. Transfer of data from the shift registers to the latches occurs when the LE input is high. Data is stored in the latches when LE is low. The current source on the logic inputs provides active pull up when the input pins are open. Package Type See Table 2-1 for pin information. 64-lead PQFP (Top view)
40 MHz 32-Channel Serial-to-Parallel Converter with Push-Pull Outputs
≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ DINB DOUTB DINC DOUTC DIND DOUTD QA1 8-Bit Latches QA8 QB1 8-Bit Latches QB8 QC1 8-Bit Latches QC8 8-Bit Shift Register 8-Bit Shift Register 8-Bit Shift Register 8-Bit Shift Register QD1 8-Bit Latches QD8 HV7620 DS20005779A-page 2 2019 Microchip Technology Inc. Functional Block Diagram
2019 Microchip Technology Inc. DS20005779A-page 3 HV7620
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings† Continuous Total Power Dissipation: † Notice: Stresses above those listed under “Absolute Maxi mum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. Note 1: Fo r operations above 25°C ambient, derate linearly to maximum operating temperature at 20 mW/°C. 2: Device is ESD sensitive. Handling precautions are recommended. RECOMMENDED OPERATING CONDITIONS Parameter Sym. Min. Typ. Max. Unit Conditions Logic Supply Voltage VDD1 4.5 — VDD2 V 12V Supply Voltage VDD2 10.8 — 13.2 V High-Voltage Supply Voltage VPP 50 — 200 V High-Level Input Voltage VIH VDD1 –0.5V — VDD1 V Low-Level Input Voltage VIL 0 — 0.5 V Clock Frequency VDD1 = 5V fCLK — — 10 MHz VDD1 = 12V — — 5 MHz Operating Junction Temperature Range TA –40 — +85 °C Allowable Pulsed Current through Output Diodes IOD — — 500 mA Note 1 Allowable Pulsed VPP or HVGND Current IGND(VPP) — — 16 A Note 1 Slew Rate of VPP VPP(SLEW) — — 340 V/µs Note 1: Curren t pulse width = 500 ns; duty cycle = 5%
DC ELECTRICAL CHARACTERISTICS VDD2 = 12V, VPP = 200V and TJ = 25°C. Parameter Sym. Min. Typ. Max. Unit Conditions VDD1 Supply Current IDD1 — — 5 mA fCLK = 10 MHz VDD2 Supply Current IDD2 — — 22 mA VDD2 = 13.2V, fCLK = 10 MHz High Voltage Supply Current IPP — — 2 mA All outputs high or low Quiescent VDD1 Supply Current IDD1Q — — 100 µA All input = VDD1 Quiescent VDD2 Supply Current IDD2Q — — 100 µA All input = VDD1 High-Level Output HVOUT VOH 185 — — V IO = –50 mA Data OUT VDD –1 — — V IO = –100 µA Low-Level Output HVOUT VOL — — 20 V IO = +50 mA Data OUT — — 1 V IO = +100 µA High-Level Logic Input Current IIH — — 1 µA VIN = VDD1 Low-Level Logic Input Current IIL — — –10 µA VIN = 0V HVGND to LVGND Voltage Difference VGG –1 — 1 V AC ELECTRICAL CHARACTERISTICS VPP = 200V and TJ = 25°C. Parameter Sym. Min. Typ. Max. Unit Conditions Clock Frequency VDD1 = 5V fCLK — — 10 MHz Per register, CL = 15 pF VDD1 = 12V — — 5 MHz Clock Width High or Low tWL, tWH 40 — — ns Data Set-Up Time Before Clock Rises tSU 20 — — ns Data Hold Time after Clock Rises tH 20 — — ns Time from Latch Enable to HVOUT tON, tOFF — — 275 ns CL = 15 pF LE Pulse Width tWLE 25 — — ns Delay Time Clock to LE Low to High tDLE 50 — — ns LE Set-Up Time before Clock Rises tSLE 20 — — ns BL or CS Low to High to HVOUT tDLF, tDLN — — 250 ns Clock to HVOUT tCOF, tCON — — 275 ns Delay Time Clock to Data Low to High VDD1 = 5V tDLH — — 250 ns CL = 15 pFVDD1 = 12V — — 100 ns Delay Time Clock to Data High to Low VDD1 = 5V tDHL — — 250 ns CL = 15 pFVDD1 = 12V — — 100 ns HV7620 DS20005779A-page 4 2019 Microchip Technology Inc.
TEMPERATURE SPECIFICATIONS Parameter Sym. Min. Typ. Max. Unit Conditions TEMPERATURE RANGE Operating Junction Temperature TJ –40 — +85 °C Maximum Junction Temperature TJ(MAX) — — +125 °C Storage Temperature TS –65 — +150 °C PACKAGE THERMAL RESISTANCE 64-lead PQFP JA — 41 — °C/W 2019 Microchip Technology Inc. DS20005779A-page 5 HV7620 Switching Waveforms CLK Data Input 50% 50% 50% 50% tSU tH tWL tf tWH tr 90% 10% 50% 90% 10% 50% tDLE tWLE tSLE 10% 90% tOFF LE tON VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL HVOUT HVOUT 50% 50% 50% 50% tDHL tCOF tCON tDLH Data Valid VOH VOL VOH VOL Data Output 10% tDLF 90% tDLN VIH VIL VOH VOL BLA, BLB, BLC, BLD, or CS HVOUT 50%
DS20005779A-page 6 2019 Microchip Technology Inc.
2.0 PIN DESCRIPTION
The details on the pins of HV7620 are listed on Table 2-1. Refer to Package Type for the location of pins. TABLE 2-1: 64-LEAD PQFP PIN FUNCTION TABLE Pin Number Pin Name Description
1 HVGND High-voltage supply ground
2 VPP High-voltage power supply
3 HVOUTD8 High-voltage output
4 HVOUTC8 High-voltage output
5 HVOUTB8 High-voltage output
6 HVOUTA8 High-voltage output
7 HVOUTD7 High-voltage output
8 HVOUTC7 High-voltage output
9 HVOUTB7 High-voltage output
10 HVOUTA7 High-voltage output
11 HVOUTD6 High-voltage output
12 HVOUTC6 High-voltage output
13 HVOUTB6 High-voltage output
14 HVOUTA6 High-voltage output
15 HVOUTD5 High-voltage output
16 HVOUTC5 High-voltage output
17 HVOUTB5 High-voltage output
18 HVOUTA5 High-voltage output
19 VPP High-voltage power supply
20 HVGND High-voltage supply ground
21 HVGND High-voltage supply ground
22 VDD2 12V power supply
23 BLC Blanking pins
24 BLD Blanking pins
25 LE Latch enable pin
26 DOUTD Data output pin
27 DIND Data input pin
28 DINC Data input pin
29 DOUTC Data output pin
30 POL Polarity pin
31 LVGND Low-voltage supply ground
32 DIR Direction pin
33 CS Chip select pin
34 DOUTB Data output pin
35 DINB Data input pin
36 DINA Data input pin
2019 Microchip Technology Inc. DS20005779A-page 7 HV7620
37 DOUTA Data output pin
38 CLK Clock pin
39 BLA Blanking pins
40 BLB Blanking pins
41 VDD1 Logic power supply
42 LVGND Low-voltage supply ground
43 N/C No internal connection
44 HVGND High-voltage supply ground
45 HVGND High-voltage supply ground
46 VPP High-voltage power supply
47 HVOUTD4 High-voltage output
48 HVOUTC4 High-voltage output
49 HVOUTB4 High-voltage output
50 HVOUTA4 High-voltage output
51 HVOUTD3 High-voltage output
52 HVOUTC3 High-voltage output
53 HVOUTB3 High-voltage output
54 HVOUTA3 High-voltage output
55 HVOUTD2 High-voltage output
56 HVOUTC2 High-voltage output
57 HVOUTB2 High-voltage output
58 HVOUTA2 High-voltage output
59 HVOUTD1 High-voltage output
60 HVOUTC1 High-voltage output
61 HVOUTB1 High-voltage output
62 HVOUTA1 High-voltage output
63 VPP High-voltage power supply
64 HVGND High-voltage supply ground
TABLE 2-1: 64-LEAD PQFP PIN FUNCTION TABLE (CONTINUED) Pin Number Pin Name Description
DS20005779A-page 8 2019 Microchip Technology Inc.
3.0 FUNCTIONAL DESCRIPTION
Follow the steps in Table 3-1 to power up and power dow n the HV7620. TABLE 3-1: POWER-UP AND POWER-DOWN SEQUENCE Power-Up Power-Down Step Description Step Description
1 GND (HV, LV) 1 Logic Input Signals
2 VDD1 2 VPP
3 VDD2 3 VDD2
4 VPP 4 VDD1
5 Logic Input Signals 5 GND (HV, LV)
TABLE 3-2: TRUTH FUNCTION TABLE 1 Function Inputs HVOUT DINA DINB DINC DIND CLK LE DIR BLA BLB BLC BLD CS POL A B C D All O/P High X X X X X X X X X X X L L H H H H All O/P Low X X X X X X X X X X X L H L L L L “A” (Note 3) Ou tputs Low X X X X X X X L X X X X H L Note Note Note Normal Polarity X X X X X X X H H H H H H No Inversion Outputs Invert ed X X X X X X X H H H H H L Inversion Transpar- ent Mode H L L L ↑ H X H H H H H H H L L L Data Stored X X X X X L X H H H H H H Stored data Shift CWA X X X X ↑ H H H H H H H X AN AN+1 BN BN+1 CN CN+1 DN DN+1 Shift CCWB X X X X ↑ H L H H H H H X AN AN-1 BN BN-1 CN CN-1 DN DN-1 Note 1: H = High logic level L = Low logic level X = Irrelevant ↑ = Low -to-high transition 2: D ependent on previous stage’s state before the last CLK ↑ or last LE high 3: BLB, BLC and BLD will have a similar effect on their respective output.
Logic Data Output High Voltage Outputs 2019 Microchip Technology Inc. DS20005779A-page 9 HV7620 FIGURE 3-1: Input and Output Equivalent Circuits.
DS20005779A-page 10 2019 Microchip Technology Inc.
4.0 PACKAGE MARKING INFORMATION
4.1 Packaging Information
Legend: XX...X Product Code or Cust omer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC ® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo. YYWWNNN e3 HV7620PG 1912999 XXXXXXXXe3 64-lead PQFP Example
2019 Microchip Technology Inc. DS20005779A-page 11 HV7620 NOTES:
64-Lead PQFP (3-Sided) Package Outline (PG) Symbol A A1 A2 b D D1 E E1 e L L1 L2 L3 șș Dimen- sion (mm) 0.80 BSC 0.73 1.95 REF 0.25 BSC 0.55 REF 0O 5O Drawings not to scale. Note: 1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEH DPROGHGPDUNLGHQWL¿HU DQHPEHGGHGPHWDOPDUNHU RU DSULQWHGLQGLFDWRU 2. 7KHOHDGVRQWKLVVLGHDUHWULPPHG Seating Plane Gauge Plane θL View B View B be Side View A2A E D Seating Plane Top View Note 1 (Index Area D1/4 x E1/4) Note 2 HV7620 DS20005779A-page 12 2019 Microchip Technology Inc.
2019 Microchip Technology Inc. DS20005779A-page 13 HV7620 APPENDIX A: REVISION HISTORY Revision A (January 2019)
- Converted Supertex Doc# DSFP- HV7620 to Microchip DS20005779A
- Removed “HVCMOS® Technology” from the Features section
- Changed the package marking format
- Made minor text changes throughout the docu - ment
DS20005779A-page 14 2019 Microchip Technology Inc. PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. Example: a) HV7620PG-G: 40 MHz 32-Channel Serial-to- Parallel Converter with Push- Pull Outputs, 64-lead PQFP , 66/Tray PART NO. Device Device: HV7620 = 40 MHz 32-Channel Serial-to-Parallel Converter with Push-Pull Outputs Package: PG = 64-lead PQFP Environmental: G = Lead (Pb)-free/RoHS-compliant Package Media Type: (blank) = 66/Tray for a PG Package XX Package - X - X Environmental Media Type Options
2019 Microchip Technology Inc. DS20005779A-page 15 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application me ets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or ot herwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP , INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2019, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-4106-9 Note the following details of the code protection feature on Microchip devices:
- Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
- Microchip believes that its family of pr oducts is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
- There are dishonest and possibly illegal meth ods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
- Microchip is willing to work with the customer who is concerned about the integrity of their code.
- Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC ® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==
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