HV7370

HV7370 SIRECTIFIER | Alldatasheet

Document overview

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Technical content

Features

HVCMOS® technology for high performance High density integration ultrasound transmitter 0 to ±100V open-drain voltage ±850mA source and sink current Up to 20MHz operation frequency Matched delay times 1.8 to 5V CMOS logic interface

Applications

Medical ultrasound imaging Piezoelectric transducer drivers NDT ultrasound transmission Pulse waveform generator General Description The Supertex HV7370 is a four-channel, monolithic high voltage, high-speed damper. It is designed for working with the HV738, HV748 or HV758 for medical ultrasound waveform generators requiring fast return-to-zero applications. The HV7370 consists of a controller logic interface circuit, level translators, MOSFET gate drives and high current power P- channel and N-channel MOSFETs as the output stage for each channel. The output stages of each channel are designed to provide peak output currents of over ±0.85A for damping to ground, with up to ±100V swing. The control from inputs to outputs uses direct coupling topology, which not only saves components and PCB layout space, but also makes the damping frequency function down to DC. Block Diagram Quad, High Speed, ±100V 850mA, Ultrasound Damper Level Trans.NIN1 SUB VPFVDD GREF +1.8 to 3.3V Logic VPP EN MC1 VNN 0 to -75V P-Driver TXN1 VNN +9.0V N-Driver Pulser Supertex HV748 1 of 4 Channels C2 C3 C5C4 TXP1 D1 VNF VSUBVLL C6C7 EN_PWR MC0 OTP VSS PIN1 Level Trans. RGND RP1 RN1 RGND Level Trans. SUB -9.0V VDD +9.0V RGND EN RGND P-Driver ND1 +9.0V N-Driver C2 C3 C4 PD1 HVOUT1 VLL +1.8 to 3.3V EN_PWR VSS IN1 Level Trans. Damper Supertex HV7370 1 of 4 Channels VSUB VDP VDN +9.0V (Damp) (+Pulse) (-Pulse) VPP -9.0V 0 to +75V

Ordering Information

5.00x5.00mm body 1.00mm height (max) 0.50mm pitch HV7370 HV7370K6-G -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value VSS, power supply reference 0V VLL, positive logic supply -0.5V to +7.0V VDD, positive logic, level translator supply -0.5V to +13V (RGND - VDP), P-Gate driver supply +0.5V to -13V (VDN - RGND), N-Gate driver supply -0.5V to +13V RGND, RTZ-Ground voltage -2.0V to +2.0V All logic input PINX, NINX and EN voltages -0.5V to +7.0V VSUB substrate voltage +120V (NDX - RGND) damping N-MOSFET BVSUB voltage +120V (PDX - RGND) damping P-MOSFET BVSUB voltage -120V Maximum junction temperature +150°C Storage temperature -65°C to 150°C Thermal resistance, θJA 21.6°C/W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Pin Configuration Package Marking HV7370 LLLLLL YYWW AAACCC L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging 32-Lead QFN (K6) 32-Lead QFN (K6) (top view) Power-Up Sequence of Pulser & Damper Step Description

1 VSUB

2 VLL with logic signal low

3 VDD, VDN, and VDP

4 (VPP- VPF) and (VNF- VNN)

5 VPP and VNN

6 Logic control signals

Power-Down Sequence of Pulser & Damper Step Description

1 All logic control signals go to low

2 VPP and VNN

3 (VPP- VPF) and (VNF- VNN)

4 VDD, VDN, and VDP

5 VLL

6 VSUB

Operating Supply Voltages and Current (4 Channel Active) (Operating conditions, unless otherwise specified, VSS = 0V,VLL = +3.3V,VDD = VDN = +9V, VDP = -9V, VPP - VPF = +9V, VNN - VNF = -9V, VSUB = +75V VPP/VNN = ±75V, TA = 25°C) Sym Parameter Min Typ Max Units Conditions VLL Logic voltage reference 1.8 3.3 5.0 V --- VDD Internal voltage supply1 5.0 8.0 to 11 12 V --- VDP P-Gate driver supply -12 -VDD -5.0 V Negative voltage supply VDN N-Gate drive supply 5.0 VDD 12 V Positive voltage supply VSUB IC substrate voltage 5.0 VDD 100 V --- RGND RTZ-Ground voltage -2.0 0 +2.0 V --- ILL VLL Current EN = Low - 35 120 µA --- IDDQ VDD Current EN = Low - 10 - µA --- IDDEN VDD Current EN = High - 1.5 3.0 mA f = 0MHz IDDEN VDD Current - 6.0 - mA f = 5.0MHz, continuous, no loads IDPQ VDP Current EN = Low - 50 - µA f = 0MHz IDPEN VDP Current - 30 - mA f = 5.0MHz, continuous, no loads IDNQ VDN Current EN = Low - 50 - µA f = 0MHz IDNEN VDN Current - 12 - mA f = 5.0MHz, continuous, no loads Note: 1. P&N-FETs best matching when VDD = VDN = +10V, VPN = -10V Under Voltage Sym Parameter Min Typ Max Units Conditions VUVDD VDD threshold 2.0 3.7 7.0 V --- VUVLL VLL threshold 1.0 1.25 1.5 V --- VUVVDN UV threshold for VDN 3.5 4.25 4.75 V --- VUVVDP UV threshold for VDP 1.75 4.5 6.0 V Typ VUVVDP ≤ -(VDN/2), [VDN = +9.0V]

Electrical Characteristics

(Operating conditions, unless otherwise specified, VSS = 0V,VLL = +3.3V,VDD = VDN = +9V, VDP = -9V, VPP - VPF = +9V, VNN - VNF = -9V, VSUB = +75V, VPP/VNN = ±75V, TA = 25°C) Output P-Channel MOSFET, PDx Sym Parameter Min Typ Max Units Conditions IOUT Output saturation current 0.6 0.85 - A --- RON Channel resistance - 13 - Ω ISD = 100mA COSS Output capacitance - 50 - pF VSUB = 25V, f = 1.0MHz Output N-Channel MOSFET, NDx IOUT Output saturation current 0.6 0.85 - A --- RON Channel resistance - 12.5 - Ω IDS = 100mA COSS Output capacitance - 20 - pF VSUB = 25V, f = 1.0MHz

Sym Parameter Min Typ Max Units Conditions VIH Input logic high voltage (VLL -0.4) - VLL V --- VIL Input logic low voltage 0 - 0.4 V --- IIH Input logic high current - - 10 µA --- IIL Input logic low current -10 - - µA --- CIN Input logic capacitance - 5 - pF --- (Operating conditions, unless otherwise specified, VSS = 0V,VLL = +3.3V,VDD = VDN = +9V, VDP = -9V, VPP - VPF = +9V, VNN - VNF = -9V, VSUB = +75V VPP/VNN = ±75V, TA = 25°C) Sym Parameter Min Typ Max Units Conditions trp P-FET output rise time - 26 - ns 330pF//2.5kΩ load tfn N-FET output fall time - 26 - ns fOUT Output frequency range - - 20 MHz --- tEN Enable time - 180 500 µs 100Ω resistor load, +10V to NDX and -10V to PDXtEN Disable time - 2.8 10 tdrp P-FET on delay time - 19 - ns 8.2Ω resistor load (see timing diagram) tdfp P-FET off delay time - 17 - tdrn N-FET on delay time - 19 - tdfn N-FET off delay time - 17 - ΔtDELAY |tdr - tdf| delay time matching - ±3.0 - ns P to N, channel to channel tJ Delay time jitter, rise or fall - 15 - ps VPP/VNN = ±25V, input rising 50% to output PDX/NDX rising/falling 50%, with 100Ω load

10% 90% INx (Damper) NINx (Pulser) Output VNN VPP trp PINx (Pulser) 10%VPP VLL 90% tfn tdrn 50%INx INx tdfn PDx IOUT 0ANDx 50% tdfp 50% tdrp 50% SUB VDPVDD GREF EN ND1 VDN 1 of n Channels VPP PD1 VLL EN_PWR VSS IN1 VNN VSUB IOUT P-Driver N-Driver Level Translator Level Translator Switch Test Timing Diagram

Pin # Name Description 1 VLL Logic Hi voltage reference input (+3.3V). 2 VSS Power supply return (0V). 3 IN1 Input logic control of damping P&N-FET of channel 1, Hi = on, Low = off. 4 IN2 Input logic control of damping P&N-FET of channel 2, Hi = on, Low = off. 5 IN3 Input logic control of damping P&N-FET of channel 3, Hi = on, Low = off. 6 IN4 Input logic control of damping P&N-FET of channel 4, Hi = on, Low = off. 7 VSS Power supply return (0V). 8 VDD Positive internal voltage supply (+9.0V). 9 NC No connection. 10 VSUB Substrate of the damper HV7370, must VSUB = VDD, or VSUB of the pulser. 11 VDP P-FET drive floating power supply, (RGND - VDP) = +9.0V.

12 RGND

Return ground.13 RGND

14 RGND

15 VDN N-FET drive floating power supply, (VDN - RGND) = +9.0V. 16 VSUB Substrate of the damper HV7370, must VSUB = VDD, or VSUB of the pulser. 17 ND4 Output damping N-FET drain (open drain output) for channel 4. 18 PD4 Output damping P-FET drain (open drain output) for channel 4. 19 ND3 Output damping N-FET drain (open drain output) for channel 3. 20 PD3 Output damping P-FET drain (open drain output) for channel 3. 21 ND2 Output damping N-FET drain (open drain output) for channel 2. 22 PD2 Output damping P-FET drain (open drain output) for channel 2. 23 ND1 Output damping N-FET drain (open drain output) for channel 1. 24 PD1 Output damping P-FET drain (open drain output) for channel 1. 25 VSUB Substrate of the damper HV7370, must VSUB = VDD , or VSUB of the pulser. 26 VDN N-FET drive floating power supply, (VDN - RGND) = +9.0V.

27 RGND

Return ground.28 RGND

29 RGND

30 VDP P-FET drive floating power supply, (RGND - VDP) = +9.0V. 31 VSUB Substrate of the damper HV7370, must VSUB = VDD, or VSUB of the pulser. 32 EN Chip power enable Hi = on, Low = off. Thermal Pad (VSUB) Substrate bottom is internally connected to the central thermal pad on the bottom of package. It must be connected to VSUB. VSUB normally is connected to VDD = +9.0V or +75V (pulser VSUB). Note: Thermal pad must be connected to VSUB.

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV7370 NR090508 32-Lead QFN Package Outline (K6) 5.00x5.00mm body, 1.00mm height (max), 0.50mm pitch Symbol A A1 A3 b D D2 E E2 e L L1 θ Dimension (mm) MIN 0.80 0.00 0.20 REF 0.50 BSC 0.30† 0.00 0O JEDEC Registration MO-220, Variation VHHD-6, Issue K, June 2006. * This dimension is not specified in the original JEDEC drawing. The value listed is for reference only. † This dimension is a non-JEDEC dimension. Drawings not to scale. Supertex Doc. #: DSPD-32QFNK65X5P050, Version A071408. Notes: Details of Pin 1 identifier are optional, but must be located within the indicated area. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. The inner tip of the lead may be either rounded or square. Seating Plane Top View Side View Bottom View A D E e b L View B View B Note 3 Note 2 Note 1 (Index Area D/2 x E/2) Note 1 (Index Area D/2 x E/2) 3232 θ