HV7361GA-G

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Document overview

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• PDF pages: 18

Technical content

Features

• H V C M O S® Technology for High Performance
• High Density Integration AC-coupled Pulser
• 0V to ±100V Output Voltage
• ±2.5A Source and Sink Minimum Pulse Current
• Up to 35 MHz Operating Frequency
• 2 ns Matched Delay Times
• 2.5V, 3.3V or 5V CMOS Logic Interface
• Built-in Two-terminal Low-noise Interface for HV7361
• Low Power Consumption and No Floating Power Supp ly Rails or Decoupling Capacitors

Applications

• Medical Ultrasound Imaging
• Piezoelectric Transducer Drivers
• Ultrasound Industrial NDT
• Pulse Waveform Generator General Description HV7360/HV7361 are high-voltage and high-speed pu lse generators with built-i n fast return-to-zero damping Field-Effect Transistors (FETs). An added feature to HV7361 is an integrated two-terminal lo w-noise T/R switch. These integrated circuits are designed not only for portable medical ultrasound image devices but also fo r NDT and test equipment applications. Both HV7360/HV7361 are composed of controller logic in terface circuits, level translators and AC-coupled Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) gate drivers. They also have high-voltage and high-current P-channel and N-channel MOSFETs as output stages. The peak output currents of each channel are gu aranteed to be over ±2.5A with up to ±100V of pulse swing. The AC coupling topology for the gate drivers not only saves two floating voltage supplies but also makes the PCB layout easier. Package Type 22-lead CABGA (Top View) High-Speed ±100V 2.5A Two-or-Three-Level Ultrasound Pulsers

DS20005570A-page 2  2016 Microchip Technology Inc. HV7360 Typical Application Circuit +/-100V 2.5A Three-level RTZ Transmit Pulsers +2.5/3.3V VLL VDD VH INA INB PE VL1GND INC IND VSS SP1 SP2 SN1 SN2 DP1 DP2 0 to -100V +10V 2.5/3.3V Logic Input DN2 DN1 VL2 VL3 +10V HVOUT 0 to +100V HV7361 Typical Application Circuit +2.5/3.3V VLL VDD VH PE INA INB INC IND VL1GND VSS SP1 SP2 SN1 SN2 DP1 DP2 0 to -100V +10V 2.5/3.3V Logic Input DN2 DN1 VL2 VL3 +10V 0 to +100V T/R SW XDCR to Rx LNA RX +/-100V 2.5A Three-level RTZ Transmit Pulsers with T/R Switch

 2016 Microchip Technology Inc. DS20005570A-page 3 HV7360/HV7361

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings † † Notic e: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. OPERATING SUPPLY VOLTAGES AND CURRENT Electrical Specifications: GND = 0V, VH = VDD = +10V, VL = VSS = 0V, VPE = 3.3V, VPP = +100V, VNN = –100V, TA = 25°C unless otherwise specified. Parameters Sym. Min. Typ. Max. Units Conditions Logic Supply Voltage Range VLL 2.25 — 3.63 V Supply Voltage VDD-VSS 4.75 — 11.5 V 4 ≤ VDD ≤ 11.5V Low Side Supply Voltage VSS –5.5 — 0 V Gate Drive High Side Voltage VH VSS+4 — VDD V VH-VL ≥ 4VGate Drive Low Side Voltage VL VSS — VDD-4 V Output Positive High Voltage VSP1,2 0 — 100 V Output Negative High Voltage VSN1,2 –100 — 0 V VDD Quiescent Current IDDQ — 50 — μA No input transitions, PE = 0VH Quiescent Current IHQ — 2 — μA VDD Quiescent Current IDDQ — 1 — mA No input transitions, PE = 1VH Quiescent Current IHQ — 2 — μA VDD Average Current IDD — 4 — mA One channel On at 5 MHz, No loadVH Average Current IH — 10 — mA Input Logic Voltage High VIH VPE-0.3 — VPE V For logic inputs INA, INB, INC and IND Input Logic Voltage Low V IL 0 — 0.3 V Input Logic Current High IIH — — 1 μA Input Logic Current Low IIL — — 1 μA PE Input Logic Voltage High VPEH 1.7 3.3 5.25 V For logic input PEPE Input Logic Voltage Low VPEL 0 — 0.3 V PE Input Impedance to GND RINPE 100 — — kΩ

AC ELECTRICAL CHARACTERISTICS Electrical Specifications: GND = 0V, VH = VDD = +10V, VL = VSS = 0V, VPE = 3.3V, VPP = +100V, VNN = –100V, TA = 25°C unless otherwise specified. Parameters Sym. Min. Typ. Max. Units Conditions Input or PE Rise and Fall Time tirf — — 10 ns Logic input edge speed requirement Input to Output Delay td1-4 — 7.5 — ns RLOAD = 1Ω Output Rise and Fall Time tr/f1-2 — 9.5 — ns CLOAD = 330 pF, RLOAD = 2.5 kΩ Rise and Fall Time Matching ∆trf — 2 — ns Channel to channelPropagation Matching ∆tdC2C — 1 — Propagation Delay Matching ∆tdD2D — ±2 — ns Device to device delay match PE On-time tPE-ON — — 5 µs –20 ~ 85°CPE Off-time tPE–OFF — — 4 Output to MOSFET Gate Cap COG — 10 — nF 100V X7S VH to VL3 Decoupling Cap CVH — 0.22 — µF 16V X7R HV7360/HV7361 DS20005570A-page 4  2016 Microchip Technology Inc.

ELECTRICAL CHARACTERISTICS

Electrical Specifications: GND = 0V, VH = VDD = +10V, VL = VSS = 0V, VPE = 3.3V, VPP = +100V, VNN = –100V, TA = 25°C unless otherwise specified. Parameters Sym. Min. Typ. Max. Units Conditions PULSER AND DAMPING P-CHANNEL MOSFET DC PARAMETERS Drain-to-source Breakdown Voltage BVDSS –200 — — V VGS = 0V, ID = –2 mA Gate Threshold Voltage VGS(th) –1 — –2.4 V VGS = VDS, ID = –1 mA Change in VGS(th) with Temperature ∆VGS(th) — — 4.5 mV/°C VGS = VDS, ID = –1 mA Gate-to-source Sh unt Resistor RGS 10 — 50 kΩ IGS = 100 µA, if applied Gate-to-source Zener Voltage VZGS 13.2 — 25 V IGS = –2 mA, if applied Zero-gate Voltage Drain Current IDSS — — –10 μA VDS = Maximum rating, VGS = 0V — — –1 mA VDS = 0.8 maximum rating, VGS = 0V, TA = 125°C ON-state Drain Current ID(ON) –1.2 — — A VGS = –5V, VDS = –25V Stat ic Drain -t o-sou rce O N-sta te  Resistance RDS(ON) — — 8.5 Ω VGS = –5V, ID = –150 mA — — 7 VGS = –10V, ID = –1A Change in RDS(ON) with Temperature ∆RDS(ON) — — 1 %/°C VGS = –10V, ID = –1 mA AC PARAMETERS Forward Transconductance G FS 400 — — mmho VDS = –25V, ID = –500 mA Input Capacitance CISS — 75 — pF VGS = 0V,  VDS = –25V,  f = 1 MHz Common Source Output Capacitance COSS — 21 — Reverse Transfer Capacitance CRSS — 6.5 — DIODE PARAMETERS Diode Forward Voltage Drop VSBD — — 1.8 V VGS = 0V, ISD = 500 mA Reverse Recovery Time of Body Diode trrBD — 300 — ns PULSER AND DAMPING N-CHANNEL MOSFET DC PARAMETERS Drain-to-source Breakdown Voltage BVDSS 200 — — V VGS = 0V, ID = 2 mA Gate Threshold Voltage VGS(th) 1 — 2.4 V VGS = VDS, ID = 1 mA

 2016 Microchip Technology Inc. DS20005570A-page 5 HV7360/HV7361 Change in VGS(th) with Temperature ∆VGS(th) — — –4.5 mV/°C VGS = VDS, ID = 1 mA Gate-to-source Sh unt Resistor RGS 10 — 50 kΩ IGS = 100 µA Gate-to-source Zener Voltage VZGS 13.2 — 25 V IGS = 2 mA Zero Gate Voltage Drain Current IDSS — — 10 μA VDS = Maximum rating,  VGS = 0V — — 1 mA VDS = 0.8 maximum rating, VGS = 0V, TA = 125°C ON-state Drain Current ID(ON) 1.3 — — A VGS = 5V, VDS = 25V 2.3 2.5 — VGS = 10V, VDS = 50V St a t i c D r a i n - t o - s o u r c e O N - s t a t e  Resistance RDS(ON) — — 6.5 Ω VGS = 5V, ID = 150 mA — — 6 VGS = 10V, ID = 1A Change in RDS(ON) with Temperature ∆RDS(ON) — — 1 %/°C VGS = 10V, ID = 1A AC PARAMETERS Forward Transconductance GFS 400 — — mmho VDS = 25V, ID = 500 mA Input Capacitance CISS — 56 — pF VGS = 0V, VDS = 25V, f = 1 MHz Common Source Output Capacitance COSS — 13 — Reverse Transfer Capacitance CRSS — 2 — DIODE PARAMETERS Diode Forward Voltage Drop VSBD — — 1.8 V VGS = 0V, ISD = 500 mA Reverse Recovery Time of Body Diode trrBD — 300 — ns HV7631 T/R SWITCH CHARACTERISTICS Parameters Sym. Min. Typ. Max. Units Conditions Breakdown Voltage from XDCR to Rx BVA-B ±130 — — V IA-B = ±1 mA Switch-on Resistance from XDCR to Rx RSW — 15 — Ω IA-B = ±5 mA VA-B Trip Point to Turn Off VTRIP — ±1 ±2 V Switch Turn-off Voltage VOFF — ±2 — V IA-B = ±1 mA Switch-off Current IA-B(OFF) — ±200 ±300 µA VA-B = ±130V Peak Switching Current IPEAK — ±60 — mA Turn-off Time TOFF — — 20 ns Turn-on Time TON — — 20 ns Switch-on Capacitance from A to B or B to A CSW(ON) — 21 — pF SW = On Switch-off Capacitance from A to B or B to A C SW(OFF) — 15 — pF VSW = 25V Small Signal Bandwidth BW — 100 — MHz RLOAD = 50Ω ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: GND = 0V, VH = VDD = +10V, VL = VSS = 0V, VPE = 3.3V, VPP = +100V, VNN = –100V, TA = 25°C unless otherwise specified. Parameters Sym. Min. Typ. Max. Units Conditions

TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, for all specifications TA = TJ = +25°C. Parameters Sym. Min. Typ. Max. Units Conditions TEMPERATURE RANGES Maximum Junction Temperature TJ(MAX) — 125 — °C Operating Temperature TA –20 — +85 °C PACKAGE THERMAL RESISTANCE 22-Lead CABGA JA — 106 — °C/W POWER-UP AND POWER-DOWN SEQUENCE (Note 1) Power-Up Power-Down Step Description Step Description

1 VLL 1 PE inactive

2 VDD, VH, VSS and VL with signal logic low 2 VPP and VNN off

3 VPP and VNN 3 VDD, VH, VSS and VL off

4 PE active 4 VLL off

Note 1: Poweri ng up or down in any arbitrary sequence will not cause any damage to the device. The power-up sequence and power-down sequence are only recommended to minimize possible inrush current. LOGIC CONTROL TABLE PE Input Pulse Output MOSFETs INA INB INC IND SP1 to DP1 DN1 to SN1 SP2 to DP2 DN2 to SN2

1 X X X ON X X X

0 X X X OFF X X X

0 X X X X OFF OFF OFF OFF

DS20005570A-page 6  2016 Microchip Technology Inc.

 2016 Microchip Technology Inc. DS20005570A-page 7 HV7360/HV7361

2.0 PAD DESCRIPTION

Table 2-1 details the description of pads in HV7360/HV7361. TABLE 2-1: PAD FUNCTION TABLE Pad Location HV7360 Symbol HV7361 Symbol Description A1 GND GND Driver and level translator circuit ground return (0V) A2 IND IND Damping N-FET control signal logic input, controlling N-FET2 A3 INC INC Damping P-FET control signal logic input, controlling P-FET2 A4 V SS VSS Negative voltage power supply (0V) A6 VDD VDD Positive voltage supply (+10V), should connect to an external decoupling cap to VSS (0V) A7 INB INB Pulsing N-FET control signal logic input, controlling N-FET1 A8 INA INA Pulsing P-FET control signal log ic input, controlling P-FET1 A9 PE PE Drive power enable Hi = On, Low = Off, logic ‘1’ volt age reference input (+2.5V to +3.3V) B2 VL2 VL2 Gate-drive negative voltage power supply (0V) B8 VL1 VL1 Gate-drive negative voltage power supply (0V) F4 VH VH Gate-drive positive voltage power supply (+10V) F7 VL3 VL3 VH to VL decoupling cap. The trace connecting VL1, VL2, and VL3 (0V) to ground plane should be as short as possible. G4 NC — No connection for HV7360 — RX T/R switch output for HV7361 P1 SP2 SP2 Source of P-FET2, positive high voltage power supply (0 to +100V) or GND P2 DP2 DP2 Drain of P-FET2, transmit pu lser output P3 DN2 DN2 Drain of N-FET2, transmit pulser output P4 SN2 SN2 Source of N-FET2, negative high voltage power supply (0 to –100V) or GND P5 NC — No connection for HV7360 — XDCR T/R switch input for HV7361 P6 SP1 SP1 Source of P-FET1, positive high voltage power supply (0 to +100V) P7 DP1 DP1 Drain of P-FET1, transmit pu lser output P8 DN1 DN1 Drain of N-FET1, transmit pulser output P9 SN1 SN1 Source of N-FET1, negative high voltage power supply (0 to –100V)

DS20005570A-page 8  2016 Microchip Technology Inc.

3.0 FUNCTIONAL DESCRIPTION

50%INA IOUT TX + DMP tr1 tr2tf1 td1 td3 td2 td4 50% 50% 50% 90% 90% 10% 10% IOUT INB +2.5/3.3V VLL VDD VH PE INA INB INC IND VL1GND VSS SP1 DP1 DN1 SN1 SP2 DP2 DN2 SN2 XDCR -100V +10V 2.5/3.3V Logic Input VL2 VL3 +10V +100V T/R SWRX FIGURE 3-1: Pulser Timing Test for HV7360/HV7361. IA-B -VOFF -VTRIP +130V IA-B = -200μA -130V IA-B = +200μA VA-B RSW = 15Ω +IPEAK -IPEAK +VTRIP +VOFF +1.0mA +1.0mA FIGURE 3-2: T/R Switch I-V curve for HV7361.

DS20005570A-page 10  2016 Microchip Technology Inc.

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

Legend: XX...X Product Code or Customer-specific information  Y Year code (last digit of calendar year)  YY Year code (last 2 digits of calendar year)  WW Week code (week of January 1 is week ‘01’)  NNN Alphanumeric traceability code  Pb-free JEDEC ® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part numbe r cannot be marked on one line, it will be carried over to the next line, t hus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo. XXXXXX YYWWNNN e3XX HV7360 1624111 GA XXXXXX YYWWNNN e3XX HV7361 1618555 GA

0.10 C 0.10 C

0.15 C A B

0.08 C (DATUM B) (DATUM A) TOP VIEW SIDE VIEW BOTTOM VIEW NOTE 1 0.08 C Microchip Technology Drawing C04-414A Sheet 1 of 2 22X For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 22-Ball Chip Array Ball Grid Array (JY) - 5x7 mm Body [CABGA] D E e e 2X (0.50) 2X (0.25) 22X Øb A C SEATING PLANE 0.10 C eE eE eD  2016 Microchip Technology Inc. DS20005570A-page 11 HV7360/HV7361

Microchip Technology Drawing C04-414A Sheet 2 of 2 REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Dimensioning and tolerancing per ASME Y14.5M 22-Ball Chip Array Ball Grid Array (JY) - 5x7 mm Body [CABGA] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Number of Terminals Overall Height Ball Diameter Overall Width Package Thickness Pitch Ball Height Units Dimension Limits A b e E

0.50 BSC

0.20 0.91 0.12 0.25 0.98 0.15

7.00 BSC

0.30 1.05 MAX Overall Length D 5.00 BSC 0.66 0.74 0.70 Overall Terminal Pitch eE 6.50 BSC Overall Terminal Pitch eD 4.00 BSC HV7360/HV7361 DS20005570A-page 12  2016 Microchip Technology Inc.

E MAX 6.50 Contact Pad Diameter (X22) X 0.25 Microchip Technology Drawing C04-2414A NOM 22-Ball Chip Array Ball Grid Array (JY) - 5x7 mm Body [CABGA] SILK SCREEN C1Contact Pad Spacing 4.00 Contact Pad to Contact Pad G 0.20 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: E E ØX G G  2016 Microchip Technology Inc. DS20005570A-page 13 HV7360/HV7361

DS20005570A-page 14  2016 Microchip Technology Inc. NOTES:

DS20005570A-page 15  2016 Microchip Technology Inc. APPENDIX A: REVISION HISTORY Revision A (June 2016)

• Converted Supertex Doc# DSFP- HV7360 and Supertex Doc# DSFP-HV7361 to Microchip DS20005570A.
• Meged HV7360 and HV7361 into one document.
• Replaced the 22-lead LFGA “LA” package with 22-lead CABGA “GA” package.
• Made minor text changes throughout the docu - ment.

 2016 Microchip Technology Inc. DS20005570A-page 16 HV7360/HV7361 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. Examples: a) HV7360GA-G: High-voltage High-speed Pulse Generator with Built-in Fast RTZ Damping FET, 22-lead CABGA Package, 364/Tray b) HV7361GA-G: High-voltage High-speed Pulse  Generator with Built-in Fast RTZ Damping FET and an Integrated Two-terminal Low-noise T/R Switch, 22-lead CABGA Package, 364/Tray PART NO. Device Device: HV7360 = High-voltage High-speed Pulse Generator with Built-in Fast RTZ Damping FETs HV7361 = High-voltage High-speed Pulse Generator with Built-in Fast RTZ Damping FETs and an Integrated Two-terminal Low-noise T/R Switch Packages: GA = 22-lead CABGA Environmental: G = Lead (Pb)-free/RoHS-compliant Package Media Type: (blank) = 364/Tray for GA Package XX Package - X - X Environmental Media Type Options

 2016 Microchip Technology Inc. DS20005570A-page 17 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application me ets with your specifications. MICROCHIP MAKES NO RE PRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting fr om such use. No licenses are conveyed, implicitly or ot herwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0668-6 Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal meth ods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC ® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==

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