HV7358

HV7358 MICROCHIP | Alldatasheet

Document overview

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• PDF pages: 50

Technical content

Features

• 16-Channel with Active Return to True Zero
• Up to ±80V Output Voltage and ±1.6A Output Current
• Programmable Output Current: 0.3A, 0.5A, 1.0A and 1.6A
• -40 dB Second Harmonic at 5 MHz, ±70V, 5-Cycle
• Built-in T/R Switch, Damper and Protection Diodes
• Built-in Linear Regulators for Floating Gate Driver
• Internal Low Jitter Phase-Locked Loop (PLL) Clock Multiplier for TX CH Clock
• 30 MHz to 80 MHz Input Clock Frequency in PLL Mode
• 30 MHz to 200 MHz Input Clock Frequency (in Non-PLL Mode) over Low-Voltage Differential Signaling (LVDS) Connection
• PLL Frequency Integer Multiplier x1, x2, x3, x4, x5, x6, x8
• Internal Clock Frequency (f C), up to 200 MHz to Allow a 5 ns Delay Resolution
• Ensured Synchronize Internal Transmit Clock Across Devices in the Same Phase
• PLL Circuit can be Bypassed and Shut Down to Reduce the Power Consumption
• Built-in Active Bleeder Circuit on VPP and VNN for Rapid Capacitor Discharging to Reduce the Time Required for Transmit Voltage Adjustment
• Configurable 12-Bit Delay for Beamform per Channel
• Stores up to Four TX CH Patterns with the Optional Local tOFF Counter, Allowing the TXCH Apodization Use of the Pulse-Width Modulator (PWM)
• T X CH Patterns, up to 255 Pulses with Programmable Pulse Width and Frequency
• Programmable Continuous Wave (CW) Frequency Divide Ratio, from 1 to 255 of the Input Clock Frequency
• Set-and-Go Feature in CW Mode Reduces the Digital Cross-Coupled Noise on PCB
• High-Speed LVDS SPI, Typical 200 MHz Operation Allows Fast Device Programming
• SPI Group Broadcast Mode for Fast Data Writing
• T w o - W i r e I2C Interface for Control and Status Reading
• 13 mm x 13 mm TFBGA Package with 0.8 mm Pitch

Applications

• Medical Portable Notebook Size and Trolley Size Ultrasound Imaging System
• NDT Ultrasound Pulsers and Industrial Use
• HV Pulse Pattern Generators General Description The HV7358 is a 16-Channel, 3-Level HV ultrasound transmitter with built-in digital beamformer. Each channel is capable of swinging up to ±80V with an active discharge back to 0V. The outputs can source and sink more than 1.6A to achieve fast output rise and fall times. The active discharge is also capable of ±1.6A for a fast return to ground. The HV7358 additionally features the programmable output current. The output current can be programmed via the I 2C Interface. All 16 channels have built-in output protection diodes and clamp diodes. The HV7358 features 16 Integrated T/R switches, a receive damping circuit and an active RTZ circuit. The active RTZ circuit has a typical R ON of 300Ω. The active RTZ circuit activates to discharge the transmitter’s output internal node when the transmit burst ends. The gate drivers for the output MOSFETs are powered by built-in linear floating regulators referenced to V PP and V NN. This direct coupling topology of the gate drivers eliminates the need for the gate driver and floating power supply circuit. The HV7358 features an internal low-jitter PLL clock multiplier for generating the delay clock for the built-in digital beamformer. The clock input has to accept an LVDS differential system clock with frequencies from 30 MHz (min.) to 80 MHz (max.) in PLL mode and a frequency from 30 MHz (min.) to 200 MHz (max.) in Non-PLL mode. The clock multiplier is programmable by x1, x2, x3, x4, x5, x6 and x8, and the maximum delay clock frequency can be up to 200 MHz, allowing incremental delays down to 5 ns. This feature elimi- nates the need for the power-hungry external clock synthesizer/multiplier to generate the high-frequency delay clock from the system/sampling clock. The transmitter outputs are synchronized with the delay clock to reduce phase noise. 16-Channel, 3-Level HV Ultrasound Transmitter with Built-in Transmit Beamformer

DS20005918A-page 2  2018 Microchip Technology Inc. Package Type FIGURE 1: HV7358 Pin Configuration. The 168-lead TFBGA, with an outline 13 mm x 13 mm body, 1.2 mm (max.) height and 0.8 mm pitch package, is available. Note that the backside of the die bias voltage, V SUB, must be connected to ground (0V, GND). Because this package is mounted onto a 4 x 4 inch, 4-layer, 1 oz copper PCB, the maximum allowable power dissipation is about 4W. The maximum junction temperature is lower than +130°C and the package has an ambient temperature of +55°C. 168-Ball 1ɪ mm x 1ɪ mm 0.8 mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A B C D E F G H J K L M N P TX1 TX2 TX3 TX4 TX5 TX6 TX7 TX8 TX9 TX10 TX11 TX12 TX13 TX14 TX15 CLKN CLKP SDIN SDIP CSN CSP CKON CKOP SDON SDOP CSON CSOP TCKNTCKP TRIGP TRIGN VGN LCKD OTPN CPLL VLL GND GND TXRW A1A0 A2 INV CW SLEEP SPIB SDLY DISC EN LPWM RSTN BEN DNC1 GND ETOETI AV V GND TX0 GND GND VSUB GND DNC7 VEECNFVWW CNFVWW VEECPF CPF VEECNFVWW CNFVWW VEECPF CPF R'E R'E R'E R'E R'E R'E R'E R'E R'E R'E RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 DNC5 DNC6 CPF VWW CNF VEE CPF VWW CNF VEE CPF VWW CNF VEEVV V VSUB DNC4 DNC8 PV PV RDCP RDCN PV PV PV PV DNC2 DNC3GND V GND GND VV>> V>> V>> VV s CNEGR'E R'E CNEG CNEG CNEGR'E R'E CNEG CNEG CNEGR'E R'E CNEG CNEG SCL SDA PEN DNC9 DNC10 VSUB VSUB DNC11 Top View

 2018 Microchip Technology Inc. DS20005918A-page 3 HV7358 Functional Block Diagram VDD VDD 2 µF RDCP RPP TRIG Ch0 DLY0[11:0] 12-Bit B-Delay CW-Phase TLP0[6:0] 7-Bit Local PWM tOFF_P Counter TLN0[6:0] 7-Bit Local PWM tOFF_N Counter EOT0 CH0 Logic and Gate Driver TX0 RX0 RX0 RGND VNF VPP VPF VNN VNEG PVDD RTZSW0 Rb TRSW0 RxDMP0 Rb RGND CKON CKOP OTPN ETO SPIB SLEEP DISC Overtemp and UVLO LPWM CLKP CLKN SDIN SDIP W[1:0] LPWM CW INV TCKP TCKN PEN LCKD AGND VSUB 2 µF GND VNN SUB -3 to -80V VNN 1 µF 100V CNF 2 µF VNF VDD LR VNF DISC VNF LR VNEG +2.5V 0.22 µF 2 µF +3 to +80V 2 µF 1 µF 100V VPF VGN VPP LR VPF I2C PLL TX15 X15 RX0 RX15 RGND VPPCPFAVDD 2 µF +5V VLL SCL SDA TGP0[6:0] 7-Bit tOFF_P Register SPI Global Wave Pattern and Launch Parameter Registers RPC0[7:0] 8-Bit Repeat Counter SPI 12-Bit or 26-Bit Beamform Fast Shift Registers VNEG CPLL SPIBC SPISEL VPF CSOP CSON CSN CSP PSELPLLEN I2C-ADJ SDOP SDON RDCN fC VNF VPP VPF VNN VNEG PVDD RTZSW15 Rb TRSW15 RxDMP15 Rb RGND BFEN DQ DQ TGN0[6:0] 7-Bit tOFF_N Register TGW0[8:0] 9-Bit tPulse_Width Register fT EN EOT[15:0] TRIG Ch15 CH15 Logic and Gate Driver RSTN BSEL BEN TXRW TGP1[6:0] 7-Bit tOFF_P Register RPC1[7:0] 8-Bit Repeat Counter TGN1[6:0] 7-Bit tOFF_N Register TGW1[8:0] 9-Bit tPulse_Width Register TGP2[6:0] 7-Bit tOFF_P Register RPC2[7:0] 8-Bit Repeat Counter TGN2[6:0] 7-Bit tOFF_N Register TGW2[8:0] 9-Bit tPulse_Width Register TGP3[6:0] 7-Bit tOFF_P Register RPC3[7:0] 8-Bit Repeat Counter TGN3[6:0] 7-Bit tOFF_N Register TGW3[8:0] 9-Bit tPulse_Width Register DLY1[11:0] 12-Bit B-Delay CW-Phase TLP1[6:0] 7-Bit Local PWM tOFF_P Counter TLN1[6:0] 7-Bit Local PWM tOFF_N Counter DLY15[11:0] 12-Bit B-Delay CW-Phase TLP15[6:0] 7-Bit Local PWM tOFF_P Counter TLN15[6:0] 7-Bit Local PWM tOFF_N Counter fREF PFD fIN Ch1 RD Back fCW0 CWFD[7:0] CWFD15[7:0] CW Frequency Divider Counter EOT15 fCW1 fCW15 fRT fRT SDLY Cntrl Bits I2C-ADJ TRIG 16-Channel Beamform Registers fC fC fC Digital Lock Detector CW CWFD1[7:0] CW Frequency Divider Counter CWFD0[7:0] CW Frequency Divider Counter -5V (B and CW) or 0V (B only) 0.1 µF GNDVPLL LR VPLL AVDD VNN VGN CNEG 2 µF VGN TRIGP TRIGN TRIG Loop Gain Filter÷N VCO fVCO fVCO Buff EN TRIG OPT UVLO DNC FCEN (FC) +5V BEN EN Reg. Reset Q D C fC (Start TRSW on delay) EOTin ETI PVDD PVDD 2 µF +5V EOTC GND

DS20005918A-page 4  2018 Microchip Technology Inc. Typical Applications FIGURE 2: Multiple HV7358 Devices are Working Together as a 64-Channel Pulser and Beamformer. For More Details about Daisy-Chained SPI Connections, see Figure 4-2 and the Associated Discussion. +2.5/3.3V FPGA I/Os CNRLBUS GND +2.5/3.3V +5V GND VLL AVDD VDD 0.22μF 2μF CPLL 0.1 2μF 2μF SUB to Ch 1-15 Rx0 Tx0 Rx0 RGND VNN VNF VPF VPP +3 to 80V CPF VPP 2μF 1 μF100V -3 to -80V CNF VNN 1μF100V2μF 1 of 16-Ch Shown RGND RxDMP0 TRSW0 RTZSW0 VDD VNEG Rb Rb VNEG RDP RPP RDN RNN TCLKP,N (LVDS33) TXRW TCKP/N TRIGP/N BEN W0,1 INV OTPN DISC CW SDA SCL A0,1,2 SDLY EN PEN ETO ETI LPWM I2C BUS 0.1μFx2 SPI BUS GND +2.5/3.3V +5V GND VLL AVDD VDD 0.22μF 2 μF 2 μF 2μF SUB to Ch 1-15 Rx0 Tx0 Rx0 RGND VNN VNF VPF VPP +3 to 80V CPF VPP 2μF 1 μF100V -3 to -80V 1μF100V CNF VNN 2μF RGND RxDMP0 TRSW0 RTZSW0 VDD VNEG Rb Rb CNEG RDP RPP RDN RNN SDOP, OTPN, ETO ETI, LCKD LOGIC PLL LOGIC PLL U3,U4 OTPN ETO/ETI LCKD CLKP/N SDIP/N CSP/N CKOP/N SDOP/N CSOP/N CKOP/N SDOP/N CSOP/N BEN W0,1 INV OTPN DISC CW SDA SCL A0,1,2 SDLY EN PEN ETO LCKD LPWM -5V 2μF VGN 2μF -5V 2μF VGN 2μF CPLL 0.1 +5V +5V VLL 2.2K2.2K VLL 2.2K2.2K 2.2K RSTN RSTN ETI LCKD CLKP/N SDIP/N CSP/N TXRW TCKP/N TRIGP/N 1 of 16-Ch Shown

 2018 Microchip Technology Inc. DS20005918A-page 5 HV7358

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings† Note 1: The design must try to meet the complete range of operating conditions, unless otherwise stated. 2: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. 3: This device is not required for CDM or MM ESD tests. 4: EIA/JESSD51-9, 102 mm x 114 mm x 1.6 mm PCB, Horizontal Still Air, 56 Thermal Vias, T A =+ 5 5 ° C , TJ = +125°C. † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability.

DS20005918A-page 6  2018 Microchip Technology Inc. OPERATING SUPPLY VOLTAGES Unless otherwise specified: VLL = +2.5V, AVDD =V DD =+ 5 . 0 V , VPP = +80V, VNN =- 8 0 V , VGN =- 5 . 0 V , VSUB =0 V , EN = PEN = BEN = 1, TA = 0° to +85°C Parameters Sym. Min. Typ. Max. Unit Conditions Positive Logic Supply V LL 2.375 2.50 3.625 V Positive Low-Voltage PLL Supply AV DD 4.75 5.0 5.25 VA V DD, PVDD and VDD must have separated bypass cap to GND when they are connected to the same +5V Positive Low-Voltage RTZ Supply PV DD 4.75 5.0 5.25 V Positive Low-Voltage Supply V DD 4.75 5.0 5.25 V Negative Voltage Supply V GN -5.25 -5.0 -4.75 V B mode and CW mode — 0— VGN = 0 (B mode only) Positive VPP Voltage Supply V PP 3.0 — 8.0 VI n C W m o d e 8.0 — 80 In B mode Negative VNN Voltage Supply V NN -8.0 — -3.0 In CW mode -80 — -8.0 In B mode Note: The device is not ensured to function outside the operating range. POWER-UP AND POWER-DOWN SEQUENCES Powering up/down in any arbitrary sequence will not cause any damage to the device. The powering up/down sequences are only recommended in order to minimize possible inrush current. Step Power-up Description Step Power-Down Description 1V LL On with Logic Signal Low 1 EN = 0 and the Logic Control Signal goes to Low 2A V DD, PVDD, VDD and VGN On 2 V PP and VNN Off 3V PP and VNN On 3 AV DD, VPDD, VDD and VGN Off 4E N = 1 and Logic Control Signal Active 4 V LL Off Note: The HV7358 is a high-voltage CMOS I 2C with multiple supply rails. It is highly recommended to add a Schottky diode at each voltage rail to GND, with 2~3A and sufficient BV, on the same PCB device(s) in mounted. Only one set of such diodes is needed per PCB.

 2018 Microchip Technology Inc. DS20005918A-page 7 HV7358 ELECTRICAL SPECIFICATIONS Electrical Specifications: VLL =+ 2 . 5 V , A VDD =V DD =+ 5 V , VPP =+ 8 0 V , VNN =- 8 0 V , VGN =- 5 V , VSUB =0 V , EN = 1, SPIB = BEN = 0, TA = +25°C Parameters Sym. Min. Typ. Max. Units Conditions VLL Quiescent Current I LLQ —2 . 07 . 0 μA EN = PEN = 0, fTCK =f CLK =0M H zAVDD Quiescent Current I AVDDQ —0 . 55 . 0 VDD Quiescent Current I DDQ —5 8 7 5 PVDD Quiescent Current I PVDDQ —6 . 0 1 5 VGN Quiescent Current I GNQ -5.0 -2.2 — VPP Quiescent Current I PPQ —2 . 08 . 0 VNN Quiescent Current I NNQ -14 -7.0 — VLL Current at Chip Enabled I LLEN —0 . 0 10 . 1 m A E N = 1, PEN = 0, fTCK =f CLK =0M H zAVDD Current at Chip Enabled I AVDDEN —0 . 31 . 5 VDD Current at Chip Enabled I DDEN —1 . 3 53 . 0 PVDD Current at Chip Enabled I PVDDEN —0 . 21 . 5 VGN Current at Chip Enabled I VGNEN -1.5 -0.2 — VPP Current at Chip Enabled I PPEN —0 . 11 . 0 VNN Current at Chip Enabled I NNEN -0.75 -0.67 — AVDD Current with PLL and Buffer Enabled IAVDD_PLL — 4.7 8.0 mA EN = PEN = BEN = 1, fTCK =4 0M H z , fC =1 6 0M H z(1) VLL CW Current I LLCW —3 . 0 1 0m A T X CH one-channel output 5 MHz, continuous, no loads, CW = 1, CWOC = 1, VPP/VNN =± 5 V(1)AVDD CW Current I AVDDCW —0 . 52 . 0 VDD CW Current I DDCW —8 . 0 1 5 PVDD CW Current I PVDDCW —1 . 4 55 . 0 VGN CW Current I GNCW -10 -4.6 — mA TX CH one-channel output 5 MHz, continuous, no loads, CW = 1, CWOC = 1, VPP/VNN =± 5 V(1)VPP CW Current I PPCW —1 3 1 8 VNN CW Current I NNCW -18 -10.5 — Note 1: Characterized only; not 100% tested in production.

DS20005918A-page 8  2018 Microchip Technology Inc. TABLE 1-1: TXCH OUTPUT P-CHANNEL MOSFET ON VPP Parameters Sym. Min. Typ. Max. Units Conditions B mode Output Current, BOC = 00b IOUT_P —0 . 9— A V PP = +25V, R L =1 Ω to GND, 20 ns pulse width at D% = 0.1%(1)B mode Output Current, BOC = 01b —0 . 6— B mode Output Current, BOC = 10b —0 . 3— B mode Output Current, BOC = 11b —0 . 1 5— B mode Output Current, BOC = 00b —1 . 6— V PP =+ 8 0 V , RL =1 Ω to GND, 20 ns pulse width at D% = 0.1% (1)B mode Output Current, BOC = 01b —1 . 1— B mode Output Current, BOC = 10b —0 . 6— B mode Output Current, BOC = 11b —0 . 3— On-Resistance B mode, BOC = 00b RONB_P —1 2— Ω ISD =1 0 0m A(1) On-Resistance, CW = 1, CWOC = 0 RONCW_P —3 6— A t V PP =+ 5 V(1) On-Resistance, CW = 1, CWOC = 1 —5 0— Note 1: Characterized only; not 100% tested in production. TABLE 1-2: TX CH OUTPUT N-CHANNEL MOSFET ON VNN Parameters Sym. Min. Typ. Max. Units Conditions B mode Output Current, BOC = 00b IOUT_N —- 1 . 0 — A V NN =- 2 5 V , RL =1 Ω to GND, 20 ns pulse width at D% = 0.1%(1)B mode Output Current, BOC = 01b —- 0 . 7 — B mode Output Current, BOC = 10b —- 0 . 3 6 — B mode Output Current, BOC = 11b —- 0 . 1 8 — B mode Output Current, BOC = 00b —- 1 . 6 — V NN =- 8 0 V , RL =1 Ω to GND, 20 ns pulse width at D% = 0.1%(1)B mode Output Current, BOC = 01b —- 1 . 0 — B mode Output Current, BOC = 10b —- 0 . 5 — B mode Output Current, BOC = 11b —- 0 . 3 — On-Resistance B mode, BOC = 11b RONB_N —1 0 . 5 — Ω ISD =1 0 0m A(1) On-Resistance, CW = 1, CWOC = 0 RONCW_N —4 2 — A t V NN =- 5 V(1) On-Resistance, CW = 1, CWOC = 1 —5 9 — Note 1: Characterized only; not 100% tested in production. TABLE 1-3: TX CH DAMPING P-CHANNEL MOSFET ON GND Parameters Sym. Min. Typ. Max. Unit s Conditions B mode Output Current, BOC = 00b IOUT_PDMP —1 . 7 — A R L =1 Ω, TXCH to VNN = -25V, 20 ns pulse width at D% = 0.1%(1)B mode Output Current, BOC = 01b —1 . 2 — B mode Output Current, BOC = 10b —0 . 6 — B mode Output Current, BOC = 11b —0 . 3 — B mode Output Current, BOC = 00b —2 . 3 — R L =1 Ω, TXCH to VNN = -80V, 20 ns pulse width at D% = 0.1%(1)B mode Output Current, BOC = 01b —1 . 5 — B mode Output Current, BOC = 10b —0 . 8 — B mode Output Current, BOC = 11b —0 . 4 — On-Resistance R ON_PDMP —8 . 1 — Ω ISD =1 0 0m A(1) Note 1: Characterized only; not 100% tested in production.

 2018 Microchip Technology Inc. DS20005918A-page 9 HV7358 TABLE 1-5: RTZ AUTO-BLEED AND V PP/VNN SUPPLY RAIL BLEED SWITCHES TABLE 1-4: TX CH DAMPING N-CHANNEL MOSFET ON GND Parameters Sym. Min. Typ. Max. Units Conditions B mode Output Current, BOC = 00b IOUT_NDMP —- 1 . 6— A R L =1 Ω, TXCH to VPP = +25V, 20 ns pulse width at D% = 0.1%(1) B mode Output Current, BOC = 01b —- 1 . 0— B mode Output Current, BOC = 10b —- 0 . 5— B mode Output Current, BOC = 11b —- 0 . 3— B mode Output Current, BOC = 00b —- 2 . 3— R L =1 Ω,TXCH to VPP =+ 8 0 V , 20 ns pulse width at D% = 0.1%(1) B mode Output Current, BOC = 01b —- 1 . 5— B mode Output Current, BOC = 10b —- 0 . 8— B mode Output Current, BOC = 11b —- 0 . 4— On-Resistance R ON_NDMP —4 . 2— Ω ISD =1 0 0m A(1) Note 1: Characterized only; not 100% tested in production. Parameters Sym. Min. Typ. Max. Units Conditions RTZSW On-Resistance R RTZSW —1 9 0— Ω ISD =± 1 . 0m A(1) Bleed Resistor to GND per Channel(1) Rb —1 7— k Ω RTZSW Off Withstand Voltage V RTZSW -80 — +80 V I SW = ± 1 0 0μA(1) RDCP Switch Output Current I RDCP —5 . 8— m A V PP = +80V(1) RDCN Switch Output Current I RDCN —- 6 . 0— V NN =- 8 0 V(1) Voltage of RDCP V RDCP 0— + 8 2 V I RDCP/N =± 0 . 6 A(PK) (1) Voltage of RDCN Bleed Pin for VNN VRDCN -82 — 0 Suggested Bleed Resistor Value to GND for RDCP and RDCN Pins RDCP —1 . 0— k Ω An external resistor (0.25W) for pin to GND suggested(2) RDCN —1 . 0— Note 1: Characterized only; not 100% tested in production. 2: Design guidance only. TABLE 1-6: TX CH OUTPUT ISOLATION DIODES AND BLEED RESISTOR Parameters Sym. Min. Typ. Max. Units Conditions Diode Forward Voltage V F —1 . 2— V I FM =3 0 0m A Forward Continuous Current(1) IFM —3 0 0— m A Peak Forward Pulse Current I FSM —3 . 0— A P W = 5 0 n s (1) Total Capacitance of Diode Pair C T — 3.5 — pF At 1 MHz, 1 dBm, 0V DC (1) Note 1: Characterized only; not 100% tested in production.

DS20005918A-page 10  2018 Microchip Technology Inc. TABLE 1-9: LOGIC INPUTS CHARACTERISTICS TABLE 1-7: TRSW AND RXDMP SWITCHES Parameters Sym. Min. Typ. Max. Units Conditions TRSW Analog Switch-On Resistor R TRSW —1 72 2 Ω ITRSW =± 1m A(1) TRSW Off Withstand Voltage V TRSW -80 — +80 V I SW = ±100 μA(1) RXCH to GND Protection Diode V F — ±0.8 ±1.2 V I F =± 2 0m A(1) RXDMP Switch-On Resistance R RXDMP —1 5— Ω ISD =± 1m A(1) RXCH Bleed Resistor to GND(1) Rb —1 7— k Ω RXCH Pin to GND Capacitance C RXG — — 7.0 pF At 1 MHz, 1 dBm, 0V DC (2) Note 1: Characterized only; not 100% tested in production. 2: Design guidance only. TABLE 1-8: BUILT-IN VOLTAGE LINEAR REGULATORS Unless otherwise specified: VLL =+ 2 . 5 V , A VDD =V DD =+ 5 V , VPP = +80V, VNN =- 8 0 V , VGN =- 5 V , VSUB =0 V , E N=1, PEN = BEN = 0, TA =+ 2 5 ° C Parameters Sym. Min. Typ. Max. Units Conditions Output P-Channel Gate Drive Voltage Referenced to VPP VPF -4.9 -5.0 -5.1 V (V GN –V PP)<- 8 . 0 V Output N-Channel Gate Drive Voltage Referenced to VNN VNF 5.1 5.0 5.3 V (V DD –V NN)>+ 8 . 0 V Output P-Channel Gate Drive Voltage Referenced to GND VNEG -5.1 -5.0 -4.9 V CW = 0 Output PLL Voltage Referenced to GND VPLL 4.4 4.6 4.8 V PEN = 1 Dropout Voltage of (VPP –V GN) V DOPF — 3.5 — V 100 mA load, drop to 95% at worst case(1) Dropout Voltage of (VDD –V NN)V DONF —3 . 5— V Dropout Voltage of (VNEG –V NN)V DONEG — 1.36 — V 10 mA load, drop to 95% at worst case(1) Dropout Voltage of (AVDD –V PLL)V DOPLL — 0.31 — V 1 mA load, drop to 95% at worst case(1) Note 1: Characterized only; not 100% tested in production. Parameters Sym. Min. Typ. Max. Units Conditions Rise/Fall Time of Input Logic Signals t rf — — 3.5 ns 10% to 90% at pin(s) (2) Input Logic Low Voltage(1) VIL 0— 0 . 2 V LL V Input Logic High Voltage(1) VIH 0.8 — V LL V Input Logic Low Current I IL -0.1 — — μA Input Logic High Current I IH ——1 . 0 μA Input Capacitance(2) CIN —2 . 03 . 0 p F EN Switching On Time t EN —3 0 0 — μs 50% EN rise to TX CH ready(2) EN Switching Off Time — 300 — ns 50% EN fall to TX CH, all output FETs on HV rails are off(1) Internal Reset Signal Width(2) tRST 100 — 150 ns Reset Input Low Time(1) tRSTN 100 — — ns Note 1: Characterized only; not 100% tested in production. 2: Design guidance only.

 2018 Microchip Technology Inc. DS20005918A-page 11 HV7358 TABLE 1-10: OVERTEMPERATURE AND UNDERVOLTAGE PROTECTIONS Parameters Sym. Min. Typ. Max. Units Conditions OTP Output Maximum Pull-up V OH —— 5 . 2 5V OTP Output Low Maximum Voltage V OL —— 0 . 1 V A t 1 0 0 μA —— 0 . 4 V A t 4 m A OTP Output High Current I OFF —— 1 0 μA 0° to +125°C, at 5.25V pull-up (1) Thermal Shutdown Trip Point T TRIP +135 — +155 °C OTP = H when thermal shutdown occurs(1) Thermal Shutdown Hysteresis T HYS —4 0 — VDD Ok Voltage V DDUVON 3.9 4.2 4.5 V External power supply inputs(1) VDD UVLO Trip Voltage V DDUVOFF 3.7 3.95 4.3 VLL Ok Voltage V LLUVON 1.65 1.75 1.85 VLL UVLO Trip Voltage V LLUVOFF 1.5 1.6 1.7 VPLL Ok Voltage V PLLUVON — 3.8 — +4.5V LR for PLL circuit (1) VPLL UVLO Trip Voltage V PLLUVOFF —3 . 3 — VNEG Ok Voltage V NGUVON — –4.0 — -5V LR for RTZ P-FET gate drive circuit(1) VNEG UVLO Trip Voltage V NGUVOFF — –4.4 — VPP-PF Ok Voltage V PP-PFON — –3.4 — V Floating ±5V LRs for HV P-FET and N-FET gate drive circuit VPP-PF UVLO Trip Voltage V PP-PFOFF — –3.8 — VNF-NN Ok Voltage V NF-NNON —3 . 8 — VNF-NN UVLO Trip Voltage V NF-NNOFF —3 . 4 — Note 1: Characterized only; not 100% tested in production.

DS20005918A-page 12  2018 Microchip Technology Inc. TABLE 1-11: SWITCH TIMING CHARACTERISTICS Unless otherwise specified: VLL =+ 2 . 5 V , A VDD =V DD =+ 5 V , VPP =+ 8 0 V , VNN =- 8 0 V , VGN =- 5 V , VSUB =0 V , E N=1, PEN = BEN = 0, TA =+ 2 5 ° C Parameters Sym. Min. Typ. Max. Units Conditions SDI Valid to CLK Setup Time(1) t1 2.0 — — ns CLKP to SDI Data Hold Time(1) t2 2.0 — — ns CLK High Time % of 1/fCLK(1) t3 45 — 55 % CLK Low Time % of 1/fCLK (1) t4 45 — 55 % CSN Minimum High Time Between SPI Words t 5 3-cycle CLK Designed for f CLK =2 0 0M H z(2) CLKP Rise to CSN Rise(1) t6 —2 . 0 — n s CSON Fall to CLKP Rise(1) t7 —2 . 0 — n s SDOP Delay from CLKP Rise t 8 — 2.0 3.0 ns SPIB = 0, 3 pF Load(1) CSN Rise to CLK Rise(1) t9 —2 . 0 — n s CSN Rise to TXRW or to SPIB(2) t10 9-cycle TCK CLK Start, TXRW, SPIB to CSN Fall(2) t11 — 200 — ns SDIP to SDOP Delay t 12 — 10 — ns SPIB = 1, 3 pF Load(1) TXRW Rise to CLKP Rise Edge(1) t13 —6 . 0 — n s TXCH Ready Latency after TXRW = 1(2) t14 12-cycle TCK SPI or I2C Ready after TXRW = 0(2) t15 2-cycle TCK TRIG Rise to CLK Rise Setup Time t 16 0.5-cycle ns W0 or W1 Pin Ready to TXRW Rise Time t 17 3-cycle ns W0 or W1 Pin Holdup Time t 18 3-cycle ns TRIG High Time(2) t19 6-cycle TCK TXRW Rise to TRIG Rise Time t 20 3-cycle ns CW Pin Changing to TXRW Rise Time t 21 3-cycle ns Mode changing time (2) ETO High to TXRW High or Low Time t 22 2.0 — 10 ns Minimum TXRW Low Time t 23 — 1.2 — µs Must wait for the TRSW to completely turn off(2) This Chip ETO Change Time(1) t24 —4 5 — n s fC Clock Cycles before ETO Rise(1) t25 11-cycle TCK ETI High to fC Clock Rise Setup Time(1) t26 0.5-cycle ns Minimum TCK Cycles after ETI Rise t 27 TRDLY[4:0] + (6-cycle) TCK Stop TCK for power saving in RXCH time(2) Minimum TCK Cycles before TXRW = 0 t28 6-cycle TCK Delay Finish to TXCH Launch Latency Time(2) tLatency 5-cycle TCK SPI Data Clock Resynchronization Time(2) tSync 32-cycle CLK Second Harmonic Distortion HD2 — -43 -40 dB HD2 at 5M H z , 5-cycle pulse inversion, ±70V, in 100 µs appart, 220 pF/2.5k Load. The tr, tf, tdr, tdf values, at ±70V, 220 pF //2.5k Load. Output Rise Time from 0V to VPP tr —1 2 1 4n s Output Fall Time from 0V to VNN tf —1 2 1 4n s Output Rise Time from VNN to VPP tr2 —2 4 2 6n s Output Fall Time from VPP to VNN tf2 —2 4 2 6n s Propagation Delay Rise Time 1 t dr —2 0 — n s Propagation Delay Fall Time 1 t df —2 0 — n s Delay Time Matching Δtd — ±1.0 — ns P to N, channel to channel matching in IC, at ±70V, 220 pF //2.5k Load(1) Note 1: Characterized only; not 100% tested in production. 2: Design guidance only.

 2018 Microchip Technology Inc. DS20005918A-page 13 HV7358 TABLE 1-12: SPI AND I 2C I/O CHARACTERISTICS Unless otherwise specified: VLL =+ 2 . 5 V , A VDD =V DD =+ 5 V , VPP =+ 8 0 V , VNN =- 8 0 V , VGN = -5V, VSUB =0 V , E N=1, TA =+ 2 5 ° C Parameters Sym. Min. Typ. Max. Units Conditions LVDS Differential Input: CLKP/N, SDIP/N, CSP/N and TRIGP/N Pins SPI LVDS Clock I/O Frequency f CLK 30 — 200 MHz SPI LVDS Clock Input Duty Cycle(1) D% 45 50 55 % AC Differential Sensitivity V SNS 150 200 — mV P-P at 200 MHz (1) AC Common-Mode Voltage(1) VCMAC 1— 1 . 4 V DC Common-Mode Voltage V REF VLL/2 – 0.2 V LL/2 V LL/2 + 0.2 V CLK Input Offset Voltage(1) VOFFSET —3 0 — m V LVDS DC Input Differential Voltage V ID 100 350 600 mV Same as FPGA I/O CLK Input Resistance R IN_CLK —5 . 0 —k Ω CLK Input Capacitance(2) CIN_CLK —4 . 0 —p F CLK Input Bias Current I BIAS_CLK — 1.0 — mA At input 200 mVp-p LVDS Differential Output: CKOP/N, SDOP/N and CSOP/N Pins LVDS DC Output Differential Voltage V OD 300 500 — mV R T =1 0 0Ω, termination resistor at the P to N LVDS input pins(2) LVDS DC Output Common-Mode Voltage VOCM VLL/2 – 0.2 V LL/2 V LL/2 + 0.2 V LVDS Output High Voltage for P&N Pins V OH — 1.38 1.6 V LVDS Output Low Voltage for P&N Pins V OL 0.9 1.03 — V Output Current for P&N Pins I O_LVDS ±3.0 ±3.5 ±5.0 mA Output Rise Time t RO —1 . 5 —n s Output Fall Time t FO —1 . 5 —n s CKOP/N Output Clock Duty Cycle D% CKO 49.5 50 50.5 % At 200 MHz (2) Output Rise Propagation Delay t DRO — 1.5 2.0 ns CKOP 50% to CKN 50%(2) Output Fall Propagation Delay t DFO —1 . 52 . 0 n s BEN Enable Time t BEN — 0.7 1.0 ns BEN 50% to CLK CKO, SDO and CSO Logic High V OHO 1.95 — — V CKO, SDO and CSO Logic Low V OLO —— 0 . 3 5 V Note 1: Characterized only; not 100% tested in production. 2: Design guidance only. 3: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to as the VIHmin of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 4: The maximum tHD,DAT only has to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. 5: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement of a tSU,DAT of 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must out- put the next data bit to the SDA line, tRmax +t SU,DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. 6: The maximum tF for the SDA and SCL bus lines of 300 ns is longer than the specified maximum tof for the output stages, 250 ns. This allows series protection resistors (Rs) to be connected between the SDA/SCL pins and the SDA/SCL bus lines. 7: I/O pins of Fast mode devices must not obstruct the SDA and SCL lines if VLL is switched off.

DS20005918A-page 14  2018 Microchip Technology Inc. Fast I2C Interface I/O: SDA and SCL Pins Low-Level Input Voltage V IL -0.5 — 0.3 * V LL V High-Level Input Voltage V IH 0.7 * VLL — 0.5 + V LL V Hysteresis of Schmitt Trigger Inputs(2) Vhys 0.05 * VLL —— V Pulse Width of Spikes (which must be by the input filter suppressed)(1) tSP 0 — 50 ns Low-Level Output Voltage (open-drain or open-collector) VOL6 0— 0 . 6 V I SINK =6m A (1) Output Fall Time from VIHmin to VILmax with a bus capacitance of 10 pF to 400 pF, I = 6 mA(1) tof6 20 — 250 (6) ns Input Current I i -10(7) —1 0 (7) µA 0.4V to 2.8V I/O Capacitance(2) Ci — — 10 pF SCL Clock Frequency f SCL —— 4 0 0 k H z Bus Free Time, Stop to Start t BUF 1.3 — — µs Hold Time (Repeated) Start Condition t HD,STA 0.6 — — µs After this period, 1st Low Period of the SCL Clock t LOW 1.3 — — µs High Period of the SCL Clock t HIGH 0.6 — — µs Setup Time (Repeated) Start Condition t SU,SAT 0.6 — — µs Data Hold Time t HD,DAT 0(3) —0 . 9 (4) µs Cbus compatible Setup Time for Stop Condition t SU,STO 0.6 — — µs Data Setup Time t SU,DAT 100(5) —— n s Rise Time of SDA or SCL t R 20 — 300 ns Fall Time of SDA or SCL t F 20 — 300 ns Capacitive Load for SDA or SCL C b —— 4 0 0 p F TABLE 1-12: SPI AND I 2C I/O CHARACTERISTICS (CONTINUED) Unless otherwise specified: VLL = +2.5V, AVDD =V DD =+ 5 V , VPP =+ 8 0 V , VNN =- 8 0 V , VGN = -5V, VSUB =0 V , E N=1, TA =+ 2 5 ° C Parameters Sym. Min. Typ. Max. Units Conditions Note 1: Characterized only; not 100% tested in production. 2: Design guidance only. 3: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to as the VIHmin of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 4: The maximum tHD,DAT only has to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. 5: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement of a tSU,DAT of 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must out- put the next data bit to the SDA line, tRmax +t SU,DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. 6: The maximum tF for the SDA and SCL bus lines of 300 ns is longer than the specified maximum tof for the output stages, 250 ns. This allows series protection resistors (Rs) to be connected between the SDA/SCL pins and the SDA/SCL bus lines. 7: I/O pins of Fast mode devices must not obstruct the SDA and SCL lines if VLL is switched off.

 2018 Microchip Technology Inc. DS20005918A-page 15 HV7358 TABLE 1-13: TX CH CLOCK AND PLL AC/DC CHARACTERISTICS Over operating conditions unless otherwise specified: VLL =+ 2 . 5 V , A VDD =V DD =+ 5 V , VGN =- 5 V , VPP =+ 8 0 V , VNN = -80V, EN = 1, TA =+ 2 5 ° C Parameters Sym. Min. Typ. Max. Units Conditions VPLL Regulator Output Voltage V CPLL 4.37 4.50 4.64 V ±3%, T A = 5° to +75°C PEN = 1 PLL Current Consumption I VPLL —5 . 0 8 . 0 m A V CPLL = 4.50V(2) PEN = 0 PLL Current Consumption — — 3.0 µA Input Clock Frequency in Non-PLL mode f TCK 30 — 200 MHz PEN = LCKD = 0(2) Input Clock Frequency in PLL mode 30 — 80 MHz PEN = LCKD = 1(2) Clock Output Duty Cycle(2) D% 45 50 55 % VCO Frequency Range f VCO 160 240 250 MHz At pin DNC1 (1) VCO Frequency Range Ratio (fmax/fmin)(2) rfvco —1 . 5 6— — Lock Time t LOCK — 300 500 µs f REF = 80 to 96 MHz jump(1) Bandwidth of PLL Loop BW — 1.0 — MHz In design now (2) fVCO Frequency Divider N 1 — 8 — Integer number: 1,2,3,4,5,6, 8 (1) Output fC Clock Integrated RMS Jitter t J —1 52 0p s f VCO =2 4 0M H z , fTCK =8 0 M H z(2) Output fC Clock Integrated RMS Jitter t JS —1 5—p s f VCO = 240 MHz, fTCK =8 0M H z w/1%, 10 kHz VCPLL change(2) Static Phase Error, 500 µs after LCKD =1 EPH — ±50 ±100 ps f VCO =2 4 0M H z , fTCK =8 0 M H z(2) Worst-Case Phase Jump Relock Time t PJ ——1 0µ s f VCO =2 4 0M H z , fTCK =8 0 M H z(2) Note 1: Characterized only; not 100% tested in production. 2: Design guidance only.

DS20005918A-page 16  2018 Microchip Technology Inc. TABLE 1-14: TRSW AND RXDMP SWITCHES SW ITCHING TIMING AND SPIKE VOLTAGES Over operating conditions unless otherwise specified: VLL =+ 2 . 5 V , A VDD =V DD = +5V, VGN =- 5 V , VPP =+ 8 0 V , VNN = -80V, EN = 1, TA =+ 2 5 ° C Parameters Sym. Min. Typ. Max. Units Conditions TRSW Switch-On Fixed Propagation Delay t TRSW — 200 — ns Addition to TRDLY<4:0>(1) TRSW Switch-On Programmable Delay 8 — 288 1/f C TRDLY<4:0> value(1) TRSW Switch-Off Delay Time — 1.0 1.2 μs TXRW fall to TRSW off, before TXCH next launch(1) RTZSW Switch-On Delay Time t RTZSW 8— 2 8 8 1 / f C TRDLY<4:0> I2C register value(1) RTZSW Switch-Off Delay Time — 105 — ns TXRW fall to RTZSW off (1) RXDMP Damp Switch-On Delay Time t RXDMP — 15.2 — ns TXRW fall to RXDMP on (1) RXDMP Damp Switch-Off Delay Time — 1.1 — μs TRSW on to RXDMP off (1) TXCH Output Frequency Range in B mode f OUT —3 0 4 0M H z 1 0 0 Ω resistor load(1) TRSW Turn-On Spike Voltage at TXCH Pins V TRSW_ON — 80 110 mVpk TX CH 50Ω load to GND(1) TRSW Turn-Off Spike Voltage at TXCH Pins V TRSW_OFF -90 -70 — RXDMP Turn-On Spike Voltage at RXCH Pins V RXDMP_ON —4 5 6 0 R X CH 300 load to GND(1) RXDMP Turn-Off Spike Voltage at RXCH Pins V RXDMP_OFF -70 -60 — Note 1: Characterized only; not 100% tested in production. TABLE 1-15: TEMPERATURE SPECIFICATIONS Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Operating Ambient Temperature Range T O 0— + 8 5 ° C Storage Temperature Range T A -55 — +150 °C Junction Temperature T J — +125 — °C Package Thermal Resistances Thermal Resistance Junction to Ambient JA — +16.5 — °C/W JEDEC (2S2P) 4-Lead PCB, 114.3 mm x 76.2 mm x 1.6 mm, T A = +85°CThermal Resistance Junction to PCB JB —+ 4 . 5—° C / W Thermal Resistance Junction to Case Top

 2018 Microchip Technology Inc. DS20005918A-page 17 HV7358

2.0 TYPICAL PERFORMANCE CURVES

Note: VIN =1 2 V , A VCC =D VCC =5 V , TA = +25°C unless otherwise specified. FIGURE 2-1: LV Supply Quiescent Current vs. Temperature (±70V, 5 MHz, 5 Cycles, PRF 2.5 kHz). FIGURE 2-2: HV Supply Quiescent Current vs. Temperature (±70V, 5 MHz, 5 Cycles, PRF 2.5 kHz). FIGURE 2-3: LV Supply Current vs. TX Frequency (±70V, 5 Cycles, PRF 2.5 kHz). FIGURE 2-4: HV Supply Current vs. TX Frequency (±70V, 5 Cycles, PRF 2.5 kHz). Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. -10 02 5 8 5 Current (μA) Temperature (°C) ILLQ IAVDDQ IPVDDQ IDDQ IGNQ -12 -10 02 5 8 5 Current (μA) Temperature (°C) IPPQ INNQ -10 2.5 5 10 Current (mA) Frequency (MHz) ILL IDD IAVDD IPVDD IGN -1.5 -0.5 0.5 1.5 2.5 5 10 Current (mA) Frequency (MHz) IPP INN

 2018 Microchip Technology Inc. DS20005918A-page 19 HV7358

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION HV7358 Symbol Description C1, H1, L1, P1 V LL Logic Circuit Power Supply Pin: 0.22 µF ceramic cap to GND per pin. T4 AV DD Positive Power Supply Pin for Logic and PLL: +5V, 0.1 µF + 1 µF ceramic caps to GND per pin. C4, E3, H3, L3, P4, P6 VDD Positive Voltage Supply Input Pins: +5V, 1 µF ceramic cap to GND per pin. A7, B7, G8, H8, R7, T7 PVDD Positive Voltage Supply Input Pins for the RTZ N-Gate Drive: +5V, 1 µF ceramic cap to GND per pin. A13, B13, D15, H15, M15, R13, T13 VPP TXCH Positive Power Supply: +3V to +80V, 2 µF ceramic X7R cap to GND per pin. A15, B15, F15, K15, P15, R15, T15 VNN TXCH Negative Power Supply: -3V to -80V, 2 µF ceramic X7R cap to GND per pin. A12, B12, C15, G15, L15, R12, T12 CPF Internal V PF Gate Drive Voltage Linear Regulator Output Bypass Cap: 2 µF 10V to VPP per pin. A14, B14, E15, J15, N15, R14, T14 CNF Internal V NF Gate Drive Voltage Linear Regulator Output Bypass Cap: 2 µF 10V to VNN per pin. T5 A GND PLL Circuit Ground and 0V. C2, C5, F3, H2, J3, L2, M3, P2, P5, GND Circuit Ground and 0V. A8, B8, C9, D9, E9, F9, G9, H9, J8, K8, L9, M9, N9, P9, R8, T8 R GND The TXCH and RXCH Signal Return Grounds (0V): RGND must connect to the GND plane on the PCB. A5 V GN -5V Power Supply Input Pins: Must add an X7R 2 µF bypass cap to GND per pin. VGN can be connected to GND when VPP > 10V and VNN < -10V for B mode only. A9, B9, J9, K9, R9, T9 CNEG Internal V NEG Gate Drive Voltage Linear Regulator Output Bypass Cap: 2 µF to GND per pin. T6 C PLL Internal VPLL Linear Voltage Regulator Output Bypass Cap: 0.1 µF and 2 µF to GND if the built-in PLL functions are used. It can be disabled if EN = 1 and PEN = 0 to save power dissipation. K3 EN Device Enable Pin, Active-High: When EN = 0, all the TXCH outputs are high-Z. N3 BEN LVDS Output Buffer Enable Pin: BEN = 1 to enable the LVDS output buffers, BEN = 0 to disable when BSEL = 0. The BFEN bit overrides the BEN pin function, BEN pin has no effect on buffer enable if the I2C bit, BSEL = 1; vice versa if BSEL = 0. The buffer enable is controlled by the BEN pin only. F2 SLEEP Chip Sleep Mode Enable Input: If SLEEP = 1, the device is in Power-Saving and Sleep mode, all register data will be preserved and all clocks freeze, except for the I2C interface. When SLEEP =0, device wakes up, the I2C is ready to transmit in about 3 µs. G3 PEN PLL Enable Input: PEN = 1 to enable the internal PLL; PEN = 0 to disable the PLL circuit, including locked circuits. The PEN pin function can be overridden by the I2C register, PENOVR bit = 1. If need be, PEN = 1, must pull the PEN pin high prior to EN = 1.

DS20005918A-page 20  2018 Microchip Technology Inc. TCKP TCKN LVDS/LVCMOS Differential Inputs for Transmit Clock: Can be driven by LVDS-2.5V or BLVDS-2.5V via DC coupled. The inputs can also be driven by LVDS-1.8V/2.5V via AC coupled. In the differential input cases, a 100 LVDS termination resistor must connect to the input pin pair differentially. A single TCKP or TCKN can also be driven by LVCOM-2.5 single-ended output, with biasing the other input to 1.25 VDC, and a bypass capacitor to GND. A16, B16, C16, D16, E16, F16, G16, H16, J16, K16, L16, M16, N16, P16, R16, T16 TX[15:0] High-Voltage Pulser B mode and CW Output of the Ch[15:0]. A10, B10, C10, D10, E10, F10, G10, H10, J10, K10, L10, M10, N10, P10, R10, T10 RX[15:0] T/R Switch Output of the Ch[15:0]. R11 RDCP V PP Bypass Caps Discharge Resistor Pin: Connect a power resistor from RDCP to GND. T11 RDCN V NN Bypass Caps Discharge Resistor Pin: Connect a power resistor from RDCN to GND. K2 DISC Fast Discharging Enable Input: DISC = 1, activate VPP and VNN bypass caps discharging. CLKP CLKN SPI Clock Inputs: Can be driven by LVDS-2.5V or BLVDS-2.5V via DC coupled. The inputs can also be driven by LVDS-1.8V/2.5V via AC coupled. In the differential input cases, a 100Ω LVDS termination resistor must connect to the input pin pair differentially. A single CLKP or CLKN can also be driven by LVCOM-2.5 single-ended output, with biasing the other input to 1.25 VDC, and a bypass capacitor to GND. SDIP SDIN SPI Data Inputs: Can be driven by LVDS-2.5V or BLVDS-2.5V via DC coupled. The inputs can also be driven by LVDS-1.8V/2.5V via AC coupled. In the differential input cases, a 100Ω LVDS termination resistor must connect to the input pin pair differentially. A single SDIP or SDIN can also be driven by LVCOM-2.5 single-ended output, with biasing the other input to 1.25 VDC, and a bypass capacitor to GND. CSP CSN SPI Chip Select Inputs: CSN is active-low. The inputs can be driven by LVDS-2.5V or BLVDS-2.5V via DC coupled They can also be driven by LVDS-1.8V/2.5V via AC coupled. In the differential input cases, a 100Ω LVDS termination resistor must connect to the input pin pair differentially. A single CSP or CSN can also be driven by LVCOM-2.5 single-ended output, with biasing the other input to 1.25 VDC, and a bypass capacitor to GND. R3 CSOP SPI Chip Select Output, LVDS Positive. T3 CSON SPI Chip Select Output, LVDS Negative. R2 SDOP SPI Data Output, LVDS Positive. T2 SDON SPI Data Output, LVDS Negative. R1 CKOP SPI Clock Output, LVDS Positive. T1 CKON SPI Clock Output, LVDS Negative. E2 SPIB SPI Fast Programming Interface SPIB Pin: SPIB = 1 to enable the SPI Broadcasting mode. SPIB = 0 to enable the Daisy-Chained mode. A4, B4 W0, W1 Waveform Pattern Select Input: W[1:0] Select one waveform pattern to transmit or write/read. TABLE 3-1: PIN FUNCTION (CONTINUED) HV7358 Symbol Description

 2018 Microchip Technology Inc. DS20005918A-page 21 HV7358 TRIGP TRIGN TX Trigger Inputs: TRIGP is active-high. The inputs can be driven by LVDS-2.5V or BLVDS-2.5V via DC coupled. They can also be driven by LVDS-1.8V/2.5V via AC coupled. In the differential input cases, a 100Ω LVDS termination resistor must connect to the input pin pair differentially. A single TRIGP or TRIGN can also be driven by LVCOM-2.5 single-ended output, with biasing the other input to 1.25 VDC, and a bypass capacitor to GND. E1 TXRW If TXRW = 0, the Chip is in SPI or I 2C Read/Write mode; if TXRW = 1, it is in TXCH or RXCH mode: TXRW rise edge will set all the launch counters, and reset the TXCH and RXCH state machine for ready to launch. J2 CW CW Enable Logic Input: CW = 1 for CW mode, CW = 0 for B mode. J1 INV Pulse Inversion Logic Input Selects the Polarity of the First Transmit Pulse: If INV = 1, the first transmit pulse is a negative pulse. If INV = 0, the first transmit pulse is a positive pulse. INV also selects the state of the transmitter output pins when the device is disabled. When EN = 0 and INV = 1, all the transmitter output pins are high-Z. If EN = 0 and INV = 0, all the transmitter output pins are grounded. G1 SCL I 2C Clock Input: Must pull up to 3.3V with a 2.2 kΩ resistor. G2 SDA I 2C Data Input: Must pull up to 3.3V with a 2.2 kΩ resistor. D1, D2, D3 A0, A1, A2 I 2C Device’s Address Inputs: For selecting up to eight different I2C interfaces on the same bus. K1 SDLY If SDLY = 0, the SPI Writes to the Registers of DLYch[11:0], TLPch[6:0] and TLNch[6:0]: The SPI performs a 26-bit long word data transfer per channel. When SDLY =1, the SPI writes the Delay registers, DLYch[11:0] only. The SPI performs a 12-bit word data transfer per channel. F1 LPWM SPI Register Block Select Pin: If LPWM = 0, the SPI write or TXCH launch selects the global register block, which consists of four wave pattern parameters of pulse width, global PWM time-off and launch pulse number in a TXCH burst. If LPWM = 1, select the local per channel different PWM Time-Off and Beamforming Delay registers for the SPI write or TXCH launch. P3 LCKD PLL Locked Indicator Open-Drain Output: The LOCK output is active-high when the PLL is locked. Alternatively, the PLL locking status can be read from the I2C Status register. Leave this pin open (NC) when not used. A6, A11, B6, B11 VSUB The substrate of the die must be grounded for good RF and DC (0V) point of view. C3 OTPN Overtemperature or Undervoltage Flag: This pin is an open-drain output. OTPN = 0 when an overtemperature or undervoltage event happens. The error information will be logged in the I 2C Flag register at ADDR = 01h. The open-drain output of the OTPN pin requires an external pull-up resistor. Leave this pin open (NC) when it is not used. R5 ETO End-of-Transmit Open-Drain Output: ETO = 1 when all the TXCH have finished the TXCH launch and are ready for the next launch. The next TRIG rise edge resets ETO = 0. The initial power-on ETO status is high. The open-drain output of the ETO pin requires a pull-up resistor to VLL. Leave this pin open (NC) when it is not used. R4 ETI End-of-Transmit Input: Pull ETI = 1 when all the TXCH on board have finished the TXCH launch and are ready for the next trigger. The ETI pin can be directly connected to the ETO pin with a pull-up resistor to VLL. Connect the ETI pin to GND when it is not used. B5 RSTN Chip Hard Reset Pin, Active-Low: When V LL and VDD are powered on, EN = 1 and RSTN = 0. All registers will be reset into the default values; all TXCH outputs will be high-Z. R6, C7, C8, D8, E8, F8, L8, M8, N8, P8, C6 DNC1-11 Do Not Connect: These pins are internally connected for I 2C manufacture use only. TABLE 3-1: PIN FUNCTION (CONTINUED) HV7358 Symbol Description

DS20005918A-page 22  2018 Microchip Technology Inc.

4.0 FUNCTIONAL DESCRIPTION

4.1 Overview

The HV7358 is a 16-channel, 3-level ±80V ultrasound transmitter with built-in T/R switches, gate driver and floating voltage supply regulators, PLL clock multiplier, active bleeder circuit and configuration transmit beam- former. The high integration and rich features of the HV7358 make this device suitable for portable ultra- sound systems. The T/R switch and RX CH damp switch are integrated into each channel, while the auto- bleeding switches for true zero voltage reduce received noise to minimum. The HV7358 also features a built-in gate driver, and floating voltage regulators to allow V PP and V NN high-voltage rails to move the voltage from ±3V to ±80V, both interdependently and freely. The input 2.5V or 3.3V logic control voltages are designed to work with FPGA or LVCMOS logic family devices. It also provides the special CW mode, designed to minimize the jitter and phase noise for CW waveforms output from the reduced current HV MOSFET pairs. You can set the CW beamforming delay per channel, with a range of 0 µs to 3 µs in 12.5 ns increments, when CLK is at 80 MHz with low phase noise. When the built-in PLL circuit is enabled (PEN = 1), the internal VCO maximum frequency is 250 MHz. It pro- vides low jitter in B mode and PW mode. The TRIG pin provides synchronization alignment for the TX CH launching time of channels and on-board chips.

4.2 Programmable PLL Clock

The HV7358 has an internal PLL circuit for clock frequency, multiplying and dividing operations. The PLL and clock management block has a very low timing jitter. The same pair of TCKP/N clock signals allows phase synchronization across multiple chips. The TCKP and TCKN pins are the system clock differential inputs. They can take a 30 MHz to 200 MHz frequency as the input reference frequency. The PFD is designed to work at the best low jitter of a selected 30 MHz to 80 MHz frequency range for the best output jitter a process can provide. The PLL loop gain and loop filter bandwidth are also designed to best preserve the input crystal-based system clock low-jitter feature, and filter out most of the power supply ripple and noise of the ultrasound system. The PLL output frequency divider is programmed through a 3-bit register which is accessible through I 2C. The VCO of the PLL circuit is designed to generate up to a 250 MHz maximum frequency, with a loop filter BW selected for best rejecting power supply ripple and noise. The user’s low-jitter LVDS clock source should be provided via chip LVDS distribution buffer(s) to the CLKP and CLKN inputs, with an external 100  termi- nation resistor nearby. The lock-in time of the PLL has a range of 500 µs to 1 ms. To allow the PLL to lock, set the PEN high first, then set the EN high. If enabling the PLL through I 2C, set the PLLEN bit first, then set the EN high.

4.3 LVDS Connections

Figure 4-1 shows a typical point-to-point LVDS connec- tion. The LVDS driver, on the left, drives the two 50 Ω transmission lines into the LVDS receiver on the right. The Q and Q outputs of the LVDS driver pass to the corresponding inputs of the LVDS receiver. The two 50Ω single-ended transmission lines can be microstrip, stripline, a 100 Ω differential twisted pair or similar balanced differential transmission line. A 100Ω resistor needs to be connected to the LVDS receiver near the input pin pair. LVDS uses a Current-mode driver, behaving like two equal and opposite current sources with a high output impedance. LVDS outputs typically drive ±3.5 mA to flow through the 100 Ω resistor, R T, generating a ±350 mV voltage swing differentially. The terms, “Common-mode voltage” and “offset voltage”, refer to the average of the CKOP/CKON pins; for example, CKOP + V CKON)/2. LVDS has a typical output Common-mode voltage of about 1.25V, determined by the LVDS driver. FIGURE 4-1: A Typical Point-to-Point LVDS Connection. The implementation of the 50 Ω lines using microstrip techniques on a PC board is recommended. Due to differences in PCB stack-ups, you must use the 50 to GND LVDS trace width and spacing according to the PCB manufacture suggestion. The 100 Ω termi- nation resistor, R T, terminates the CLKP and CLKN pins close to the device. The HV7358 LVDS receiver, as shown on the right in Figure 4-1, adheres to all the standard LVDS DC input levels specified in Table 1-12. DATA Transmit DATA Receive LVDS Line Driver Q Q 3.5 mA 3.5 mA LVDS Line Receiver RT 100350 mV

 2018 Microchip Technology Inc. DS20005918A-page 23 HV7358

4.4 LVDS SPI Operation

The HV7358 features the fast programming LVDS interface for programming the transmit patterns, the channel delay counters and the local t OFF counters. The fast programming LVDS interface, in all the following cases, can operate up to 200 MHz (see Figure 4-2). When LPWM = 1, the SPI write and TX CH launching process are switched to the local Beamform registers block, which contains per-channel delay and the local PWM Time-Off registers. The TX CH launch waveform pattern parameters, the pulse width and repeat pulses number are always taken from the Global Waveform Pattern registers, written by the fast SPI operation, when the pin, LPWM = 0. The waveform selection is done by the W0 and W1 pins directly. You can change their selection before TXRW is pulled high. During the waveform patterns, the SPI writing the W0 and W1 pins also serves as a pointer to select one of the four Waveform Pattern registers to write. When SDLY = 1 and LPWM = 1, only the per-channel delay counters are selected to program. The local PWM time-off counters are bypassed. The fast SPI writing operation will perform a short word (12-bit/word) data transfer. When SDLY = 0 and LPWM = 1, all the channel delay counters and local PWM Time-Off registers are selected to program. The fast SPI writing operation performs a long word (26-bit/word) data transfer. During either long or short data transfers, the chip will be able to perform the SP Broadcasting mode if SPIB = 1. That means the SPI inputs, clock, data and chip select will be copied and buffered out to SPI interface outputs. The HV7358 also features the built-in fast programming LVDS output buffers to allow a daisy-chain operation when multiple HV7358 devices are used in the system. The retiming of the CSOP/N and SDOP/N signals ensures sufficient setup time for the next device in the chain. The LVDS output buffers eliminate the need for external LVDS buffers/drivers for each HV7358 when multiple devices are used in the system. The pins’ lay- out is optimized for the daisy-chain operation to allow a clean PCB layout. If the built-in LVDS output buffers are not used, they can be disabled to save power by driving BEN = 0 if BSEL = 0. Alternatively, the built-in LVDS output buffers can be enabled or disabled by writing ‘1’ or ‘0’ to the BFEN bit in the I 2C register, if BSEL = 1. The fast programming interface can also operate in two modes: Broadcasting or Daisy-Chain. The Pin mode selects the operating mode. When SPIB = 1, the fast programming interface operates in SPI Broadcasting mode. When SPIB = 0, the fast programming interface operates in Daisy-Chain mode. Alternatively, the oper- ating mode can be selected via the F/D bit in the I register if the override bit, EN_OVR = 1. All LVDS interface input pin pairs must have external 100 termination resistors between the CLKP and CLKN, SDIP and SDIN, CSP and CSN pins.

 2018 Microchip Technology Inc. DS20005918A-page 29 HV7358

4.5 I 2C Interface Operation

1. The master (Processor/FPGA) initiates a Start condition. A Start condition is defined as a change in the state of the SDA line, from high-to-low, while the SCL line is high. 2. The master sends the 7-bit slave address, with the Most Significant bit (MSb) first, followed by the R/W bit. The R/W bit in this case is low. 3. The master waits for the Acknowledgment from the addressed slave device (HV7358). The Acknowledgment is defined as the addressed slave device when it pulls down the SDA line during the ninth clock of the SCL. 4. After the Acknowledgment is received, the master sends the APR byte with the Register Address Pointer. 5. The master waits for the Acknowledgment. 6. The master initiates a Repeated Start condition. 7. The master sends the 7-bit slave address, with the Most Significant bit first, followed by the R/W bit. The R/W bit in this case is high for the read operation. 8. The master waits for the Acknowledgment. 9. The addressed slave device sends the byte stored in the register that is addressed by the APR, the Address Pointer. 10. The master sends the Acknowledgment. 11. The master issues the Stop condition. 12. If repeated reads from the same register are desired, repeat Steps 6-11. FIGURE 4-13: Data Transfer on the I2C Bus. FIGURE 4-14: Acknowledgment on the I2C Bus. P STOP CONDITION ACKNOWLEDGEMENT SIGNAL FROM RECEIVER ACKNOWLEDGEMENT SIGNAL FROM RECEIVER MSB SDA SCL P START CONDITION BYTE COMPLETE, INTERRUPT WITHIN RECEIVER CLOCK LINE HELD LOW WHILE INTERRUPTS ARE SERVICED ACK ACK 12 7 89 1 2 3 - 8 9 DATA OUTPUT BY SCL FROM MASTER S START CONDITION CLOCK PULSE FOR ACKNOWLEDGEMENT 12 789 TRANSMITTER DATA OUTPUT BY RECEIVER

 2018 Microchip Technology Inc. DS20005918A-page 31 HV7358

4.6 SPI and I 2C Registers Description

TABLE 4-1: SPI BEAMFORM DATA PARAMETERS Data Description TGP(w)6:0 Global PWM Time-Off register for the positive pulses if INV =0. The time-off will be at both sides of the TGW pulse width to reduce the pulse width. The time period is tOFF_P =T G P(w)[6:0]/fC. TGN(w)6:0 Global PWM Time-Off register for the negative pulses if INV =0. The time-off will be at both sides of the TGW pulse width to reduce the pulse width. The time period is tOFF_N =T G N(w)[6:0]/fC. TGW(w)8:0 Global Pulse-Width 9-Bit register for each waveform pattern. RPC(w)7:0 Global Repeating Pulse Counter register for each waveform pattern. DLY(ch)11:0 Beamform Delay 12-Bit registers in the local fast SPI register bank. Each channel delay time will be, tDELAY_7(ch) =D L Y(ch)[11:0]/fC, before the next TXCH launch, if 000h < DLY < FFFh after the TRIG is issued. When DLY = 000h, the channel is high-Z (the channel is not used for the next launch). When DLY = FFFh, the channel is directly going to RTZ+ mode as a receive only channel. TLP (ch)6:0 Local per Channel PWM Time-Off register for the positive pulses if INV =0. The time-off will be at both sides of the TGW pulse width to reduce the pulse width per channel. The time period is t OFF_P =T L P(ch)[6:0]/fC. TLN(ch)6:0 Local per Channel PWM Time-Off register for the negative pulses if INV =0. The time-off will be at both sides of the pulse-width TPW to reduce the pulse width. The time period is tOFF_N =T L N(ch)[6:0]/fC. Note 1: “w” denotes the Waveform Pattern Number 0, 1, 2 or 3. It is pointed to by the pin, W[1:0]. 2: “ch” denotes the local channel number, from 0 to 15. The local registers are always written or read sequentially, starting from Channel #15.

DS20005918A-page 32  2018 Microchip Technology Inc. TABLE 4-2: I 2C CONTROL DATA PARAMETERS(1) Data Description BSEL SPI output buffers enabling the control bit in the I 2C register. If BSEL =0, all buffers are enabled by the BEN pin; if BSEL = 1, all buffers are enabled by the BFEN bit. BFEN The BFEN bit overrides the BEN pin function. The BEN pin has no effect on buffer enable when BSEL = 1. The buffer enable is controlled only by the BFEN bit; vice versa if BSEL = 0. PLLEN PLL function enable bit in the I 2C register when PSEL = 1. PSEL PLL enable control selecting bit in the I 2C register. If PSEL = 0, it is controlled by the PEN pin; if PSEL = 1, it is controlled by the PLLEN bit in the I2C register. SPIBC SPI Broadcasting mode enable bit in the I 2C register. If SPISEL = 1, the Broadcasting mode is controlled by this bit. SPISEL SPI Broadcasting mode control selecting bit in the I 2C register. If SPISEL =0, it is controlled by the SPIB pin; if SPISEL = 1, it is controlled by the SPIBC bit in the I2C register. N[2:0] PLL frequency multiplier, divider and prescaler for the integer numbers in the I 2C register. If PEN = LCKD = 1, the internal TXCH frequency is fC =f TCK * (N); here, fTCK =f REF of the PFD. If PEN = LCKD = 0, the internal TXCH frequency is fC =f TCK. CWFD[7:0] The CW Frequency Divisor I 2C register. CW frequency is set by: fCW = fC/2 * CWFD. When CWFD = 0, the TXCH output is in high-Z. The CWFD initial default value is ‘0’. The CWFD values will be loaded into the channel’s CWFD counter prior to a TXRW rise edge when the CW pin is high. The per channel CWFD counters start counting down after the beamform delay. CWOC I 2C control bits for the CW output RON selection. If CWOC = 0, RONCW =3 0Ω; if CWOC = 1, RONCW =4 5Ω. This bit is for all channels. BOC[1:0] I 2C control bits for the B mode output peak current. BOC =00b, BOC = 01b for ±0.9A, BOC =10b for ±600 mA and BOC = 11b for ±300 mA. These bits are for all channels. OTP Overtemperature flag bit. If OTP = 1, the chip is overtemperature; if OTP =0, the temperature is in the specified working range. The flag will be reset after the read of the ADDR = 01h register. If the overtemperature event continues, the OTPN = 0 will be retriggered at the next EN rise edge. You must perform a read operation to clear the register after the initial power-on, OTPN = 1 and EN = 1. V(x)UV Undervoltage flag bit. When the one voltage rail is undervoltage, V(x)UV = 1, the flag bit(s) will be cleared by the I 2C reading of the ADDR = 01h register. If any undervoltage continues, the OTPN = 0 will be retrigged at the next EN rise edge. You must perform a read operation to clear the register after the initial power-on, OTPN = 1 and EN = 1. TRDLY[4:0] TRSW On-Time Delay Selection Control register. TRDLY = (8 to 288)/f C. RESET If RESET = 1, reset all SPI and I2C registers. The RESET will be zero after the Reset is done. This bit functions the same as the RSTN hardware Reset pin. EOTC If EOTC = 0, the RTZ+ and TRSW delay period starts immediately after all channels are finished. If EOTC = 1, the period starts at the first fC clock rise edge after ETI becomes high and after all channels finish the TXCH period. EOT Read-only bit for the End-of-TX CH flag for all 16 channels in the chip. If EOT = 0, the TXCH period is not finished. When EOT = 1, all 16 channels in this IC TXCH period are finished. LOCKD Read-only bit for the PLL locked flag. If LOCKD = 0, the PLL is not locked; if LOCKD = 1, the PLL is locked. URSV[1:0] Reserved for D% control bits. Note 1: For all register bits, the Power-on Reset is Default Zero.

 2018 Microchip Technology Inc. DS20005918A-page 33 HV7358 TABLE 4-4: TRSW ON-TIME DELAY TRDLY[4:0], R/W VIA I2C TABLE 4-3: B MODE GLOBAL TX CH PULSE-WIDTH TGW(w)[8:0], R/W VIA I2C/SPI W[1:0] Pins SPI Data Write TGW(w)[8:0] I2C Read-Back Address of TGW(w)8:0 D8 D7 D6 D5 D4 D3 D2 D1 D0

00 TXCH Pulse-Width GPW0[8:0] for Wave #0 TX CH Pulse Width (Half Cycle Time) for

Waveform #0(1)

01 TXCH Pulse-Width GPW1[8:0] for Wave #1 TX CH Pulse Width (Half Cycle Time) for

Waveform #1(1)

10 TXCH Pulse-Width GPW2[8:0] for Wave #2 TX CH Pulse Width (Half Cycle Time) for

Waveform #2(1)

11 TXCH Pulse-Width GPW3[8:0] for Wave #3 TX CH Pulse Width (Half Cycle Time) for

Waveform #3(1) Note 1: The half-cycle period TXCH pulse width, tPulse_Width = TGW(w)[8:0]/fC, where 2 ≤ TGW(w) ≤ 511. When TGW(w) = 0 or 1, the channel TXCH output will be RTZ, where the “w” denotes the Global Waveform Patterns #0~3. 2: The 9-bit data read-back from two I2C addresses. TRDLY4:0 k Value (Dec) TRSW Switch-On Delay After ETI = 1: tTRSW_ON =k / fC (in ns) D4 D3 D2 D1 D0 f C =8 0M H z f C =1 2 0M H z f C =1 6 0M H z f C =2 0 0M H z 0000 0 1 12.5 8.4 6.3 5.0 0000 1 8 100 67 50 40 0001 0 12 150 100 75 60 0001 1 16 200 133 100 80 0010 0 20 250 166 125 100 0010 1 24 300 200 150 120 0011 0 36 450 300 225 180 0011 1 40 500 333 250 200 0100 0 48 600 400 300 240 0100 1 60 750 500 375 300 0101 0 64 800 533 400 320 0101 1 72 900 600 450 360 0110 0 80 1000 667 500 400 0110 1 96 1200 800 600 480 0111 0 100 1250 833 625 500 0111 1 120 1500 1000 750 600 1000 0 128 1600 1067 800 640 1000 1 144 1800 1200 900 720 1001 0 160 2000 1333 1000 800 1001 1 192 2400 1600 1200 960 1010 0 200 2500 1667 1250 1000 1010 1 240 3000 2000 1500 1200 1011 0 288 3600 2400 1800 1440 Note 1: When TRDLY[4:0] > 10110b, the TRSW switch-on delay is the same as k = 288.

DS20005918A-page 34  2018 Microchip Technology Inc. TABLE 4-5: B MODE GLOBAL TX CH PWM TIME-OFF, R/W VIA I2C/SPI W[1:0] Pin TGP(w)[6:0](3,4)

Description

D6 D5...D1 D0 TxCH P-FETs Time-Off at INV = 0 or N-FETs Time-Off at INV = 1(2)

00 TGP0[6:0] Global TX CH PWM Time-Off for P Side of Waveform #0

01 TGP1[6:0] Global TX CH PWM Time-Off for P Side of Waveform #1

10 TGP2[6:0] Global TX CH PWM Time-Off for P Side of Waveform #2

11 TGP3[6:0] Global TX CH PWM Time-Off for P Side of Waveform #3

W[1:0] pin TGN(w)[6:0](3,4) D6 D5...D1 D0 TxCH N-FETs Time-Off at INV = 0 or P-FETs Time-Off at INV = 0(1)

00 TGN0[6:0] Global TX CH PWM Time-Off for N Side of Waveform #0

01 TGN1[6:0] Global TX CH PWM Time-Off for N Side of Waveform #1

10 TGN2[6:0] Global TX CH PWM Time-Off for N Side of Waveform #2

11 TGN3[6:0] Global TX CH PWM Time-Off for N Side of Waveform #3

Note 1: PWM time-off, tOFF_P = TGP(w)[6:0]/fC. 2: PWM time-off, tOFF_N = TGN(w)[6:0]/fC. 3: TGP(w) + TGN(w) ≠ 1; otherwise, the channel TXCH output will be RTZ. 4: If TGP(w) + TGN(w) ≥ 2, then TGW – 2 * TGN(w) ≥ 2 and TGW – 2 * TGP(w) ≥ 2. If TGP(w) = TGN9(w) = 0, then TGW ≥ 2; otherwise, the TXCH output will be RTZ.

 2018 Microchip Technology Inc. DS20005918A-page 35 HV7358 TABLE 4-6: TX CH PULSER AND RXCH SWITCH OUTPUT STATUS AT POWERED ON Control Pins Logic to Gate Drive CW Mode TX0~15 Outputs and RX CH Switches Status EN TXRW CW INV POS NEG CW Logic ETO/ ETI(5) TX0~15 Output RTZSW/ TRSW RXDMP Notes 110 000 Disable 0 RTZ Off On TX CH B mode noninverting(1) 110 010 Disable 0 VPP Off On 110 001 Disable 0 VNN Off On 110 011 Disable 1 RTZ+(3) On Off RX CH mode 110 100 Disable 0 RTZ Off On TX CH B mode inverting(1) 110 101 Disable 0 VNN (6) Off On 110 110 Disable 0 VPP(6) Off On 110 111 Disable 1 RTZ+(3) On Off RX CH mode(3) 111 000 Enable 0 high-Z(4) Off On CW mode noninverting(2) 111 010 Enable 0 VCW+ Off On 111 001 Enable 0 VCW- Off On 111 011 Enable 0 RTZ+(3) ON Off 111 100 Enable 0 high-Z(4) Off On CW mode inverting(2) 111 101 Enable 0 VCW- Off On 111 110 Enable 0 VCW+ Off On 111 111 Enable 0 RTZ+(3) ON Off 10x x00 Disable 0 high-Z(4) Off On SPI/I 2C RW 0xx xxx Disable 0 high-Z(4) Off ON IC disabled Note 1: In B mode, you must use a low duty cycle (D%  10%) due to the IC power dissipation limit. 2: In CW mode (D% = 100%), the VPP/VNN output voltage must be reduced due to the IC power dissipation limit. 3: When the TXCH output is in RTZ+ state, the channel is in Receiving mode (RTZ+). 4: When the TXCH output is in high-Z state, all output MOFETs are off. 5: When ETI = 1 (TRSW), all channels are in Receiving mode after the delay. 6: When INV = 1, Tx0~15 are inverting the output waveforms. TABLE 4-7: CHIP ENABLE, SLEEP AND OTP STATUS EN OTP, VLLUV, VDDUV SLEEP PEN BEN I 2C SPI PLL V PLL VNEG, VPF, VNF, LRs SDO, CSO, CKO TXCH Output 10 0 x 1 On On X On On Enable Normal (VPP, VNN, RTZ, high-Z, RTZ+ or CW) 10 0 1 1 On On On On On Enable 10 0 0 1 On On Off On On Enable 10 0 x 0 On On X On On Disable 10 1 x x On Off Off Off On X high-Z 11 x x x On Off Off Off Off Disable high-Z 0x x x x On Off Off Off Off Disable high-Z

DS20005918A-page 36  2018 Microchip Technology Inc. TABLE 4-8: I 2C CONTROL PARAMETERS ADDRESS I2C ADDR (Hex) I2C Control Register Data for Write or Read D7 D6 D5 D4 D3 D2 D1 D0 0 0 h 000000 E O T L O C K D 01h 0 VNFUV VPFUV VPLLUV VNEGUV VDDUV VLLUV OTP 02h — EOTC BSEL BFEN SPISEL SPIBC PSEL PLLEN 03h URSV1 URSV0 BOC[1:0] CWOC N[2:0] 04h CWFD[7:0] 05h — — — TRDLY[4:0] 10h TGW0[7:0] Read-Back for Waveform Pattern #0 11h TGW1[7:0] Read-Back for Waveform Pattern #1 12h TGW2[7:0] Read-Back for Waveform Pattern #2 13h TGW3[7:0] Read-Back for Waveform Pattern #3 14h TGW0[8] TGP0[6:0] Read-Back for Waveform Pattern #0 15h TGW1[8] TGP1[6:0] Read-Back for Waveform Pattern #1 16h TGW2[8] TGP2[6:0] Read-Back for Waveform Pattern #2 17h TGW3[8] TGP3[6:0] Read-Back for Waveform Pattern #3 18h 0 TGN0[6:0] Read-Back for Waveform Pattern #0 19h 0 TGN1[6:0] Read-Back for Waveform Pattern #1 1Ah 0 TGN2[6:0] Read-Back for Waveform Pattern #2 1Bh 0 TGN3[6:0] Read-Back for Waveform Pattern #3 1Ch RPC0[7:0] Read-Back for Waveform Pattern #0 1Dh RPC1[7:0] Read-Back for Waveform Pattern #1 1Eh RPC2[7:0] Read-Back for Waveform Pattern #2 1Fh RPC3[7:0] Read-Back for Waveform Pattern #3 20h 0 0 0 0 DLY0[11:8] Read-Back for Ch #0 High Nibble 21h DLY0[7:0] Read-Back for Ch #0 Lo Byte 22h 0 0 0 0 DLY1[11:8] Read-Back for Ch #1 High Nibble 23h DLY1[7:0] Read-Back for Ch #1 Low Byte 3Eh 0 0 0 0 DLY15[11:8] Read-Back Ch #15 High Nibble 3Fh DLY15[7:0] Read-Back Ch #15 Low Byte 40h 0 TLP0[6:0] for Ch #0 41h 0 TLP1[6:0] for Ch #1 4Fh 0 TLP15[6:0] for Ch #15 50h 0 TLN0[6:0] for Ch #0 51h 0 TLN1[6:0] for Ch #1 5Fh 0 TLN15[6:0] for Ch #15

 2018 Microchip Technology Inc. DS20005918A-page 37 HV7358 TABLE 4-9: BEAMFORM PER CHANNEL DELAY TIME, R/W VIA I2C/SPI DLY(ch)11:0 Delay Time per Channel B Mode and CW Mode D11 D10...D1 D0 0000, 0000, 0000 The channel(ch) is in high-Z Channel off TX CH high-Z 0000, 0000, 0001 tDLY(ch) =1 / fC The per channel (ch) B-pulses/CW waveform (w) 1111, 1111, 1110 tDLY(ch) = 4094/fC 1111, 1111, 1111 The channel is in RXCH only No TRIG TRSW and RTZSW on in RX CH mode only Note 1: The 12-bit data of DLY (ch) read back from two I2C ADDRs. TABLE 4-10: TX CH OUTPUT PEAK CURRENT SELECTION R/W VIA I2C BOC[1:0] TXCH Output Peak Current Description D1 D0 00 ±1.6A 1.6A and 1.0A are for B mode only. For CW mode, you must select the 0.5A or 0.3A dependent CW lasting time due to the package power dissipation limit. 01 ±1.0A 10 ±0.5A 11 ±0.3A TABLE 4-11: SPI DATA SELECT PIN LPWM FUNCTION LPWM(1) SPI Write to the Registers of TXRW = 0(2) TXCH B Mode Use (TXRW = 1)

0 Global TGPw[6:0], TGNw[6:0],TGWw[8:0] and RPCw[7:0] (31-bit/word) Global registers parameters

1 Local DLYch[11:0], TLPch[6:0] and TLNch[6:0] (26-bit/word) when

SDLY = 0; or DLYch[11:0] (12-bit/word) only when SDLY = 1 Local registers parameters Note 1: Write one word per CS operation. When LPWM = 1, the Writing Channel Pointer starts at ch = 15, advanced automatically per CS rise. The pointer will be reset at the falling edge of TXRW. 2: All register data writing must be MSB first. TABLE 4-12: SPI WORD LENGTH CONTROL PIN SDLY FUNCTION SDLY(1) SPI Write to the Registers of TXRW = 0(2) Word Length

0 All-Fast-Reg: DLYch[11:0], TLPch[6:0] and TLNch[6:0] (26-bit/word) 26-bit (long word)

1 Select the Beamform Delay registers only: DLYch[11:0] (12-bit/word) 12-bit (short word)

Note 1: Write one word per CS operation. When LPWM = 1, the Writing Channel Pointer starts at ch = 15, advanced automatically per CS rise. The pointer will be reset at the falling edge of TXRW. 2: All register data writing must be MSB first.

DS20005918A-page 38  2018 Microchip Technology Inc. TABLE 4-13: B MODE PWM TIME-OFF PER CHANNEL R/W VIA I2C TLP(ch)[6:0](3,4) PWM Time-Off for P (per channel) Description D6 D5...D1 D0 TXCH P-FETs Time-Off at INV = 0 or N-FETs Time-Off at INV = 1(1) 0000000 tOFF_P =0 / fC The per channel (ch) B-pulses PWM off-time on both sides of the P-pulse if INV = 00000001 tOFF_P =1 / fC 1111110 tOFF_P =1 2 6 / fC 1111111 tOFF_P =1 2 7 / fC TLN(ch)[6:0](3,4) PWM Time-Off for N (per channel) Description D6 D5...D1 D0 TXCH N-FETs Time-Off at INV = 0 or P-FETs Time-Off at INV = 1(2) 0000000 tOFF_N =0 / fC The per channel (ch) B-pulses PWM off-time on both sides of the N-pulse if INV = 00000001 tOFF_N =1 / fC 1111110 tOFF_N = 126/fC 1111111 tOFF_N = 127/fC Note 1: The same time-off on both sides of the P-pulse. 2: The same time-off on both sides of the N-pulse. 3: TLP(w) + TLN(w) ≠ 1; otherwise, the TXCH output will be RTZ. 4: If TLP(w) + TLN(w) ≥ 2, then TGW – 2 * TLN(w) ≥ 2 and TGW – 2 * TLP(w) ≥ 2. If TLP(w) = TLN9(w) = 0, then TGW ≥ 2; otherwise, the TXCH output will be RTZ. TABLE 4-14: CW FREQUENCY DIVIDER NUMBER R/W VIA I2C(1) CWFD[7:0] CW Transmit Clock Frequency fCW Description D7 D6 ... D1 D0 0000, 0000b All TX0 to 15 in high-Z (default) The per channel (ch) CW frequency divide down counter if CW = 10000, 0001b fCW =f TCK/2 x 1 0000, 0010b fCW =f TCK/2 x 2 0000, 0011b fCW =f TCK/2 x 3 0000, 0100b fCW =f TCK/2 x 4 …… …… 1111, 1111b fCW =f TCK/2 x 255 Note 1: fCW =f TCK/2 x CWFD[7:0], where 1 ≤ CWFD ≤ 255.

 2018 Microchip Technology Inc. DS20005918A-page 39 HV7358 TABLE 4-15: PLL LOOP FREQUENCY DIVIDER NUMBER, R/W VIA I2C N[2:0] PLL Output Frequency fC (1) Description D2 D1 D0 000 fC =1xf TCK (default) N is an integer number from 1 to 8 001 fC =1xf TCK 010 fC =2xf TCK 011 fC =3xf TCK 100 fC =4xf TCK 101 fC =5xf TCK 110 fC =6xf TCK 111 fC =8xf TCK Note 1: fVCO =f C. TABLE 4-16: I 2C DEVICE ADDRESS I2C Address Pin Device Address Device on the Bus A2 A1 A0 0 0 0 0000 , 0000b Broadcast Address 0 0 0 1101 , 0000b U0 0 0 1 1101 , 0001b U1 0 1 0 1101 , 0010b U2 0 1 1 1101 , 0011b U3 1 0 0 1101 , 0100b U4 1 0 1 1101 , 0101b U5 1 1 0 1101 , 0110b U6 1 1 1 1101 , 0111b U7

DS20005918A-page 40  2018 Microchip Technology Inc.

5.0 PACKAGING INFORMATION

5.1 Package Marking Information

Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 168-Lead TFBGA 13 mm x 13 mm Example HV7358 1851256

 2018 Microchip Technology Inc. DS20005918A-page 41 HV7358 B A 0.15 C 0.15 C

0.15 C A B

0.08 C C SEATING PLANE TOP VIEW SIDE VIEW BOTTOM VIEW NOTE 1 0.10 C 0.08 C Microchip Technology Drawing C04-1191B Sheet 1 of 2 168X For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: D E A B C D E F G H J K L M N P R T 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 A B C D E F G H J K L M N P R T e e D D e e 168X Øb A 168-Ball Thin Fine-Pitch Ball Grid Array (AFA) - 13x13x1.2 mm Body [TFBGA]

DS20005918A-page 42  2018 Microchip Technology Inc. Microchip Technology Drawing C04-1191B Sheet 1 of 2 Number of Terminals Overall Height Ball Diameter Overall Width Mold Cap Height Pitch Standoff Units Dimension Limits A b e E N

0.80 BSC

0.53 REF

0.35 0.23 0.40 0.33

13.00 BSC

0.45 1.20 MAX REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Dimensioning and tolerancing per ASME Y14.5M For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Overall Length D 13.00 BSC 168-Ball Thin Fine-Pitch Ball Grid Array (AFA) - 13x13x1.2 mm Body [TFBGA] Microchip Technology Drawing C04-1191B Sheet 2 of 2

 2018 Microchip Technology Inc. DS20005918A-page 43 HV7358 RECOMMENDED LAND PATTERN Dimension Limits Units C2Overall Contact Pad Spacing Contact Pitch MILLIMETERS E MAX

12.00 BSC

Pad Diameter (X168) ØX 0.35 Microchip Technology Drawing C04-3191B NOM C1Overall Contact Pad Spacing 12.00 BSC BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: E E ØX SILK SCREEN T R P N M L K J H G F E D C B A 1 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 168-Ball Thin Fine-Pitch Ball Grid Array (AFA) - 13x13x1.2 mm Body [TFBGA]

DS20005918A-page 44  2018 Microchip Technology Inc. NOTES:

 2018 Microchip Technology Inc. DS20005918A-page 45 HV7358 APPENDIX A: REVISION HISTORY Revision A (June 2018)

• Original Release of this Document.

DS20005918A-page 46  2018 Microchip Technology Inc. NOTES:

 2018 Microchip Technology Inc. DS20005918A-page 47 HV7358 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Device: HV7358: 16-Channel, 3-Level HV Ultrasound Transmitter with Built-in Transmit Beamformer Temperature Range: V= 0 C to +85C Package: AFA = 168-Lead TFBGA 13 mm x 13 mm Examples: a) HV7358-V/AFA: HV7358, Industrial Temperature, 168-Lead TFBGA Package. PART NO. X /XX PackageTemperature Range Device

DS20005918A-page 48  2018 Microchip Technology Inc. NOTES:

 2018 Microchip Technology Inc. DS20005918A-page 49 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2018, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-3281-4 Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are co mmitted to continuously improvin g the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT S YSTEM CERTIFIED BY DNV == ISO/TS 16949 ==

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