HV7350K6-G-M937

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Document overview

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• PDF pages: 16

Technical content

Features

• H V C M O S® Technology for High Performance
• High-density Integrated Ultrasound Transmitter
• 0V to ±60V Output Voltage
• ±1A Source and Sink Current in Pulse Mode
• ±1A Source and Sink Current in Return-to-Zero TZ) Mode
• Up to 20 MHz Operating Frequency
• Matched Delay Times
• Optional Clock Realignment
• 3.3V CMOS Logic Interface and Reference
• +3.3V Low-voltage Supply for V DD
• Built-in Linear Regulators for Floating Gate Drivers
• Built-in Output Drain Diodes and Bleed Resistors

Applications

• Portable Medical Ultrasound Imaging
• Piezoelectric Transducer Drivers
• Pulse Waveform Generator General Description The HV7350 is an 8-channel monolithic high-voltage hi gh-speed pulse generator with built-in fast return to zero-damping FETs. This high-voltage and high-speed integrated circuit is designed for portable medical ultrasound imaging system. The HV7350 consists of a controller logic interface circuit, le vel translators, MOSFET gate drives, and high-current power P-channel and N-channel MOSFETs as the output stage for each channel. The output peak currents of each channel are gu aranteed to be over ±1A with up to ±60V pulse swings as well as Return-to-Zero mode. The gate drivers for the output MOSFETs are powered by built-in linear 5V regulators referenced to V PP and V NN. This direct coupling topology of the gate drivers not only saves four floating voltage supplies or AC coupling capacitors per channel but also makes the PCB layout smaller and easier. An input clock pin is available to realign all the logic in put control lines to a master clock. Precise logic timing is always essential in any ultrasound systems. Package Type 56-lead (8 X 8) QFN (Top view) See Table 2-1 for pin information. 8-Channel High-Speed ±60V ±1A Ultrasound RTZ Pulser

DS20005627A-page 2  2016 Microchip Technology Inc. Typical Application Circuit CPFVDD +3.3V 3.3V Logic RGND HVOUT1 VPP +10 to +60V -10 to -60V P-Driver N-Driver 1 of 8 Channels Logic Level Translator -5.0V RGND RGND DMP 1.0µF VPF VNF Rb LRP CPOS GND GNDSUB REN OEN PIN1 NIN1 PIN8 NIN8 CLK DAP LRP GND LRN GND VNF VPF LRN GND GND CNEG CNF VNN +5.0V -5.0V 1.0µF1.0µF 1.0µF 1.0µF TX1 1.0µF 1.0µF VLL +3.3V 0.1µF +5.0V

 2016 Microchip Technology Inc. DS20005627A-page 3 HV7350

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings † † Notic e: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. Note 1: Device s are ESD sensitive. Handling precautions are recommended. OPERATING SUPPLY VOLTAGES AND CURRENT  (EIGHT ACTIVE CHANNELS) Electrical Specifications: VLL = +3.3V, VDD = +3.3V, VPP = +60V, VNN = –60V, VCLK = +3.3V, TA = 25°C unless otherwise indicated. Parameter Sym. Min. Typ. Max. Unit Conditions VDD Voltage Supply VDD 2.97 3.3 5.2 V VDD UVLO UVLODD 2.3 2.6 2.8 V Logic Voltage Reference VLL 2.5 3.3 5 V VLL UVLO UVLOLL 1.3 1.55 1.7 V Positive High-voltage Supply VPP +10 — +60 V Negative High-voltage Supply VNN –60 — –10 V VLL Current ILLQ — 8 — μA OEN = REN = 0VDD Current IDDQ — 1 — VPP Current IPPQ — 5 10 VNN Current INNQ — 5 10 VLL Current ILLEN — 13 20 μA OEN = REN = 1  5 ms after f = 0 MHz VDD Current IDDEN — 480 700 VPP Current IPPEN — 220 350 VNN Current INNEN — 300 400 VDD Current IDDCW — 2.3 — mA f = 5 MHz, continuous, no loads, for calcula tion reference onlyVPP Current IPPCW — 80 — VNN Current INNCW — 80 — VLL Current ILL,CLK — 33 — μA fCLK = 10 MHz, PIN = NIN = 0

DC ELECTRICAL CHARACTERISTICS Electrical Specifications: VLL = +3.3V, VDD = +3.3V, VPP = +60V,VNN = –60V, VCLK = +3.3V, TA = 25°C unless otherwise indicated. Parameter Sym. Min. Typ. Max. Unit Conditions PULSER P-CHANNEL MOSFET Output Saturation Current IOUT 1 1.5 — A Channel Resistance RON — 13.2 — Ω ISD = 100 mA PULSER P-CHANNEL MOSFET Output Saturation Current IOUT 1 1.5 — A Channel Resistance RON — 8 — Ω ISD = 100 mA DAMPING P-CHANNEL MOSFET Output Saturation Current I OUT 1 1.5 — A Channel Resistance RON — 13 — Ω ISD = 100 mA DAMPING N-CHANNEL MOSFET Output Saturation Current I OUT 1 1.5 — A Channel Resistance RON — 9 — Ω ISD = 100 mA LOGIC INPUT Input Logic High Voltage VIH 0.7 • VLL — VLL V VLL = 2.5V to 3.3V 0.8 • VLL — VLL = 5V Input Logic Low Voltage VIL 0 — 0.3 • VLL V VLL = 2.5V to 3.3V — 0.2 • VLL VLL = 5V Input Logic High Current IIH — — 10 μA Input Logic Low Current IIL –10 — — μA Input Logic Capacitance CIN — — 5 pF MOSFET DRAIN BLEED RESISTOR Output Bleed Resistance RB1~8 12 17 25 kΩ Bleed Resistors Power Limit PRB1~8 — — 50 mW HV7350 DS20005627A-page 4  2016 Microchip Technology Inc. AC ELECTRICAL CHARACTERISTICS Electrical Specifications: VLL = +3.3V, VDD = +3.3V, VPP = +60V, VNN = –60V, VCLK = +3.3V, TA = 25°C unless otherwise indicated. Parameter Sym. Min. Typ. Max. Unit Conditions Output Rise Time tr — 30 — ns 330 pF//2.5 kΩ lo ad 10%–90%Output Fall Time tf — 30 — ns Enable Time tEN — 300 500 μs Cap value (See Typical Application Circuit.), OEN = RENDisable Time tDIS — 2.8 10 μs Delay Time on PINX Rise td1 — 12 — ns 1 Ω re sistor load, D% < 1%  (See Timing Waveforms.) 50% inputs to 50% TX current Delay Time on NINX Rise td2 — 12 — Delay Time on Damping Rise td3 — 12 — Delay Time on Damping Fall td4 — 12 — Delay Time on CLK Rise tdc — 9 — Delay Time Matching ∆tDELAY — ±3 — ns P to N, channel to channel Delay Jitter on Rise or Fall tJ — 30 — ps VPP/VNN = +/–25V, input tr 50% to HVOUT tr or tf 50%, with 330 pF//2.5 kΩ load RTZ FETs Drain Diode trr trr — 25 — ns IF = 1A, IR = 1A, RL = 10Ω

 2016 Microchip Technology Inc. DS20005627A-page 5 HV7350 Retiming Clock Frequency fCLK 10 220 — MHz Retiming Clock Rise and Fall Ti mes trc, tfc — 0.5 5 ns Set-up Time, PIN/NIN to CLK tSU 2 — — ns Hold time, CLK to PIN/NIN tH 1 — — ns Clock Time Low tCLK_LO 2 — 100 ns CLK input must have at least one pulse be fore PIN and NIN inputs are not zero. Be sure to return inputs to zero before stopping clock. Clock Time High t CLK_HI 2 — 100 ns Clock Recognition Time tCLK_REC — 2 — ns Clock Release Time tCLK_RLS 150 300 800 ns Output Frequency Range fOUT — — 20 MHz 100Ω r esistor loadSecond Harmonic Distortion HD2 — –40 — dB Output Capacitance COSS — 50 — pF VDS = 25V, f = 1 MHz of TX pin total TEMPERATURE SPECIFICATIONS Parameter Sym. Min. Typ. Max. Unit Conditions TEMPERATURE RANGE Operating Junction Temperature TJ –40 — +125 °C Storage Temperature TS –65 — +150 °C PACKAGE THERMAL RESISTANCE 56-lead (8 X 8) QFN  JA — 21 — °C/W LOGIC CONTROL TABLE MODE LOGIC INPUTS TXN, OUTPUT OEN CLK PINX NINX VPP VNN RGND Asynchronous Mode Output Change on PIN/NIN

1 VLL 0 0 OFF OFF ON

1 VLL 1 0 ON OFF OFF

1 VLL 0 1 OFF ON OFF

1 VLL 1 1 OFF OFF OFF

ing Clock (CLK) Rising Edge , registered by PIN/NIN 1 0 0 OFF OFF ON 1 1 0 ON OFF OFF 1 0 1 OFF ON OFF 1 1 1 OFF OFF OFF Disabled 0 X X X OFF OFF OFF AC ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: VLL = +3.3V, VDD = +3.3V, VPP = +60V, VNN = –60V, VCLK = +3.3V, TA = 25°C unless otherwise indicated. Parameter Sym. Min. Typ. Max. Unit Conditions

DS20005627A-page 6  2016 Microchip Technology Inc. Timing Waveforms CLK PINn (NINn = 0) NINn (PINn = 0) NINn (PINn = 0) CLK CLK CLK ITXn ITXn 0ITXn 0 50% 50% 50% 50% td1 td4 td2 td3IOUT IOUT IOUT IOUT tdc tdc tdc tdc 50% 50% 0 0ITXn Synchronous Mode Asynchronous Mode PINn (NINn = 0)

 2016 Microchip Technology Inc. DS20005627A-page 7 HV7350

2.0 PAD DESCRIPTION

Table 2-1 details the description of pads in HV7350. Refer to Package Type for the location of pins. TABLE 2-1: PAD FUNCTION TABLE Pin Number Pin Name Description

1 PIN2 Input logic control of high-voltage output P-FET for Channel 2; High = on; Low = off

(See Logic Control Table.)

2 NIN2 Input logic control of high-voltage output N-FET for Channel 2; High = on; Low = off

(See Logic Control Table.)

3 PIN3 Input logic control of high-voltage output P-FET for Channel 3; High = on; Low = off

(See Logic Control Table.)

4 NIN3 Input logic control of high-voltage output N-FET for Channel 3; High = on; Low = off

(See Logic Control Table.)

5 PIN4 Input logic control of high-voltage output P-FET for Channel 4; High = on; Low = off

(See Logic Control Table.)

6 NIN4 Input logic control of high-voltage output N-FET for Channel 4; High = on; Low = off

(See Logic Control Table.) 7 OEN Output enable; High = on; Low = off (See Logic Control Table.)

8 REN

Built-in positive and negative 5V voltage regulators enable; High = on; Low = off If REN = 0, four isolated 5V power supplies may provide, as external supplies, for the VPP to CPF, CNF to VNN, CPOS to GND and GND to CNEG pins. Note that between VPP to CPF and CNF to VNN, two must be floating supplies. (See Logic Control Table.)

9 PIN5 Input logic control of high-voltage output P-FET for Channel 5; High = on; Low = off

(See Logic Control Table.)

10 NIN5 Input logic control of high-voltage output N-FET for Channel 5; High = on; Low = off

(See Logic Control Table.)

11 PIN6 Input logic control of high-voltage output P-FET for Channel 6; High = on; Low = off

(See Logic Control Table.)

12 NIN6 Input logic control of high-voltage output N-FET for Channel 6; High = on; Low = off

(See Logic Control Table.)

13 PIN7 Input logic control of high-voltage output P-FET for Channel 7; High = on; Low = off

(See Logic Control Table.)

14 NIN7 Input logic control of high-voltage output N-FET for Channel 7; High = on; Low = off

(See Logic Control Table.)

15 PIN8 Input logic control of high-voltage output P-FET for Channel 8; High = on; Low = off

(See Logic Control Table.)

16 NIN8 Input logic control of high-voltage output N-FET for Channel 8; High = on; Low = off

(See Logic Control Table.) 17 VLL Logic supply voltage and reference input (+3.3V)

18 GND Logic and circuit return ground (0V)

19 VDD Positive voltage power supply (+3.3V)

20 VPP

Positive high-voltage power supply (+10V to +60V)21 VPP

22 VPP

23 CPF Built-in linear voltage VPF regulator output decoupling capacitor pin, 1 uF from VPP to CPF for every CPF pin 24 CNF Built-in linear voltage VNF regulator output decoupling capacitor pin, 1 uF from CNF to VNN for every CNF pin

25 VNN

Negative high-voltage power supply (–10V to –60V)26 VNN

27 VNN

28 TX8 TX pulser Channel 8 output

29 RGND Damping ground and bleed resistors common return ground

DS20005627A-page 8  2016 Microchip Technology Inc.

30 TX7 TX pulser Channel 7 output

31 RGND Damping ground and bleed resistors common return ground

32 TX6 TX pulser Channel 6 output

33 RGND Damping ground and bleed resistors common return ground

34 TX5 TX pulser Channel 5 output

35 CNEG Built-in linear voltage –5V regulator output decoupling capacitor pin, 1 uF from CNEG to GND

36 CPOS Built-in linear voltage +5V regulator output decoupling capacitor pin, 1 uF from CPOS to GND

37 TX4 TX pulser Channel 4 output

38 RGND Damping ground and bleed resistors common return ground

39 TX3 TX pulser Channel 3 output

40 RGND Damping ground and bleed resistors common return ground

41 TX2 TX pulser Channel 2 output

42 RGND Damping ground and bleed resistors common return ground

43 TX1 TX pulser Channel 1 output

44 VNN

Negative high-voltage power supply (–10V to –60V)45 VNN

46 VNN

47 CNF Built-in linear voltage VNF regulator output decoupling capacitor pin, 1 uF from CNF to VNN for every CNF pin 48 CPF Built-in linear voltage VPF regulator output decoupling capacitor pin, 1 uF from VPP to CPF for every CPF pin

49 VPP

Positive high-voltage power supply (+10V to +60V)50 VPP

51 VPP

52 VDD Positive voltage power supply (+3.3V)

53 GND Logic and circuit return ground (0V)

54 CLK Retiming register clock input. Connect to VLL to disable the retiming function.

55 PIN1 Input logic control of high-voltage output P-FET for Channel 1; High = on; Low = off

(See Logic Control Table.)

56 NIN1 Input logic control of high-voltage output N-FET for Channel 1; High = on; Low = off

(See Logic Control Table.) VSUB (Thermal Pad) Substrate bottom is internally connected to the central thermal pad on the bottom of package. It must be con- nected to GND (0V) externally. TABLE 2-1: PAD FUNCTION TABLE (CONTINUED) Pin Number Pin Name Description

 2016 Microchip Technology Inc. DS20005627A-page 9 HV7350

3.0 FUNCTIONAL DESCRIPTION

Follow the steps below to power up and power down the HV7350: POWER-UP AND POWER-DOWN SEQUENCE (Note 1) Power-Up Power-Down Step Description Step Description

1 VLL with logic signal low 1 All logic signals go to low

2 VDD 2 VPP and VNN

3 REN = 1 (external supplies on) 3 REN = 0 (external supplies off)

4 VPP and VNN 4 VDD

5 Logic control signals active 5 VLL

Note 1: Powering up or down in any arbitrary sequence will not damage the device. The power-up sequence and power-down sequence are only recommended to minimize possible inrush current. OUTPUT CURRENT AND RON (Note 1, Note 4) ISC

2 RonP RonN IDMP

3 RonDP RonDN

1.5A 13Ω 6.5Ω 1.5A 13Ω 8Ω Note 1: VPP/VNN = +/-60V; VDD = +3.3V; REN = 1 2: ISC is current into 1Ω to GND. 3: IDMP is current from +/–30V connected to TX pin. 4: Maximum pulse width for current measurement on TX pin is 20 ns.

DS20005627A-page 10  2016 Microchip Technology Inc.

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

Legend: XX...X Product Code or Customer-specific information  Y Year code (last digit of calendar year)  YY Year code (last 2 digits of calendar year)  WW Week code (week of January 1 is week ‘01’)  NNN Alphanumeric traceability code  Pb-free JEDEC ® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part numbe r cannot be marked on one line, it will be carried over to the next line, t hus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo. 56-lead QFN Example YYWWNNNYYWWNNN e3XXXXXXXXXXXX HV7350K6HV7350K6e3 16219871621987

 2016 Microchip Technology Inc. DS20005627A-page 11 HV7350 56-Lead QFN Package Outline (K6) 8.00x8.00mm body, 1.00mm height (max), 0.50mm pitch Symbol A A1 A3 b D D2 E E2 e L L1 ș Dimension (mm) MIN 0.80 0.00 0.20 REF 0.50 BSC 0.30 0.00 0 O JEDEC Registration MO-220, Variation VLLD-2, Issue K, June 2006. 7KLVGLPHQVLRQLVQRWVSHFL¿HGLQWKH-('(&GUDZLQJ ‚7KLVGLPHQVLRQGLIIHUVIURPWKH-('(&GUDZLQJ Drawings are not to scale. S# S 6Q 68 8 0 0 031010 Notes: 1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEH DPROGHGPDUNLGHQWL¿HU DQHPEHGGHGPHWDOPDUNHU RU a printed indicator. 2. 'HSHQGLQJRQWKHPHWKRGRIPDQXIDFWXULQJDPD[LPXPRIPPSXOOEDFN PD\\EHSUHVHQW 3. 7KHLQQHUWLSRIWKHOHDGPD\\EHHLWKHUURXQGHGRUVTXDUH Seating Plane Top View Side View Bottom View A D E b L View B View B Note 3 Note 2 Note 1 (Index Area D/2 x E/2) Note 1 (Index Area D/2 x E/2)56 θ e

DS20005627A-page 12  2016 Microchip Technology Inc. NOTES:

 2016 Microchip Technology Inc. DS20005627A-page 13 HV7350 APPENDIX A: REVISION HISTORY Revision A (October 2016)

• Converted Supertex Doc# DSFP- HV7350 to Microchip DS20005627A
• Changed the packaging quantity of 56-lead QFN M937 from 2000/Reel to 3000/Reel
• Made minor text changes throughout the docu - ment

DS20005627A-page 14  2016 Microchip Technology Inc. PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. Examples: a) HV7350K6-G: 8-Channel High-Speed ±60V ±1A Ultrasound RTZ Pulser, 56-lead VQFN, 250/Tray b) HV7350K6-G-M937: 8-Channel High-Speed ±60V ±1A Ultrasound RTZ Pulser, 56-lead VQFN, 3000/Reel PART NO. Device Device: HV7350 = 8-Channel High-Speed ±60V ±1A Ultrasound RTZ Pulser Package: K6 = 56-lead VQFN Environmental: G = Lead (Pb)-free/RoHS-compliant Package Media Type: (blank) = 250/Tray for a K6 Package M937 = 3000/Reel for a K6 Package XX Package - X - X Environmental Media Type Options

 2016 Microchip Technology Inc. DS20005627A-page 15 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application me ets with your specifications. MICROCHIP MAKES NO RE PRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting fr om such use. No licenses are conveyed, implicitly or ot herwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0997-7 Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal meth ods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC ® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==

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