HV7321

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Document overview

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Technical content

Features

• Power Sequencing Free 5 Output Levels including RTZ (Return-to-Zero)
• -44 dB Single-Cycle Pulse-Inversion Second Harmonic Distortion (HD2) at 5 MHz
• Output Voltage up to ±80V
• ±2.5A Peak Output Current
• ±300 mA Current from V PP1/VNN1 in CW Mode-0
• Integrated T/R Switch & RX Damper Switch
• Bleeder Switches Achieve True Zero during RTZ
• Supports Both Transparent and Re-Timing Mode
• Re-Timing Clock Frequency Supports up to

220 MHz

• Built-In Output Protection Diodes and Clamp Diodes
• +2.5/+3.3V Input Logic
• Built-In CW Switches to Pair with External CW Transmitters (CW Mode-1)
• 9 mm x 9 mm 64-Lead VQFN Package

Applications

• Medical Ultrasound Imaging Systems
• NDT Ultrasound
• Piezoelectric or Capacitive Transducer Drivers General Description The HV7321 is a 4-channel, 5-level, ultrasound transmitter with built-in T/R switches, output protection diodes and clamp diodes. The HV7321 can provide up to ±2.5A and the output voltage swing can be up to ±80V. The HV7321 supports both Transparent and Re-Timing mode. The re-t iming clock frequency can support up to 220 MHz. The re-timing feature helps reduce the output jitter in troduced by the driving the field-programmable gate array (FPGA). The HV7321 has two different modes for CW transmission, CW-Mode 0 and CW-Mode 1. In CW-Mode 0 (Mode = 0, PWS = 0), the V PP1 and VNN1 rails are used for CW transmission. The output current is reduced in CW Mode-0. In CW-Mode 1, the HV7321 accepts the output of an external CW beamformer as CW source. The HV7321 is LVCMOS 2.5V/3.3V input compatible, which can be interfaced with the FPGA directly. The HV7321 is available in a 9 mm x 9 mm 64-Lead VQFN package. 4-Ch. 5-Level ±80V High-Voltage Ultrasound Pulser with T/R Switches

DS20005639A-page 2  2016 Microchip Technology Inc. Package Types VSUB 6364 6061 59 58 5455565762 50515253 49 POS0 NEG0 SEL0 MODE VDD GND VGN VPP0 VPP0 CPF0 CNF0 VNN0 VNN0 VNN2 VNN1 CNF1 1CWIN0 SEL1 NEG1 POS1 PWS CLK GND VLL REN NEG2 CWIN2 SEL3 POS2 2019 2221 2524 26 27 3130292823 321817 CWIN1 OEN SEL2 NEG3 POS3 CWIN3 OTPN VDD GND VGP VPP0 CPF0 VNN0 VNN2 VNN1 CNF1 VPP0 CNF0 VNN0 CPF1 VPP1 TX0 RX0 RGND RX1 CNEG RGND TX3 CPF1 VPP1 RX3 RX2 TX2 CPOS TX1

 2016 Microchip Technology Inc. DS20005639A-page 3 HV7321 HV7321 – Block Diagram Rb OEN POS3 NEG3 SEL3 CLK RX0 +2.5V/3V +5V -10V GND VGN VSUB CNEG VNN2 CNF0 VNN0 CNF1 VNN1 TX0 RX0 RGND TX1,2,3 VLL VDD CPOS VGP CPF0 VPP0 CPF1 VPP1 2 µF 2 µF VPF1 VGN VPP1VPP0 VNEG GND V GN VNF1VNN2 VPP0 SUB VPOS To Ch. 1-3 0 to +80V0 to +80V 0 to -80V0 to -80V 2 µF 1 µF 2 µF 2 µF 2 µF 2 µF 2 µF100V 100V VGNVPF0GND 1 µF 1 µF 100V 2 µF 1 µF 100V 2 µF 2 µF 100V VNF0 VGP VNN0 VGP VNN1 VPP1 to CWSW1-3 CWSW0 VPF0 VNF0 VPF0 VNEG VNF1 VPOS VNN0 VNN1 RTZSW0 TRSW0 Rb RXDMP0 RGND 1 of 4 channels +10V LRVPOS LRVPF0 LRVPF1 RX1,2,3LRVNEG LRVNF0 LRVNF1 SEL0 NEG0 POS0 OTPN PWS REN MODE CWIN0-3 Logic and Retiming

DS20005639A-page 4  2016 Microchip Technology Inc. HV7321 – Typical Application Circuit +80V VPF1 VNN1 TX0 -60V VPP0 VNN0 -80V +60V 1 of 4 Channels VDD CWIN3 GND +2.5V VLL PWS POS3 VSUB MODE REN TX1-3 RX1-3 RX0 RGND RTZSW CWSW RXDMP TRSW VGP -10V OEN to other ICs CTRN[3:0] OTPN DT[63:0] CLL= 2 µF 10V CDD = 2µF 10V CGP = 2 µF 16V CPP0 = 2 µF 100V CPP1 = 2 µF 100V CNN1 = 2 µF 100V CGN = 2 µF 16V Connect to a low-voltage CW source (such as the MD1730) CCPOS = 1µF 10V CPOS CPF0 CPF1 CCPF1 = 2 µF 10V CNF0 CCNEG = 1 µF 10V CNEG CNF1 CCNF1 = 2 µF 10V CNN0 = 2 µF 100V CCNF0 = 2 µF 10V CCPF1 = 2 µF 10V VNN2 VNF1 TXFPGA I/Os +5V +10V VPP1 RX0 VGN RGND SUB TRSW Decode Level Shift VPF0 VNF0 CWIN2 CWIN1 CWIN0 CLK NEG3 SEL3 POS0 NEG0 SEL0 OTPN For CW Mode-1

 2016 Microchip Technology Inc. DS20005639A-page 5 HV7321

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings † † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at th ose or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

VSUB = 0V, PWS = OEN = REN = 1, TA = 25°C, unless otherwise specified. Parameters in Bold apply over the operating temperature range of TA = TJ = 0 to +85°C. Parameter Sym. Min. Typ. Max. Unit Conditions Operating Supply Voltages Positive Logic Supply V LL 2.25 2.50 3.60 V Note 1 Positive Voltage Supply V DD 4.75 5.0 5.25 V Note 1 Positive Gate Driver Supply V GP 8.0 10 12 V Note 1 See Table 3-1.Negative Gate Driver Supply V GN -12 -10 -8.0 High Voltage Positive Supply VPP0 0 — 80 V Note 1 Must be VPP0 ≥ VPP1VPP1 0 — 80 High Voltage Negative Supply VNN0 -80 — 0 V Note 1 Must be VNN0  VNN1VNN1 -80 — 0 Operating Supply Current VLL Quiescent Current I LLQ —0 . 0 6 0 . 7 μA OEN = REN = 0 VDD Quiescent Current I DDQ —3 08 0 µ A VPP0 Quiescent Current I PP0Q —0 . 3 7 6 µ A VNN0 Quiescent Current I NN0Q -9 -0.78 — µA VPP1 Quiescent Current I PP1Q —0 . 4 41 0 µ A VNN1 Quiescent Current I NN1Q -10 -1.46 — µA VNN2 Quiescent Current I NN2Q -7 -3.84 — µA Note 1: Characterized only; not 100% tested in production. 2: Design guidance only.

DS20005639A-page 6  2016 Microchip Technology Inc. VDD Current I DDEN —0 . 9 1 . 0 m A f = 0 MHz fCLK = 0 MHz MODE = 0 or 1 VPP0 Current I PP0EN — 0.1 0.13 mA VNN0 Current I NN0EN -0.12 -0.1 — mA VPP1 Current I PP1EN — 0.1 0.13 mA VNN1 Current I NN1EN -0.12 -0.1 — mA VNN2 Current I NN2EN -0.05 -0.03 — mA VLL Current with Re-Timing I LLRT — 0.11 0.3 mA f CLK = 80 MHz TX one-channel output, no load, continuous, Note 1V DD Current with Re-Timing I DDRT —7 . 0 8 8 m A VLL Max. Current of SEL = 0/1 I LL5 —2 34 0 μA CLK = 0 PWS = 1 MODE = 0 I PP05/INN05 and IPP15/INN15 are calculated using TX one channel output continuous, no load, at 5M H z . V DD Max. Current of SEL = 0/1 I DD5 —1 . 5 1 . 7 m A VGP Max. Current of SEL = 0/1 I GP5 —2 . 6 4m A VGN Max. Current of SEL = 0/1 I GN5 -14 -9 — mA VPP0 Current of SEL = 0 (1) IPP05 — 136 146 mA VNN0 Current of SEL = 0 (1) INN05 -132 -125 — mA VPP1 Current of SEL = 1 (1) IPP15 — 148 158 mA VNN1 Current of SEL = 1 (1) INN15 -150 -143 — mA VGP Current of SEL = 1 I GPCW — 1.0 2.0 mA TX one-channel output 5 MHz, continuous, no load VPP1/VNN1 =± 5 V PWS = MODE = 0 CW Mode-0, Note 1 VGN Current of SEL = 1 I GNCW -8.0 -5.0 — mA VPP1 Current of SEL = 1 I PP1CW —1 72 6 m A VNN1 Current of SEL = 1 I NN1CW -20 -15 — mA CWSW High-Voltage Analog Switch CW Switch Input Voltage V CWSW Analog Switch On-Resistance (1) RCWSW — 26.5 35 Ω ICWSW = ±100 mA TRSW Off Withstand Voltage V CWSW -80 — +80 V I SW = ±1.0 μA CWSW Off Capacitance to GND CCWSW —5 . 0— pF MODE = 1, 1 MHz, 0 dBm, DC 0V, Note 1CWSW On Capacitance to GND — 60 — CWSW Switching On Time tCWSW — 800 1100 ns 50% MODE rise to CWSW on/off Note 1CWSW Switching Off Time — 66 90 TX Output P-Channel MOSFET on VPP0 On-Resistance R ON_P0 —8 . 51 9 Ω ISD = 100 mA Peak Output Current I OUT_P0 11 . 5 —A VPP0 = +25V, RL = 1.0Ω to GND Note 1 2.0 2.8 — A VPP0 = +80V, RL = 1.0Ω to GND Note 1 ELECTRICAL CHARACTERISTICS (CONTINUED) VSUB = 0V, PWS = OEN = REN = 1, TA = 25°C, unless otherwise specified. Parameters in Bold apply over the operating temperature range of TA = TJ = 0 to +85°C. Parameter Sym. Min. Typ. Max. Unit Conditions Note 1: Characterized only; not 100% tested in production. 2: Design guidance only.

 2016 Microchip Technology Inc. DS20005639A-page 7 HV7321 TX Output P-Channel MOSFET on VPP1 On-Resistance at PWS = 1 RON_P1 —1 62 1 Ω ISD = 100 mAOn-Resistance at PWS = 0 — 33 43 Peak Output Current at PWS = 1 (1) IOUT_P1 0.8 1.0 — A VPP0,1 = +25V, RL = 1.0Ω to GND 1.5 1.75 — V PP0,1= +80V, RL = 1.0Ω to GND Peak Output Current at PWS = 0 (1) 0.4 0.5 — V PP0,1 = +25V, RL = 1.0Ω to GND 0.8 0.95 — V PP0,1 = +80V, RL = 1.0Ω to GND TX Output N-Channel MOSFET on VNN0 On-Resistance RON_N0 —81 0 Ω ISD = 100 mA Peak Output Current (1) IOUT_N0 -1.4 -1.7 — A V NN0 = -25V, RL = 1.0Ω to GND -2.0 -2.3 — A V NN0 = -80V, RL = 1.0Ω to GND TX Output N-Channel MOSFET on VNN1 On-Resistance at PWS = 1 RON_N1 —1 11 3 Ω ISD = 100 mAOn-Resistance at PWS = 0 — 36 45 Peak Output Current at PWS = 1 (1) IOUT_N1 — -1.2 -1.0 A VNN0,1 = -25V, RL = 1.0Ω to GND — -1.6 -1.3 V NN0,1 = -80V, RL = 1.0Ω to GND Peak Output Current at PWS = 0 (1) — -0.4 -0.3 V NN0,1 = -25V, RL = 1.0Ω to GND — -0.55 -0.4 V NN0,1= -80V, RL = 1.0Ω to GND TX Damping P-Channel MOSFET on GND On-Resistance RON_PDMP —7 . 01 6 Ω ISD = 100 mA Peak Output Current (1) IOUT_PDMP 2.3 2.7 — A RL = 1.0Ω from -25V to TX 2.3 2.8 — A RL = 1.0Ω from -80V to TX TX Damping N-Channel MOSFET on GND On-Resistance RON_NDMP —7 . 01 6 Ω ISD = 100 mA Peak Output Current (1) IOUT_NDMP — -2.0 -1.8 A RL = 1.0Ω from +25V to TX — -2.3 -2.0 A RL = 1.0Ω from +80V to TX RTZSW Auto Bleed High-Voltage Analog Switch RTZSW On-Resistance (1) RRTZSW — 238 270 Ω ISD = ±1.0 mA RTZSW Off Withstand Voltage (1) VRTZSW -80 — +80 V ISW = ±100 μA TX OUTPUT Isolation Diodes and Bleed Resistor Diode Forward Voltage V F —0 . 9 6 1 . 9 V I FM = 300 mA, Note 1 Forward Continuous Current I FM — 300 — mA Note 2 Peak Forward Pulse Current I FSM — 3.0 — A PW = 50 ns, Note 2 Total Capacitance of 2-diode C T — 3.5 — pF at 1 MHz, 1 dBm, 0V DC, Note 2 TX/RX Bleed Resistor to GND R b 11 15 20 k Ω Note 1 ELECTRICAL CHARACTERISTICS (CONTINUED) VSUB = 0V, PWS = OEN = REN = 1, TA = 25°C, unless otherwise specified. Parameters in Bold apply over the operating temperature range of TA = TJ = 0 to +85°C. Parameter Sym. Min. Typ. Max. Unit Conditions Note 1: Characterized only; not 100% tested in production. 2: Design guidance only.

DS20005639A-page 8  2016 Microchip Technology Inc. TRSW and RXDMP Switches TRSW Analog Switch On-Resistor RTRSW —1 82 2 Ω ITRSW = ±1.0 mA Note 1 TRSW Off Withstand Voltage V TRSW -80 — +80 V I SW = ±100 μA, Note 1 RX to GND Protection Diode V F —1 . 5 2 . 2V I F = ±100 mA, Note 1 RXDMP Switch On-Resistance R RXDMP —1 72 1 Ω ISD = ±1.0 mA, Note 1 RX Pin to GND Capacitance C RXG — — 7.0 pF 1 MHz, 1 dBm, 0V DC, Note 2 Built-In Gate Drive Voltage Linear Regulators Output P-Channel Gate Drive Voltage Referenced to VPP0 VPF0 -5.2 -4.6 -3.8 V V GN - VPP0 < -10V Output P-Channel Gate Drive Voltage Referenced to VPP1 VPF1 -5.2 -4.6 -3.8 V V GN - VPP1 < -10V Output N-Channel Gate Drive Voltage Referenced to VNN0 VNF0 3.3 4.2 5.2 V V GP - VNN0 > 10V Output N-Channel Gate Drive Voltage Referenced to VNN1 VNF1 3.3 4.2 5.2 V V GP - VNN1 > 10V Output N-Channel Gate Drive Voltage Referenced to GND VPOS 3.2 4.2 5.2 V Output P-Channel Gate Drive Voltage Referenced to GND VNEG -5.2 -4.5 -3.8 V Dropout Voltage of (VPP0 - VGN) V DOPF0 -2.9 -2.6 -2.4 V Dropout Voltage of (VPP1 - VGN)V DOPF1 -2.9 -2.6 -2.4 V Dropout Voltage of (VGP - VNN0)V DONF0 3.0 3.3 3.6 V Dropout Voltage of (VGP - VNN1)V DONF1 3.0 3.3 3.6 V Dropout Voltage of (VNEG - VGN)V DONEG 2.9 3.3 3.5 V Dropout Voltage of (VGP - VPOS)V DOPOS -2.8 -2.6 -2.4 V Logic & Clock Input Characteristics Input Logic Low Voltage V IL 0 — 0.2 V LL V Input Logic High Voltage V IH 0.8 VLL —V LL V Input Logic Low Current I IL -1.0 — — μA Note 1 Input Logic High Current I IH —— 1 . 0 μA Note 1 Input Capacitance C IN —2 . 0 3 . 0 p F Note 2 OEN Switching On Time tOEN — 200 — µs 50% OEN rise to TX ready, Note 2 OEN Switching Off Time — 20 — ns 50% OEN fall to TX all output FETs on HV rails are off, Note 1 Thermal protection OTPN & UVLO OTPN Output Max. Pull-Up V OH — — 5.25 V OTPN Output Low Max. Voltage V OL — — 0.1 V at 100 μA — — 0.4 V at 4.0 mA OTPN Output High Current I OFF ——1 5 μA 25°C, at 5.25V pull-up, Note 1 ELECTRICAL CHARACTERISTICS (CONTINUED) VSUB = 0V, PWS = OEN = REN = 1, TA = 25°C, unless otherwise specified. Parameters in Bold apply over the operating temperature range of TA = TJ = 0 to +85°C. Parameter Sym. Min. Typ. Max. Unit Conditions Note 1: Characterized only; not 100% tested in production. 2: Design guidance only.

 2016 Microchip Technology Inc. DS20005639A-page 9 HV7321 Thermal Shutdown Trip Point T TRIP 125 138 160 °C OTPN = LO when thermal shut- down occurs, Note 1Thermal Shutdown Hysteresis T HYS —3 8—° C VDD OK On Voltage V DDUVON 3.45 3.7 4.05 V Note 1VDD UVLO Trip Voltage V DDUVOFF 3.05 3.4 3.85 VLL OK On Voltage V LLUVON 1.59 1.7 1.81 VLL UVLO Trip Voltage V LLUVOFF 1.39 1.6 1.71 TX Output HD2 & Timing Characteristics Second Harmonic Distortion HD2 — -44 -40 dB V PP0/VNN0 = ±70V launched in 100 µs apart, with load of 220 pF//1k (Second Harmonic Distortion). HD2, single-cycle inverting

5.0 MHz

All these tr,tf,td values, at V PP0,1/VNN0,1 = ±70V, 220 pF//1k Note 1 Output Rise Time from 0V to VPP0 tr1 —1 01 2 ns Output Fall Time from 0V to VNN0 tf1 —1 01 2 Output Rise Time from VNN0 to VPP0 tr2 —1 71 9 Output Fall Time from VPP0 to VNN0 tf2 —1 71 9 Output Rise Time from VNN0 to 0V tr3 — 10 13.5 Output Fall Time from VPP0 to 0V t f3 — 10 13.5 Propagation Delay Rise Time 1 t dr1 —1 61 8 ns Propagation Delay Fall Time 1 t df1 —1 61 8 Propagation Delay Rise Time 2 t dr2 — 17.5 19 Propagation Delay Fall Time 2 t df2 — 17.5 19 Propagation Delay Rise Time 3 t dr3 —1 41 6 Propagation Delay Fall Time 3 t df3 —1 41 6 Output Rise Time from 0V to VPP1 tr4 —1 51 7 ns All these tr,tf,td values at VPP0,1/VNN0,1 = ±70V, 220 pF//1k Note 1 Output Fall Time from 0V to VNN1 tf4 —1 51 7 Output Rise Time from VNN1 to VPP1 tr5 —2 42 7 Output Fall Time from VPP1 to VNN1 tf5 —2 42 7 Output Rise Time from VNN1 to 0V tr6 —1 01 3 Output Fall Time from VPP1 to 0V t f6 —1 01 3 Propagation Delay Rise Time 4 t dr4 —1 51 7 ns Propagation Delay Fall Time 4 t df4 —1 51 7 Propagation Delay Rise Time 5 t dr5 —1 61 8 Propagation Delay Fall Time 5 t df5 —1 61 8 Propagation Delay Rise Time 6 t dr6 —1 51 7 Propagation Delay Fall Time 6 t df6 —1 51 7 Delay Time Matching with SEL = L ∆td1 —1 . 5 2 . 0n s P to N, ch.-to-ch. matching in IC, typ. at VPP0,1/VNN0,1,2 = ±70V, 220 pF//1k, Note 1Delay Time Matching with SEL = H ∆td2 —1 . 5 2 . 0n s ELECTRICAL CHARACTERISTICS (CONTINUED) VSUB = 0V, PWS = OEN = REN = 1, TA = 25°C, unless otherwise specified. Parameters in Bold apply over the operating temperature range of TA = TJ = 0 to +85°C. Parameter Sym. Min. Typ. Max. Unit Conditions Note 1: Characterized only; not 100% tested in production. 2: Design guidance only.

DS20005639A-page 10  2016 Microchip Technology Inc. TRSW Switch On Delay Time tTRSW 130 180 230 ns From POS = 0 & NEG = 0, Note 1 TRSW Switch Off Delay Time 8 12 16 ns From POS = 1 or NEG = 1, Note 1 RTZSW Switch On Delay Time tRTZSW 130 180 240 ns From POS = 0 & NEG = 0, Note 1 RTZSW Switch Off Delay Time 11 21 31 ns From POS = 1 or NEG = 1, Note 1 RXDMP Damp Switch On Delay Time tRXDMP 3 10 15 ns From POS = 1 or NEG = 1, Note 1 RXDMP Damp Switch Off Delay Time 0.55 1.4 2.35 us From POS = 0 & NEG = 0, Note 1 PWS = 0 to 1 Mode Change Time tMC — 220 — ns Note 2 Output Max. Frequency Range f OUT — 20 — MHz 100 Ω resistor load, Note 2 Re-Timing Clock Frequency f CLK 10 — 220 MHz Note 2 Re-Timing Clock Rise & Fall Times tRC,tFC —0 . 5 5 . 0n s Note 2 Set-Up Time, POS/NEG to CLK t su 2.0 — — ns Note 2 Hold Time, CLK to POS/NEG t H 1.0 — — ns Note 2 Clock Time Low (2) tCLK_LO 2.0 — 100 ns CLK input must be activated before POS and NEG inputs are high. CLK input must be deacti- vated after POS and NEG inputs are low. Clock Time High (2) tCLK_HI 2.0 — 100 Clock Recognition Time (1) tCLK_REC —2 . 0— Clock Release Time (1) tCLK_RLS 150 330 500 TEMPERATURE CHARACTERISTICS Unless otherwise indicated, all parameters apply with VLL = +2.5V, VDD = +5.0V, VPP0,1 = +80V, VNN0,1,2 = -80V, VGP = +10V, VGN = -10V, VSUB = 0V, OEN = REN = 1 Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Operating Ambient Temperature Range T OA 0— + 8 5 ° C Storage Temperature Range T ST -55 — +150 °C Maximum Junction Temperature T J — — +130 °C Total Power Dissipation PD — 3.0 — W Thermal Package Resistances (64LD 9 mm x 9 mm VQFN) Junction-to-Ambient Thermal Resistance JA —1 6 . 3—° C / W JEDEC (2S2P) 4L PCB 114.3 mm x 76.2 mm x1.6 mm T A = 85°C Junction-to-Board Thermal Resistance JB — 2.55 — °C/W JEDEC (2S2P) 4L PCB 114.3 mm x 76.2 mm x1.6 mm T A =8 5 ° C Junction-to-Case Top Thermal Resistance JC —0 . 2— ° C / W JEDEC (2S2P) 4L PCB 114.3 mm x 76.2 mm x1.6 mm T A =8 5 ° C ELECTRICAL CHARACTERISTICS (CONTINUED) VSUB = 0V, PWS = OEN = REN = 1, TA = 25°C, unless otherwise specified. Parameters in Bold apply over the operating temperature range of TA = TJ = 0 to +85°C. Parameter Sym. Min. Typ. Max. Unit Conditions Note 1: Characterized only; not 100% tested in production. 2: Design guidance only.

 2016 Microchip Technology Inc. DS20005639A-page 11 HV7321 TABLE 1-1: INPUT OUTPUT LOGIC TRUTH TABLE (TRANSPARENT, CLK = 0) Function OTP N Logic Inputs TX Output RTZSW TRSW CWSW RXDMP OEN MODE PWS CLK SEL NEG POS Pulsed-Echo Mode (1) 11 0 1 0 0 0 0 R T Z O F F O F F O N 11 0 1 0 0 0 1 V PP0 OFF OFF ON 11 0 1 0 0 1 0 V NN0 OFF OFF ON 11 0 1 0 0 1 1 R T Z + (4) ON OFF OFF 11 0 1 0 1 0 0 R T Z O F F O F F O N 11 0 1 0 1 0 1 V PP1 OFF OFF ON 11 0 1 0 1 1 0 V NN1 OFF OFF ON 1 1 0 1 0 1 1 1 high Z OFF OFF ON CW Mode-0 (2) 11 0 0 0 0 0 0 R T Z O F F O F F O N 11 0 0 0 0 0 1 V PP0 OFF OFF ON 11 0 0 0 0 1 0 V NN0 OFF OFF ON 11 0 0 0 0 1 1 R T Z + (4) ON OFF OFF 11 0 0 0 1 0 0 R T Z O F F O F F O N 11 0 0 0 1 0 1 V PP1 OFF OFF ON 11 0 0 0 1 1 0 V NN1 OFF OFF ON 1 1 0 0 0 1 1 1 high Z OFF OFF ON CW Mode-1 (3) 11 1 x x other than 011 high Z OFF ON ON

011 R T Z + (4) ON OFF OFF

Disabled x 0 x x x x x x high Z OFF OFF ON Thermal Protection Activated 0 x x x x x x x high Z OFF OFF ON Note 1: In Pulsed-Echo mode, low duty cycle must be used due to the IC power dissipation limit. 2: When PWS = 0, VPP1/VNN1 output current is reduced for low-voltage CW mode-0. VPP0/VNN0 output current is unaffected when PWS = 1, as in Pulsed-Echo mode. 3: In CW MODE = 1, the CWSW is turned on to use external CW waveform at CWIN, if the channel S E L=N E G=P O S=0 . 4: When SEL = 0, NEG = 1, POS = 1, the channel is in Receiving mode (RTZ+).

DS20005639A-page 12  2016 Microchip Technology Inc. TABLE 1-2: INPUT OUTPUT LOGIC TRUTH TABLE (WITH CLK RE-TIMING, CLK  10MHZ) Function OTP N Logic Inputs TX Output RTZSW TRSW CWSW RXDMP OEN MODE PWS CLK SEL NEG POS Pulsed-Echo Mode (1) 11 0 1 ↑ 000R T ZO F FO F F O N 11 0 1 ↑ 001V PP0 OFF OFF ON 11 0 1 ↑ 010V NN0 OFF OFF ON 11 0 1 ↑ 011 R T Z + (4) ON OFF OFF 11 0 1 ↑ 100R T ZO F FO F F O N 11 0 1 ↑ 101V PP1 OFF OFF ON 11 0 1 ↑ 110V NN1 OFF OFF ON 11 0 1 ↑ 111 h i g h Z O F FO F F O N CW Mode-0 (2) 11 0 0 ↑ 000R T ZO F FO F F O N 11 0 0 ↑ 001V PP0 OFF OFF ON 11 0 0 ↑ 010V NN0 OFF OFF ON 11 0 0 ↑ 011 R T Z + (4) ON OFF OFF 11 0 0 ↑ 100R T ZO F FO F F O N 11 0 0 ↑ 101V PP1 OFF OFF ON 11 0 0 ↑ 110V NN1 OFF OFF ON 11 0 0 ↑ 111 h i g h Z O F FO F F O N CW Mode-1 (3) 11 1 xx other than 011 high Z OFF ON ON Disabled x0 x xxxxx h i g h Z O F FO F F O N Thermal Protection Activated 0x x xxxxx h i g h Z O F FO F F O N Note 1: In Pulsed-Echo mode, low duty cycle must be used due to the IC power dissipation limit. 2: When PWS = 0, VPP1/VNN1 output current is reduced for low-voltage CW mode-0. VPP0/VNN0 output current is unaffected when PWS = 1, as in Pulsed-Echo mode. 3: In CW MODE = 1, the CWSW is turned on to use external CW waveform at CWIN, if the channel S E L=N E G=P O S=0 . 4: When SEL = 0, NEG = 1, POS = 1, the channel is in Receiving mode (RTZ+).

 2016 Microchip Technology Inc. DS20005639A-page 13 HV7321

1.1 TYPICAL TIMING DIAGRAMS

Figure 1-1 shows the timing of control inputs and RTZ, T/R and RXDMP switches per each channel of the HV7321. Upon the completion of a receiving period, an RTZ period (SEL, NEG, POS = 000) should be asserted before transmitting again. FIGURE 1-1: Logic Input Timing Diagram. FIGURE 1-2: TX Output Timing Diagram. FIGURE 1-3: Timing Diagram of HV7321 TX Output and Switches in CW Mode-1 Driven by External CW Source. 001 010 000 010 001 101 110 100 110 101 tdr1 tr1 tf2 tdf2 tr3 tdr3 tf1 tdf1 tr2 tdr2 tf3 tdf3 tdr4 tr4 tf5 tdf5 tr6 tdr6 tf4 tdf4 tr5 tdr5 tf6 tdf6 TX output SEL input NEG input POS input TX output VPP0 SEL input NEG input POS input RTZSW switch tRTZSW(OFF) RX time ON PWS input tMCCW-mode TRSW switch RXDMP switch RTZ+ B-Mode ON OFF RTZ TX time ON OFF OFF VNN0 RTZ VPP1 VNN1 RTZ RTZ+ 000 000000000 011 011 011 001 010 101 110 ON ON OFF tTRSW(OFF) tRXDMP(ON) tRTZSW(ON) tTRSW(ON) tRXDMP(OFF) RX time External CW Source VCW+ External CW source SEL Input NEG Input POS Input MODE Input External CW Source VCW- HV7321 Tx Output RTZ Hi-Z Per Ch CW Delay in external CW source RTZ CW end MODE = 0MODE = 1 000 000

DS20005639A-page 14  2016 Microchip Technology Inc. NOTES:

 2016 Microchip Technology Inc. DS20005639A-page 15 HV7321

2.0 TYPICAL PERFORMANCE CURVES

FIGURE 2-1: ILLQ vs. Temperature. FIGURE 2-2: IPP0Q vs. Temperature. FIGURE 2-3: IPP1Q vs. Temperature. FIGURE 2-4: IDDQ vs. Temperature. FIGURE 2-5: INN0Q vs. Temperature. FIGURE 2-6: INN1Q vs. Temperature. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or ta bles, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0.1 0.2 0.3 0.4 0.5 0 2 55 07 5 1 0 0 ILLQ (ȝA) Temperature (°C) 0 2 55 07 5 1 0 0 IPP0Q (ȝA) Temperature (°C) 0 2 55 07 5 1 0 0 IPP1Q (ȝA) Temperature (°C) 0 2 55 07 5 1 0 0 IDDQ (ȝA) Temperature (°C) 02 5 5 0 7 5 1 0 0 INN0Q (ȝA) Temperature (°C) 0 2 55 07 5 1 0 0 INN1Q (ȝA) Temperature (°C)

 2016 Microchip Technology Inc. DS20005639A-page 17 HV7321

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Pin Symbol Description 1C W IN0 External CW input for channel 0 2 SEL1 SEL input logic pin selects transmission high-voltage rails for channel 1. If SEL = 0, select VPP0/VNN0. If SEL = 1, select VPP1/VNN1. See Table 1-1. 3N E G 1 NEG input logic pin turns on/off corresponding output N-channel MOSFET for channel 1. See Table 1-1. 4P O S 1 POS input logic pin turns on/off corresponding output P-channel MOSFET for channel 1. See Table 1-1. 5C W IN1 External CW input for channel 1 6O E N Output enable logic input pin. When OEN = VLL, the transmitter outputs are enabled. When OEN = 0, the transmitter outputs are disabled. 7P W S Logic input pin. When PWS = 0, the output FETs for VPP1 and VNN1 are scaled down to reduce the output current for CW Mode-0. 8 CLK Re-timing clock input pin. Connect CLK to ground for transparent mode. 9, 22, 59 GND Ground

10 V LL Input logic power supply pin

11 REN Enable pin for the built-in voltage regulators.See section Section 4.3 “Operation Modes” for details. 12 SEL2 SEL input logic pin selects transmission high-voltage rails for channel 2. If SEL = 0, select VPP0/VNN0. If SEL = 1, select VPP1/VNN1. See Table 1-1.

13 NEG2 NEG input logic pin turns on/off corresponding output N-channel MOSFET for

channel 2. See Table 1-1. 14 POS2 POS input logic pin turns on/off corresponding output P-channel MOSFET for channel 2. See Table 1-1.

15 CW IN2 External CW input for channel 2

16 SEL3 SEL input logic pin selects transmission high-voltage rails for channel 3. If SEL = 0, select VPP0/VNN0. If SEL = 1, select VPP1/VNN1. See Table 1-1.

17 NEG3 NEG input logic pin turns on/off corresponding output N-channel MOSFET for

channel 3. See Table 1-1. 18 POS3 POS input logic pin turns on/off corresponding output P-channel MOSFET for channel 3. See Table 1-1.

19 CW IN3 External CW input for channel 3

20 OTP N Temperature sensor open drain output

21, 60 V DD +5V supply

23 V GP +10V supply pin for the linear regulator

24, 25, 56, 57 V PP0 Positive high-voltage supply pin. VPP0 must be equal to or greater than VPP1. 26, 55 C PF0 Internal linear regulator output pin. Connect 2 µF 10V capacitor to VPP0. 27, 54 C NF0 Internal linear regulator output pin. Connect 2 µF 10V capacitor to VNN0. 28, 29, 52, 53 V NN0 Negative high-voltage supply pin. VNN0 must be equal to or more negative than VNN1,2 30, 51 V NN2 Negative high-voltage supply pin. VNN2 connects to the most negative supply rail. 31, 50 V NN1 Negative high-voltage supply pin. VNN1 must be equal to or less negative than VNN0. 32, 49 C NF1 Internal linear regulator output pin. Connect 2 µF 10V capacitor to VNN1. 33, 48 C PF1 Internal linear regulator output pin. Connect 2 µF 10V capacitor to VPP1. 34, 47 V PP1 Positive high voltage supply VPP1. Must be equal to or lower than VPP0.

35 TX3 Channel 3 transmitter output pin

DS20005639A-page 18  2016 Microchip Technology Inc.

36 RX3 Channel 3 T/R switch output

37, 44 R GND Power ground

38 RX2 Channel 2 T/R switch output

39 TX2 Channel 2 transmitter output pin

40 C NEG Internal linear regulator output pin. Connect 1 µF 10V capacitor to GND. 41 C POS Internal linear regulator output pin. Connect 1 µF 10V capacitor to GND.

42 TX1 Channel 1 transmitter output pin

43 RX1 Channel 1 T/R switch output

45 RX0 Channel 0 T/R switch output

46 TX0 Channel 0 transmitter output pin

GN -10V supply pin for the linear regulator 61 MODE CW Mode selection pin. See section Section 4.3 “Operation Modes”. 62 SEL0 SEL input logic pin selects transmission high-voltage rails for channel 0. If SEL = 0, select VPP0/VNN0. If SEL = 1, select VPP1/VNN1. See Table 1-1.

63 NEG0 NEG input logic pin turns on/off corresponding output N-channel MOSFET for

channel 0. See Table 1-1. 64 POS0 POS input logic pin turns on/off corresponding output P-channel MOSFET for channel 0. See Table 1-1. Thermal Pad V SUB Connect to ground. TABLE 3-1: PIN FUNCTION TABLE (CONTINUED) Pin Symbol Description

 2016 Microchip Technology Inc. DS20005639A-page 19 HV7321

4.0 DEVICE DESCRIPTION

4.1 Overview

The HV7321 is a 4-channel, 5-level ultrasound transmitter with built-in T/R switches, output protection diodes and clamp diodes. The HV7321 can provide up to 2.6A and the output voltage swing can be up to 80V. The HV7321 supports both Transparent and Re-Timing mode. The re-timing clock frequency can support up to 220 MHz. The re-timing feature helps reduce the output jitter introduced by the driving FPGA.

4.2 Recommended Power-up

Powering up/down in any arbitrary sequence will not cause any damage to the device. The powering-up sequences in Table 4-1 are only recommended in order to minimize possible in-rush current. Figure 4-1 shows the timing diagram of related signals. FIGURE 4-1: Power-On Events and Power-Saving Time Diagram.

4.3 Operation Modes

There are five modes of operation: Device Disabled, Output Disabled, Pulsed-Echo Mode, CW Mode-0 and CW Mode-1.

4.3.1 DEVICE ENABLE MODE

In Device Disabled mode, the regulators are turned off when REN is low. The regulators are ON when REN = VLL. All regulators are ON except V NEG and VPOS for power saving when REN = 1. When REN is low, OEN = X (OEN = 1 or 0) since device is disabled. Refer to Table 4-2.

4.3.2 OUTPUT HIGH Z MODE

In Output Disabled mode, regulators are enabled REN = 1 and OEN = 0 (Output Enable logic input) and output pins (TX0-3) are in high Z state. OEN = 1 enables the outputs.

4.3.3 PULSED-ECHO MODE

Pulsed-Echo mode (B-mode) enables the 5-level waveform generation. OEN = 1, MODE = 0, and PWS = 1 enable Pulsed-Echo mode after HV7321 powers on. SEL/NEG/POS inputs of desired channel determine the corresponding TX Output pulse. TABLE 4-1: POWER-UP SEQUENCE Step Power-Up Description 1V LL ON with logic signal low 2V DD, VGP and VGN ON 3R E N = 1 4V PP0,1 and VNN0,1 ON

5 OEN = 1 & Logic control signal active

VDD > VDDUVON VGP input VPP input OEN input REN input Internal VDD Power-Good Signal |VGN| |VNN| tOEN_ON VCNEG output VPPࡳVCPF VCNF ࡳVNN (3V) Ready to Work (Power Saving) TABLE 4-2: REN & OEN LOGIC INPUTS REN OEN Device TX Output

0 X Disabled high Z

DS20005639A-page 20  2016 Microchip Technology Inc.

4.3.4 CW MODE-0

CW Mode-0 enables continuous wave mode provided solely by the HV7321. OEN = 1, MODE = 0 and PWS = 0 activate CW Mode-0. FPGA selects VPP1 and VNN1 amplitudes via SEL/NEG/POS inputs. In theory, V PP0 and V NN0 can be selected but this is strongly discouraged since V PP0 and V NN0 usage increases power consumptio n and causes excessive heating in CW Mode-0.

4.3.5 CW MODE-1

CW Mode-1 is enabled using an external CW signal source for continuous wave mode. OEN = 1 and MODE = 1 activate CW Mode -1. External CW signals can connect to any of CW IN0-3. In this mode, the CW signal source also feeds the CLK input. See Table 4-3 for details.

4.3.5.1 External CW Beamformer Option

(CW Mode-1) The HV7321 has built-in CW switches that allow the use of an external CW beamformer to further minimize jitter and phase noise on CW waveforms. This mode is called CW Mode-1. One suggested external CW beamformer is the MD1730, which has very low phase noise and 8-channel CW output. A pair of HV7321s can operate with the MD1730 as an 8-channel CW waveform generator. See Figure 4-2. The MD1730 supports both differential and single-ended signals using CLKP and CLKN inputs. The MD1730 enables setting the CW output phase delay and frequency for channels via SPI. Please refer to the MD1730 data sheet for more information. FIGURE 4-2: HV7321 + MD1730 Integration. TABLE 4-3: MODE & PWS LOGIC INPUTS Mode PWS State 0 0 CW Mode-0 0 1 Pulsed-Echo

1 X CW Mode-1

TABLE 4-3: MODE & PWS LOGIC INPUTS Mode PWS State 1 of 4 channles +1V to +8V +2.5V RX0 -10V TXRW to next HV7321 CLK to other ICs CTRN[3:0] OTPN DT[63:0] TX FPGAI/Os OEN REN MODE PWS OTPN SEL0 NEG0 POS0 SEL3 NEG3 POS3 CLK CWIN0 CWIN1 CWIN2 CWIN3 GND VSUB SUB VGN RX1-3 TX1-3 RGND RGND RXDMP RX0 TX0 VNN1 VPP1 VNN0 VPP0 VGPVPPVLL +5V +10V 0V to +80V 0V to -80V 0V to -80V 0V to +80V TRSW TRSW RTZSW VPF1 VNF1 VPF0 VNF0 Decode & Level Shift +2.5V +5V +10V VGPVPPVLL CPF VCW+ CKB0 VLL CBE1 CLK CLK VLLCBE0 VCW+ CKB1 CW0 CW1 CW2 CW3 CW4~7 to next HV7321 CWIN03 VCW-CNFVGNDAPGND SUB other CW channels 1 of 8 channels MD1730 VCW- VPF VNF CW Fre. Dvdr & Phase Delay SPI LVDS CLK CWSW HV7321 -1V to -8V-10V EN SPIM CS SDO SDI SCK CLK CLK CBE0,1

 2016 Microchip Technology Inc. DS20005639A-page 21 HV7321

4.4 High Temperature Protection

When overtemperature is detected, OTPN = 0 and all outputs are high Z regardless of OEN and the other logic control inputs. Table 4-4 shows the relationship between REN, OEN inputs, OTPN output, and the corresponding device status. TABLE 4-4: REN, OEN, OTP N VS. DEVICE STATUS OTPN REN OEN Device TX Output 0 0 X Disabled high Z 0 1 X Enabled high Z 1 0 X Disabled high Z 1 1 0 Enabled high Z 1 1 1 Enabled ON

DS20005639A-page 22  2016 Microchip Technology Inc. NOTES:

 2016 Microchip Technology Inc. DS20005639A-page 23 HV7321

5.0 PACKAGING INFORMATION

5.1 Package Marking Information

Legend:XX...XProduct Code or Customer-specific information YYear code (last digit of calendar year) YYYear code (last 2 digits of calendar year) WWWeek code (week of January 1 is week ‘01’) NNNAlphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) *This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part nu mber cannot be marked on one line, it will be carried over to the next line, th us limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo. 64-Lead VQFN (9 x 9 x 1.0 mm) Example HV7321K6 1642256

DS20005639A-page 24  2016 Microchip Technology Inc. Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.

 2016 Microchip Technology Inc. DS20000000A-page 25 HV7321 APPENDIX A: REVISION HISTORY Revision A (October 2016)

• Original Release of this Document.

DS20000000A-page 26  2016 Microchip Technology Inc. NOTES:

 2016 Microchip Technology Inc. DS20000000A-page 27 HV7321 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX PackageDevice Device: HV7321: 4-Ch. 5-Level ±80V High-Voltage Ultrasound Pulser with T/R Switches Package: K6 = Very Thin Plastic Quad Flat Pack, No Lead Package, 9.00 x9.00 x1.0 mm Body, 0.50 mm Pitch, 64-Lead (VQFN) Environmental: G = Lead (Pb)-free/ROHS-compliant package Examples: a) HV7321K6-G: 4-Ch. 5-Level ±80V High-Voltage Ultrasound Pulser with T/R Switches 64LD 9x9 mm VQFN package Environmental

DS20000000A-page 28  2016 Microchip Technology Inc. NOTES:

 2016 Microchip Technology Inc. DS20000000A-page 29 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application me ets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting fr om such use. No licenses are conveyed, implicitly or ot herwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-1033-1 Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal meth ods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC ® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==

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