HV7022PJ-C-G

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Document overview

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Technical content

Features

• High-Voltage CMOS technology
• Symmetric row drive (reduces latent imaging in ACTFEL displays)
• Output voltage up to +230V
• Low power level shifting
• Source/sink current minimum 70 mA
• Shift register speed 4.0 MHz
• Pin-programmable shift direction

Description

HV7022 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. It is especially suited for use as a symmetric row driver in AC thin-film elec- troluminescent (ACTFEL) displays. HV7022 offers 34 output lines, a direction (DIR) pin to give CW or CCW shift register loading, output enable (OE), and polarity (POL) control. After data is entered on the falling edge of CLK, a logic high will cause the output to swing to V PP if POL is high, or to GND if POL is low. Package Type 44-Lead PLCC See Table 2-1 for pin information 1 446 40 HV7022 34-Channel Symmetric Row Driver

DS20005428A-page 2  2016 Microchip Technology Inc. Functional Block Diagram HVOUT1 OE POL DATA INPUT DATA OUT GND S/R CLK VDD VPP DIR HVOUT2 HVOUT34 Level Translator P N P N P N Level Translator Level Translator

 2016 Microchip Technology Inc. DS20005428A-page 3 HV7022

1.0 ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS† 1: Duty cycle is limited by the total power dissipated in the package. 2: For operation above 25°C ambient derate linearly to maximum operating temperature at 25 mW/°C. † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

Recommended Operating Conditions: VPP = 230V, VDD = 12V, TA = 25°C, unless otherwise noted Symbol Parameter Min Max Units Conditions DC Characteristics IDD VDD supply current - 10 mA f CLK= 4.0MHz, VDD=13.2V IPP VPP supply current - 4.0 mA One output high ( Note 1) - 100 µA All outputs low or High-Z - 750 All outputs low or High-Z (125°C) IDDQ Quiescent VDD supply current - 100 µA All V IN= GND or VDD VOH High-level output HVOUT 195 - V I O= -70mA DATA OUT 11 - V I O= -500µA VOL Low-level output HVOUT -3 0 V I O= +70mA DATA OUT - 1.0 V I O= +500µA IIH High-level logic input current - 1.0 µA V IH= 12V IIL Low-level logic input current - -1.0 µA V IL= 0V AC Characteristics fCLK Clock frequency - 4.0 MHz – tWH,tWL Pulse duration clock width high or low 125 - ns – tSUD Data set-up time before falling clock 100 - ns – tHD Data hold time after falling clock 100 - ns – tSUC Setup time clock low before VPP↑ or GND↓ 300 - ns – tSUE Setup time enable high before VPP↑ or GND↓ 300 - ns – tSUP Setup time polarity high or low before VPP↑ or GND↓ 300 - ns – tHC Hold time clock high after VPP↑ or GND↓ 500 - ns – tHE Hold time enable high after VPP↑ or GND↓ 300 - ns – tHP Hold time polarity high or low after VPP↑ or GND↓ 300 - ns –

DS20005428A-page 4  2016 Microchip Technology Inc. Note 1: The total number of ON outputs times the duty cycl e must not exceed the allowable package power dissi- pation. tDHL Delay time high to low-level output from clock - 150 ns CL= 10pF tDLH Delay time low to high-level output from clock - 200 ns CL = 10pF tTHL Transition time high to low-level serial output - 200 ns CL= 15pF tTLH Transition time low to high-level serial output - 100 ns CL= 15pF tONH High-level turn-on time HVOUT from enable - 500 ns VOH= 195V, RL= 2.0kΩ to 95V tONL Low-level turn-on time HVOUT from enable - 500 ns VOH= 130V, RL= 2.0kΩ to 30V tOFFH High-level turn-off time HVOUT from enable -1 0 0 0 n s VOH= 195V, RL= 2.0kΩ to 95V tOFFL Low-level turn-off time HVOUT from enable - 500 ns VOH= 130V, RL= 2.0kΩ to 30V SR Slew rate, VPP or GND -4 5 V / µ s One active output driving 4.7nF load to VPP or GND TEMPERATURE SPECIFICATIONS Parameter Symbol Min Typ Max Units Conditions Temperature Ranges Operating Temperature – -40 – 85 °C – Storage Temperature – -65 – 150 °C – Package Thermal Resistances Thermal Resistance, 44-Lead PLCC θja –3 7– ° C / W – ELECTRICAL CHARACTERISTICS (CONTINUED) Recommended Operating Conditions: VPP = 230V, VDD = 12V, TA = 25°C, unless otherwise noted Symbol Parameter Min Max Units Conditions

 2016 Microchip Technology Inc. DS20005428A-page 5 HV7022

1.1 Power up and Recommended

To power-up HV7022, perform the following power-up sequence: 1. Connect ground 2. Apply V DD 3. Set all inputs (Data, CLK, Enable, etc) to a known state. 4. Apply V PP (VPP should not drop below V DD or float during operation). To power-down the device, reverse the steps above. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Units VDD Logic supply voltage 10.8 13.2 V VPP High voltage supply – 230 V VIH High-level input voltage VDD = 10.8 8.1 – VVDD = 13.2 9.9 – VIL Low-level input voltage VDD = 10.8 - 2.7 VVDD = 13.2 - 3.3 fCLK Clock frequency - 4.0 MHz TA Operating free-air temperature -40 +85 °C IOD Allowable pulsed current through output diode. – ±300 mA

DS20005428A-page 6  2016 Microchip Technology Inc.

2.0 PIN DESCRIPTION

The locations of the pins are listed in Package Type. TABLE 2-1: PIN DESCRIPTION Pin # HV7022 Description 1H V OUT18/17 High voltage outputs. 2H V OUT17/18 3H V OUT16/19 4H V OUT15/20 5H V OUT14/21 6H V OUT13/22 7H V OUT12/23 8H V OUT11/24 9H V OUT10/25

10 HV OUT9/26

11 HV OUT8/27

12 HV OUT7/28

13 HV OUT6/29

14 HV OUT5/30

15 HV OUT4/31

16 HV OUT3/32

17 HV OUT2/33

18 HV OUT1/34

19 Data OUT Serial data output. Data output for cascading to the data input of the next device. 20 OE Output enable input. When OE is Low, all HV outputs are forced into a High-Z state, regardless of data in each channel. When OE is High, all HV outputs reflect data latched.

21 CLK Data shift register clock

Input are shifted into the shift register on the negative edge of the clock. 22 GND Logic and high voltage ground. 23 DIR Direction. 24 VDD Low voltage logic power rail. 25 POL Polarity. 26 DATA INPUT Serial data input. Data needs to be present before each falling edge of the clock. 27 VPP High voltage power rail. 28 NC No Connect. 29 HV OUT34/1 High voltage outputs

30 HV OUT33/2

31 HV OUT32/3

32 HV OUT31/4

33 HV OUT30/5

34 HV OUT29/6

 2016 Microchip Technology Inc. DS20005428A-page 7 HV7022 Note 1: Pin designation for DIR H/L Example: for DIR = H, pin 1 is HVOUT18 for DIR = L, pin 1 is HVOUT17

35 HV OUT28/7

High voltage outputs.

36 HV OUT27/8

37 HV OUT26/9

38 HV OUT25/10

39 HV OUT24/11

40 HV OUT23/12

41 HV OUT22/13

42 HV OUT21/14

43 HV OUT20/15

44 HV OUT19/16

TABLE 2-1: PIN DESCRIPTION Pin # HV7022 Description

DS20005428A-page 8  2016 Microchip Technology Inc.

3.0 FUNCTIONAL DESCRIPTION

Table 3-1 provides functional information about HV7022. Note 1: H = logic high level, L = logic low level, X = irrelevant, ↓ = high-to-low transition Q1 = HVOUT1, Qn = HVOUTn, etc. * = dependent on previous state and whether an O/P or S/R command occurred. FIGURE 3-1: HVOUT Characteristics FIGURE 3-2: Input and Output Equivalent Circuits TABLE 3-1: FUNCTIONAL TABLE CLK I/O Relations Inputs Outputs CLK DIR DATA POL OE Shift Reg HV OUT DATA OUT O/P HIGH X X H H H * H * O/P OFF X X L H H * HIGH-Z * O/P LOW X X H L H * L * O/P OFF X X L L H * HIGH-Z * O/P OFF X X X X L * All O/P HIGH-Z * Load S/R, set DIR ↓ LXXX Q n →Qn+1 * Q 34 ↓ HXXX Q n →Qn-1 * Q 1 No ↓ X X X X * No Change No Change I (mA) I (mA) Volts 0 20 40 60 80 100 180 140 100 0 20 40 60 80 100 VPP > 40V VDD = 12V & 14V 180 140 100 Volts (VPP - HVOUT) Temp = 25OC VDD = 12V Output N-Channel Characteristics through FET Output P-Channel Characteristics through FET Temp = 25OC VDD = 14V VDD = 10V VDD DATA INPUT GND VPP GND HVOUT Logic Inputs GND DATA OUT Logic Data Output High Voltage Outputs VDD

 2016 Microchip Technology Inc. DS20005428A-page 9 HV7022 FIGURE 3-3: Switching Waveforms 50% 50% DATA OUT CLK 50% 50% 50% tSUD tHD VIH tWL tWH 1/fCLK tTLH 90% 10% tTHL 90% 10% tDLH tDHL DATA INPUT VIH VIL VOH VOL tSUC 10% 90% tHC 50% 50% VIH VIL 90% POL 10% tSUP SUP tHP 50% 50% tSUE tHE 10% 90% 10% 90% tONL tONH tOFFL tOFFH VIH VIL OE HVOUT HVOUT High Impedence High Impedence VIL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL HVOUT P-CH HVOUT N-CH HVOUT P-CH HVOUT N-CH

DS20005428A-page 10  2016 Microchip Technology Inc.

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

Legend: XX...X Product Code or Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC ® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo. 44-lead PLCC Example XXXXXXXXX XXXXXXXXXXX YYWWNNN XXXXXXXXXXX HV7022PJ-C 1526343e3

 2016 Microchip Technology Inc. DS20005428A-page 11 HV7022 44-Lead PLCC Package Outline (PJ) .653x.653in body, .180in height (max), .050in pitch Symbol A A1 A2 b b1 D D1 E E1 e R Dimension (inches) .050 BSC .025 JEDEC Registration MS-018, Variation AC, Issue A, June, 1993. † This dimension differs from the JEDEC drawing. Drawings not to scale. .150 MAX .048/.042 x 45O .075 MAX 6 40 D E1 E Top View Horizontal Side View View B A A2 Seating Plane e b Note 1 (Index Area) .056/.042 x 45O .020max (3 Places) .020 MIN Vertical Side View View B Note 2 Base Plane R Notes: 1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEH DPROGHGPDUNLGHQWL¿HU DQHPEHGGHGPHWDOPDUNHU RU a printed indicator. 2. $FWXDOVKDSHRIWKLVIHDWXUHPD\\YDU\\

DS20005428A-page 12  2016 Microchip Technology Inc. APPENDIX A: REVISION HISTORY Revision A (February 2016)

• Updated Supertex Doc.# DSFP-HV7022C to Microchip DS20005428A.
• Changed part number from HV7022C to HV7022.
• Removed 44-Lead Quad Cerpac package.
• Minor text changes throughout.

 2016 Microchip Technology Inc. DS20005428A-page 13 HV7022 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Device: HV7022 = 34-Channel Symmetric Row Driver Package: PJ = 44-Lead PLCC Version C = Revision C Environmental G = Lead (Pb)-free/ROHS-compliant package Media Type: (blank) = 27/Tube for PJ package Examples: a) HV7022PJ-C-G 44-Lead PLCC package, 27/Tube PART NO. X Device X Environmental XX Package Options Media - - Type - X Version

DS20005428A-page 14  2016 Microchip Technology Inc. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application me ets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting fr om such use. No licenses are conveyed, implicitly or ot herwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0267-1 Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
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• There are dishonest and possibly illegal meth ods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC ® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==

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