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Document overview

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Technical content

Features

  • 96 High-Voltage Channels - Up to 80V Operating Output Voltage - 75 mA Peak Output Sink/Source Current
  • Six Parallel 16-bit Shift Registers - Clockwise and Counter-Clockwise Data Shifting via DIR Pin
  • 30 MHz Data Rate

Applications

  • Inkjet Printer Driver
  • AC Plasma Data Driver
  • 3 D P r i n t e r D r i v e r Related Devices
  • HV583: 128-Channel Serial to Parallel Converter with Push-Pull Outputs

Description

HV582 is a unipolar, 96-channel low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for applications requiring multiple high-voltage outputs with current sinking and sourcing capabilities, such as plasma displays and Inkjet printers. The device consists of six parallel 16-bit shift registers, a 96-bit latch and 96 high-voltage outputs. The shift registers operate at 30 MHz, allowing 180 MHz data rates due to the parallel arrangement. HV582 is offered in a 169-ball 10 x 10 x 1.1 mm TFBGA package. Package Type * See Section 2.0, Package Pin Configuration and Function Description. HV582 10x10x1.1 mm TFBGA* Bottom View 678910 5 4 1 23111213 H G F E D J K N M L C B A 96-Channel Serial to Parallel Converter with Push-Pull Outputs

DS20005455A-page 2  2015 Microchip Technology Inc. Block Diagram 96-Bit Latch HVOUT1 D1A CLK Level Translator 16-Bit Shift Register 16-Bit Shift Register 16-Bit Shift Register 16-Bit Shift Register 16-Bit Shift Register 16-Bit Shift Register D1B D2A D2B D3A D3B D4A D4B D5A D5B D6A D6B DIR LE RST OL POL OE OH Level Translator D16 D65 D80 D17 D32 D33 D48 D49 D64 D81 D96 LD1 LD96 Decoder Decoder VPP HVGND VPP HVGND HVOUT96 VDD HVGNDGND

 2015 Microchip Technology Inc. DS20005455A-page 3 HV582

1.0 ELECTRICAL

Absolute Maximum Rating† †Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operational listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device is ESD sensitive. Use appropriate ESD precaution. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min. Typ. Max. Units Conditions Logic Supply Voltage V DD 4.5 5.0 5.5 V High-Voltage Supply V PP 10 — 80 V High-Level Input Voltage V IH VDD –0 . 9 — V DD V Low-Level Input Voltage V IL 0— 0 . 9 V TABLE 1-1: POWER SEQUENCES Sequence Type Steps Power-Up Sequence 1. Connect Ground. 2. Apply V DD. 3. Set All Inputs (Data, CLK, etc.) to a known state. 4. Apply V PP. Power-Down Sequence Repeat the Power-Up sequence in reverse order. DC ELECTRICAL CHARACTERISTICS Electrical Specification: Unless otherwise specified, TA = TJ = +25°C, VDD = 5.0V and VPP = 80V. Parameter Symbol Min. Typ. Max. Units Conditions VPP Quiescent Supply Current I PPQ – – 100 µA VDD Quiescent Supply Current I DDQ – – 100 µA VDD Supply Current I DD –– 2 5 m A f CLK= 30 MHz, LE = low High-Level Output Voltage HV OH 70 75 – V I OUT = 75 mA, VPP = 80V Output P-Channel Body Diode HV OHD –– 8 3 V I OUT = -75 mA, VPP = 80V (Note 1) Low-Level Output Voltage HV OL –5 . 0 1 0V I OUT = -75 mA Output N-Channel Body Diode HV OLD -3.0 – – V I OUT = 75 mA (Note 1) Logic Input High Current I IH –– 1 . 0 µ A V IH = VDD 10 30 50 V IH = VDD, RST and POL only Note 1: Specification is for design guidance only.

DS20005455A-page 4  2015 Microchip Technology Inc. Logic Input Low Current I IL -1.0 – – µA V IL = -0.3V Logic Output High V OH 3.5 – – V I OUT =4m A Logic Output Low V OL –– 1 . 0 I OUT =- 4m A DC ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specification: Unless otherwise specified, TA = TJ = +25°C, VDD = 5.0V and VPP = 80V. Parameter Symbol Min. Typ. Max. Units Conditions Note 1: Specification is for design guidance only. AC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise specified TA = TJ = +25°C, VDD = 5.0V and VPP = 80V. Parameter Symbol Min. Typ. Max. Units Conditions Data Clock Frequency f CLK ——3 0 M H z Clock Pulse Width, High and Low t wCLK 16.6 — — ns Note 1 LE Pulse Width, High and Low t wLE 16.6 — — Note 2 Setup Time, DnA/B to CLK t su1 5—— Note 1 Setup Time, CLK to LE t su2 15 — — Note 1 Setup Time, LE to OL,OH tsu3 25 — — Note 1 Hold Time, CLK to DnA/B t h1 15 — — Note 1 Hold Time, LE to CLK t h2 15 — — Note 1 CLK to DnA/B (High-to-Low) t pdHL ——2 5 C L = 170 pF CLK to DnA/B (Low-to-High) t pdLH ——2 5 C L = 170 pF LE,OL,OH to HVOUTn (High-to-Low) tpHL —— 3 0 0 C L = 170 pF LE,OL,OH to HVOUTn (Low-to-High) tpLH —— 3 0 0 C L = 170 pF OE to HVOUTn (High-to-Low) t pHZL —— 1 5 0 C L = 170 pF OE to HVOUTn (Low-to-High) t pLZH —— 1 5 0 C L = 170 pF OE to HVOUTn (High-to-Low) t pHZ —— 3 0 0 OE to HVOUTn (Low-to-High) t pLZ —— 3 0 0 Rise Time HVOUTnt r —— 2 0 0 C L = 170 pF Fall Time HVOUTnt f —— 2 0 0 C L = 170 pF Note 1: Specification is obtained by characterization and is not 100% tested. 2: Specification is for design guidance only. TEMPERATURE SPECIFICATIONS Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Operating Junction Temperature T J -40 — +125 °C Storage Temperature T A -65 — +150 °C Package Thermal Resistance Thermal Resistance, 169-Ball TFBGA  JA —2 7— ° C / W

 2015 Microchip Technology Inc. DS20005455A-page 5 HV582

1.1 Logic Characteristics

TABLE 1-2: LOGIC FUNCTION TRUTH TABLE Function Inputs Outputs RST Data CLK LE OE POL OL OH Shift Reg. 1 2...96 HV Outputs 1 2...96 Data Out Store Data in Latches Transparent Mode Legend: D= D a t a H = Level High L = Level Low X = Don’t Care Z = High Impedance b= I n v e r s i o n * = Dependent of previous stage’s state before the last CLK or last LE high = Low-to-High Transition TABLE 1-3: OUTPUT SHIFT OPERATION Input Output DIR Shift Operation D1A D1B L D1 to D16 D2A D2B L D17 to D32 D3A D3B L D33 to D48 D4A D4B L D49 to D64 D5A D5B L D65 to D80 D6A D6B L D81 to D96 D1B D1A H D16 to D1 D2B D2A H D32 to D17 D3B D3A H D48 to D33 D4B D4A H D64 to D49 D5B D5A H D80 to D65 D6B D6A H D96 to D81

DS20005455A-page 6  2015 Microchip Technology Inc.

1.2 Timing Diagram

1.3 Input and Output Equivalent Circuits

50% 50% 50% 50% 50%50%50% 50%50% 50% tsu3 50% 50% 50%50% 90% 10% 90% 10% 10% 90% 90% 10% 50% 50% tpLHtpHZ tpLZ tpLZH tpHZL tpHL tr tf CLK DnA/B (input) LE OL, OH OE OE HVOUTn DnA/B (output) LE, OH, OL VIH VIL VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 50% 50% VOH VOL Logic Data Output High Voltage OutputsLogic Inputs VDD Input GND VDD Data Out GND VPP HVGND HVOUT

 2015 Microchip Technology Inc. DS20005455A-page 7 HV582

2.0 PACKAGE PIN

This section details the pin designation for the 169-Ball TFBGA package (Figure 2-1). The descriptions of the pins are listed in Table 2-1. FIGURE 2-1: 169-Ball TFBGA Package 87653 101941 2 11321 H G F E D J K N M L C B A HVOUT94 HV OUT96 NC D6B D3B POL OH D5A HV OUT3H V OUT5H V OUT6LE HVOUT93 HV OUT95 NC D5B D2B OE DIR D4A HV OUT2H V OUT4H V OUT7CLK HVOUT92 HV OUT91 NC D4B D1B OL RESET D3A HV OUT1H V OUT8H V OUT9D6A HVOUT90 HV OUT89 HV OUT88 NC V DD GND V DD VHDNG OUT10 HV OUT11 HV OUT12NC HVOUT87 HV OUT86 HV OUT85 NC HV GND HVGND HVGND HVGND NC HV OUT13 HV OUT14 HV OUT15HVGND HVOUT84 HV OUT83 HV OUT82 NC HV GND HVGND HVGND HVGND NC HV OUT16 HV OUT17 HV OUT18HVGND HVOUT81 HV OUT80 HV OUT79 NC V PP VPP VPP VPP NC HV OUT19 HV OUT20 HV OUT21VPP HVOUT78 HV OUT77 HV OUT76 NC V PP VPP VPP VPP NC HV OUT22 HV OUT23 HV OUT24VPP HVOUT75 HV OUT74 HV OUT73 NC V PP VPP NC V PP NC HV OUT25 HV OUT26 HV OUT27VPP HVOUT72 HV OUT71 HV OUT70 NC NC NC NC NC NC HV OUT28 HV OUT29 HV OUT30NC HVOUT69 HV OUT68 HV OUT61 HV OUT58 HV OUT55 HV OUT52 HV OUT49 HV OUT46 HV OUT40 HV OUT37 HV OUT31 HV OUT32HVOUT43 HVOUT67 HV OUT64 HV OUT62 HV OUT59 HV OUT56 HV OUT53 HV OUT50 HV OUT47 HV OUT41 HV OUT38 HV OUT35 HV OUT33HVOUT44 HVOUT66 HV OUT65 HV OUT63 HV OUT60 HV OUT57 HV OUT54 HV OUT51 HV OUT48 HV OUT42 HV OUT39 HV OUT36 HV OUT34HVOUT45 NC NC D2A D1A NCRST Top View

DS20005455A-page 8  2015 Microchip Technology Inc. TABLE 2-1: PIN ASSIGNMENT Pin # Symbol Pin # Symbol Pin # Symbol A1 HV OUT66 D3 HV OUT70 K6, K8 GND A2 HV OUT65 D4, D5, D6, D7, D8, D9, D10, E4, E7, E10, F4, F10, G4, G10, H4, H10, J4, J10, K4, K9, K10, L3, L10, M3, N3 NC K11 HV OUT10 A3 HV OUT63 D11 HV OUT28 K12 HV OUT11 A4 HV OUT60 D12 HV OUT29 K13 HV OUT12 A5 HV OUT57 D13 HV OUT30 L1 HV OUT92 A6 HV OUT54 E1 HV OUT75 L2 HV OUT91 A7 HV OUT51 E2 HV OUT74 L4 DB4 A8 HV OUT48 E3 HV OUT73 L5 DB1 A9 HV OUT45 E5, E6, E8, E9, F5, F6, F7, F8, F9, G5, G6, G7, G8, G9 VPP L6 OL A10 HV OUT42 E11 HV OUT25 L7 RST A11 HV OUT39 E12 HV OUT26 L8 D6A A12 HV OUT36 E13 HV OUT27 L9 D3A A13 HV OUT34 F1 HV OUT78 L11 HV OUT1 B1 HV OUT67 F2 HV OUT77 L12 HV OUT8 B2 HV OUT64 F3 HV OUT76 L13 HV OUT9 B3 HV OUT62 F11 HV OUT22 M1 HV OUT93 B4 HV OUT59 F12 HV OUT23 M2 HV OUT95 B5 HV OUT56 F13 HV OUT24 M4 DB5 B6 HV OUT53 G1 HV OUT81 M5 DB2 B7 HV OUT50 G2 HV OUT80 M6 OE B8 HV OUT47 G3 HV OUT79 M7 DIR B9 HV OUT44 G11 HV OUT19 M8 CLK B10 HV OUT41 G12 HV OUT20 M9 D4A B11 HV OUT38 G13 HV OUT21 M10 D1A B12 HV OUT35 H1 HV OUT84 M11 HV OUT2 B13 HV OUT33 H2 HV OUT83 M12 HV OUT4 C1 HV OUT69 H3 HV OUT82 M13 HV OUT7 C2 HV OUT68 H5, H6, H7, H8, H9, J5, J6, J7, J8, J9 HVGND N1 HV OUT94 C3 HV OUT61 H11 HV OUT16 N2 HV OUT96 C4 HV OUT58 H12 HV OUT17 N4 DB6 C5 HV OUT55 H13 HV OUT18 N5 D3B C6 HV OUT52 J1 HV OUT87 N6 POL C7 HV OUT49 J2 HV OUT86 N7 OH C8 HV OUT46 J3 HV OUT85 N8 LE C9 HV OUT43 J11 HV OUT13 N9 D5A C10 HV OUT40 J12 HV OUT14 N10 D2A C11 HV OUT37 J13 HV OUT15 N11 HV OUT3 C12 HV OUT31 K1 HV OUT90 N12 HV OUT5 C13 HV OUT32 K2 HV OUT89 N13 HV OUT6 D1 HV OUT72 K3 HV OUT88 D2 HV OUT71 K5, K7 V DD

 2015 Microchip Technology Inc. DS20005455A-page 9 HV582

2.1 High-Voltage Output Pins

(HVOUT1 to HVOUT96) These are the high-voltage output channels (Push-Pull).

2.2 High-Voltage Power Supply Pins

(VPP) High-voltage power supply pins for the output channels (HVOUTn).

2.3 High-Voltage Ground Pins (HV GND)

High-voltage ground pins provide the reference ground level for the high-voltage output channels.

2.4 Logic Power Supply Pins (V DD)

Logic power supply pins for the 16-bit shift registers, 96-bit latch and decoders.

2.5 Data Input/Output Pins

(D1B, D2B, D3B, D4B, D5B, D6B) Data Input/Output pins are configurable as inputs or outputs for the shift registers depending on the state of the Direction pin (DIR). When DIR is High, pins D1B to D6B are configured as inputs to the data shift registers. When DIR is Low, these pins are configured as outputs of the data shift registers.

2.6 Polarity Pin (POL)

The Polarity pin inverts the current state for all the HVOUTn channels (from High to Low or Low to High) when set High.

2.7 Output Enable Pin (OE)

The Output Enable pin controls the functionality of the high-voltage output channels. When OE is High, all HVOUTn channels are enabled and form a push-pull configuration to operate according to input data or OL , OH or POL configuration states. When OE is Low, all HV OUTn channels are forced to a high- impedance state, regardless of the data stored in the 96- bit latch or the states of the OL , OH and POL pins.

2.8 Output Low Pin (OL )

The Output Low pin sets all high-voltage output chan- nels (HV OUT1 to HV OUT96) to a Low level state (HVGND). When OL is set Low and OE is High, all the HV OUTn channels are forced to a Low-level state (HV GND), regardless of the data stored in the 96-bit latch. See Table 1-2 for more information.

2.9 Output High Pin (OH )

The Output High pin sets all high-voltage output chan- nels (HVOUT1 to HVOUT96) to a High-level state (VPP). When OH is Low while OE and OL are High, all the HVOUTn channels are forced to a High-level state (VPP), regardless of the data stored in the 96-bit latch. See Table 1-2 for more information.

2.10 Direction Pin (DIR)

The DIR pin controls the direction of the input data flow for the input registers, whether it is clockwise (DnA to DnB) or counter-clockwise (DnB to DnA). When DIR is set High, data flows from DnB to DnA. When DIR is set Low, data flows from DnA to DnB. See Table 1-3 for more information.

2.11 Logic Ground Pins (GND)

Logic ground pins provide a reference ground level for the low-voltage section of the IC, shift registers, latches and decoders.

2.12 Reset Pin (RST)

The RST pin clears shift registers and the 96-bit latch data content when it is set High. See Table 1-2 for more information.

2.13 Latch Enable Pin (LE)

The Latch Enable pin controls the data transfer from the input shift registers to the 96-bit latch and the HV OUTn channels. See Table 1-2 for more information.

2.14 Clock Input Pin (CLK)

This is the clock input pin for the 16-bit input shift registers.

2.15 Data Input/Output Pins

(D1A, D2A, D3A, D4A, D5A, D6A) The Data Input/Output pins are configurable as inputs or outputs for the shift registers depending on the state of the Direction pin (DIR). When DIR is Low, pins D1A to D6A are configured as inputs to the data shift registers. When DIR is High, pins D1A to D6A are configured as outputs of the data shift registers.

2.16 No Connection Pins (NC)

NC pins do not have any functionality on the IC. These pins should not be connected.

DS20005455A-page 10  2015 Microchip Technology Inc.

3.0 FUNCTIONAL DESCRIPTION

The HV582 is a unipolar, 96-channel low-voltage serial to high-voltage parallel converter. The device consists of six parallel 16-bit shift registers, a 96-bit latch and 96 high-voltage outputs. The six independent shift registers allow data to be updated into the 96-bit latch at six times the speed of a single register (30 MHz), providing a fast update rate for the 96 output channels. The 96-bit latch holds the data for the high-voltage output channels; whether it is a High-level or Low-level state. The flow of the input data can switch direction from clockwise (D1-6A to D1- 6B) to counter-clockwise (D1-6B to D1-6A) by con- trolling the DIR pin. A reset pin (RST) is provided to clear the contents of the latches. All channels can be set at the same time to a high-impedance state (High Z), Low-level state, High-level state, or to alter their polarity through the OE, OL , OH and POL pins, respectively. The high-output voltages (HV OUTn) can operate from 10V to 80V with a maximum current source and sink capability of 75 mA.

3.1 Application Information

HV582 is designed for applications requiring multiple high-voltage outputs with current sinking and sourcing capabilities in the range of ±75 mA. Typical applications where the HV582 is utilized are in plasma displays, Inkjet printer drivers and 3D printer drivers. FIGURE 3-1: Typical Application Block Diagram. Low Voltage Shift Register Latches Output Control High Voltage Level Translators and Push-Pull Output Buffers Microprocessor D (1-6) A CLK POL LE OE OL OH DIR Piezo Element High-Voltage Power Supply Low-Voltage Power Supply HV582 HVOUT1 HVOUT96 DIN(1-6) for Cascading the next HV582 RST D (1-6) B

 2015 Microchip Technology Inc. DS20005455A-page 11 HV582

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

Legend: XX...X Product Code or Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo. XXXXXXXXXX YYWWNNN XXXXXXXXXX XXXXXXXXXX 169-Ball TFBGA (10 x10 x1.1 mm) Example HV582GA ^^ 1533256

DS20005455A-page 12  2015 Microchip Technology Inc. B A 0.15 C 0.15 C

0.15 C A B

0.08 C (DATUM B) (DATUM A) C SEATING PLANE TOP VIEW SIDE VIEW BOTTOM VIEW NOTE 1 0.20 C 0.10 C Microchip Technology Drawing C04-377-J Rev C Sheet 1 of 2 169X For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 169-Ball Thin Fine Pitch Ball Grid Array (7G) - 10x10x1.10 mm Body [TFBGA] D D E E e 169X Øb A A2 (Complies with JEDEC Terminal Assignment recommendations)

 2015 Microchip Technology Inc. DS20005455A-page 13 HV582 Microchip Technology Drawing C04-377-J Rev C Sheet 2 of 2 Number of Terminals Overall Height Ball Diameter Overall Width Mold Cap Thickness Pitch Standoff Units Dimension Limits A b e E N

0.75 BSC

0.35 0.21 0.40 0.32 10.00 MILLIMETERS MIN NOM 169 0.45 1.10 MAX REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Terminal A1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M 169-Ball Thin Fine Pitch Ball Grid Array (7G) - 10x10x1.10 mm Body [TFBGA] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Overall Length D 10.00 0.50 0.45 0.50 (Complies with JEDEC Terminal Assignment recommendations)

DS20005455A-page 14  2015 Microchip Technology Inc. RECOMMENDED LAND PATTERN Dimension Limits Units C2Contact Pad Spacing Contact Pitch MILLIMETERS E MAX 9.00 Contact Pad Diameter (X169) b 0.35 Microchip Technology Drawing C04-2377-J Rev C NOM SILK SCREEN C1Contact Pad Spacing 9.00 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: E Øb 1 23456789 1 0 1 1 1 2 1 3 A B C D E F G H J K L M N 169-Ball Thin Fine Pitch Ball Grid Array (7G) - 10x10x1.10 mm Body [TFBGA] (Complies with JEDEC Terminal Assignment recommendations)

 2015 Microchip Technology Inc. DS200005455A-page 15 HV582 APPENDIX A: REVISION HISTORY Revision A (December 2015)

  • Original release of this document.

DS200005455A-page 16  2015 Microchip Technology Inc. NOTES:

 2015 Microchip Technology Inc. DS200005455A-page 17 HV582 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . PART NO. XX-X PackageDevice Device: HV582: Low-Voltage Serial to High-Voltage Parallel Converter with HV Outputs Package: GA-G = Thin Fine Pitch Ball Grid Array - 10 x 10 x 1.1 mm Body, 169-lead (TFBGA) Examples: a) HV582GA-G: 169-Ball 10x10 TFBGA Package

DS200005455A-page 18  2015 Microchip Technology Inc. NOTES:

 2015 Microchip Technology Inc. DS200005455A-page 19 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC 32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0105-6 Note the following details of the code protection feature on Microchip devices:

  • Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
  • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions.
  • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
  • Microchip is willing to work with the customer who is concerned about the integrity of their code.
  • Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are co mmitted to continuously improvin g the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT S YSTEM CERTIFIED BY DNV == ISO/TS 16949 ==

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