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Technical content

Features

  • 16-Channel Push-Pull Output
  • Return-To-Zero (RTZ) and High Impedance (Hi-Z) Function
  • Up to ±135V Output Voltage
  • 24 mA Minimum Source Sink Output Current
  • 250 pF Maximum Output Load
  • Current Sensor Output
  • SPI Interface with Quad-Latched 2-Bit per Channel Architecture
  • Power-On Reset Function
  • Shutdown Function
  • 59-Ball 8 x 8 mm TFBGA Package Application
  • Surface Haptic Application
  • MEMS Driver
  • Piezo Driver General Description HV53011 is a high-voltage driver solution for surface haptic applications. It consists of 16 push-pull drivers capable of ±135V output swing with Return-To-Zero (RTZ) function. Each output driver is capable of sourc- ing and sinking at least 24 mA. Each high-voltage out- put is capable of driving up to 250 pF capacitive load. A global current sensor functi on is also integrated into this device to monitor the charge and discharge cur- rents. The measured current is mapped to a low volt- age analog output with a scale factor of 3.1 V/V via a current-sensing resistor. An SPI interface is used to communicate between the microcontroller/processor and the high-voltage drivers. This interface accepts 3.3V logic I/O signals up to clock speeds of 32 MHz. Five digital LATCH control signals manage the data flow and the firing pattern. It estab- lishes the output to one of four possible states: V PP, VNN, 0V or high impedance. A proper power on and off sequence is critical to ensure the operation of the high-voltage driver. This driver requires four high-voltage power rails, VPP, VPF, VNN, VNF, and three low-voltage power rails, VCC, VSS and VLL. A companion integrated driver IC, HV53001, has a built-in power on/off sequence control circuits to maintain the proper orders. A shutdown function is available to disable the driver and set it to consume minimum power when the driver is not used. The HV53011 device is packaged in a 8 x 8 mm 59-ball TFBGA package. All high-voltage I/Os are assigned to have sufficient clearance for safety purposes. 16-Channel ±135V Push-Pull Driver with RTZ

DS20006519A-page 2  2021 Microchip Technology Inc. Typical Application Diagram SPI 32-bit LATCHD32-bit LATCHC32-bit LATCHB32-bit LATCHA SS SCK SDI SDO LATCHIN LATCHA,B,C,D 32-bit OUTPUT CONTROL REGISTER

2 HVOUT0

2 HVOUT1

2 HVOUT14

2 HVOUT15

 2021 Microchip Technology Inc. DS20006519A-page 3 HV53011 Package Types (Top View) HV53011 8 x 8 TFBGA* G A E B D J H F C L K 715 24 1 0 98631 1 * see Table 2-1. 715 24 1 0 98631 1 G A E B D J H F C L K HVOUT2HVOUT5H V OUT3 HVOUT1HVOUT4 HVOUT0 VLLHVOUT6 SSLATCHD VPPOSHDNVPP FILP VCCSDILATCHC ReservedHVGND VSSHVOUT7 SDOLATCHB VPFHVGNDHVGND VPP HVGNDSCKLATCHA HVGNDVNN HVGNDHVOUT8 HVGNDLATCHIN VNFHVGNDNC VNN HVGNDHVGNDHVGND HVGNDNC HVGNDHVOUT9 HVGNDHVGND VNNOHVGNDHVGND FILN HVOUT13HVOUT10 HV OUT12 HV OUT14HVOUT11 HVOUT15 SENSE SENSE

DS20006519A-page 4  2021 Microchip Technology Inc. Block Diagram VPPO HVOUT0 HVOUT15 SDO SCK SSSDI actuator DATA FROM MCU HV53011 HVGND SPI Interface VNNO VPPSENSE VNNSENSE Sensor Circuit High Voltage Die VPP VNN Rsense Rsense Control Logic POR VCC LATCHA LATCHIN CONTROL FROM MCU LATCHB LATCHC LATCHD LATCHIN LATCHA LATCHB LATCHC LATCHD SHDN VLL Logic voltage supply VNF VPF FILPFILN VSS VPP VPF VNF VNN VCC VSS

 2021 Microchip Technology Inc. DS20006519A-page 5 HV53011

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings † † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: OPERATING SUPPLY VOLTAGES Electrical Specifications: Unless otherwise specified: TA = TJ = +25°C. Boldface specifications apply over the TA =T J = range of -40°C to +125°C. Parameter Sym. Min. Typ. Max. Units Conditions High Positive Supply Voltage V PP 48 135 V Note 1 High Negative Supply Voltage V NN -135 -48 V Low Positive Supply Voltage (High Voltage Driver) VCC 6.0 6.5 7.0 V Low Negative Supply Voltage (High Voltage Driver) VSS -6.5 -6.0 -5.5 V Logic Input Supply Voltage (SPI Interface) VLL 3.0 3.3 3.6 V Negative Floating Supply Voltage VNF VNN + 9V - V NN+13.2V V Positive Floating Supply Voltage VPF VPP-13.2V - V PP - 9V V High-Level Input Logic Voltage V IH 0.8 VLL V Low-Level Input Logic Voltage V IL 00 . 2 V LL V Note 1: Specification is obtained by characterization and is not 100% tested.

 2021 Microchip Technology Inc. DS20006519A-page 7 HV53011 VCC Operating Supply Current I CC 0.2 mA VPP=+90V, VNN=-90V, VPF=+78V, VNF=-78V, Test pattern = Figure 1-3 with 12.5 s pulse widthVSS Operating Supply Current I SS -0.2 mA VLL Operating Supply Current I LL 25 mA VLL = +3.3V SCK = 32 MHz, SDI = 16 MHz pulse train V NF Negative Floating Supply Voltage VNF VNN+9V - VNN+13.2V V VPF Positive Floating Supply Voltage VPF VPP-13.2V - VPP-9V V HVOUT Switching Frequency f HVOUT 02 5 kHz VPP =+ 9 0 V , VNN=- 9 0 V , VPF = +78V, VNF=- 7 8 V , CL= 250 pF, Test pattern = Figure 1-3 with 12.5 μs pulse width HVOUT Output Source and Sink Current IHVOUT 24 mA VPP = +90V, VNN = -90V, VPF= +78V, VNF = -78V Return-To-Zero Slew Rate 90% to 10% (i) from VPP to 0V (ii) from VNN to 0V SR 40 100 200 V/s VPP =+ 9 0 V , VNN = -90V, VPF=+ 7 8 V , VNF = -78V, VCC=+ 6 . 5 V , VSS= -6.0V CL = 250 pF Delay Time for Output to Start Rise/Fall (from LATCHA, B, C, D to 1V HVOUT) td(ON/OFF) 100 ns VPP = +135 V, VNN = -135 V, VCC= 6.5V, VSS = -6.0V No load (Note 3) Variation of Delay Time (Channel to Channel) td 40 ns Note 3 Shutdown Pin Input Enable Voltage VIH(SHDN) 2.5 V VPPSENSE and VNNSENSE Current Sensor TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all limits apply for TA = TJ = 25°C; Boldface specifications apply over the full operating temperature range of TA =T J = -40°C to 125°C. Typical values are at +25°C. VPP = +135V, VNN = -135V, VPF = +123V, VNF = -123V, VCC = +6.5V, VSS = -6.0V, VLL = +3.3V unless otherwise specified. Parameter Sym. Min. Typ. Max. Units Conditions Note 1: Recommended operating conditions: VLL =+ 3 . 3 V , VCC = +6.5V, VSS = -6.0V, VPP = +135V, VNN = -135V all input pins = 0V unless noted. TJ =2 5 °.C 2: Design guidance only. 3: Specification is obtained by characterization and is not 100% tested.

DS20006519A-page 8  2021 Microchip Technology Inc. VPPSENSE/VNNSENSE Output Voltage Vout (VPPSENSE/ VNNSENSE) 03 . 6 V VPP = +135V, VNN = -135V, VCC = +6.5V, VSS = -6.0V, VPP - VPPO = 1.0V, VNNO - VNN = 1.0V Voltage Gain of Current Sensor AV SENSE -14% 3.1 +14% V/V VPP = +135V, VNN = -135V, VCC = +6.5V, VSS = -6.0V, VPP-VPPO and VNNO-VNN: from 0.1 to 1.0V Sensing Amplifier Output Offset V OS -280 +280 mV VPP = +135V, VNN = -135V, VCC = +6.5V, VSS = -6.0V, VPP-VPPO and VNNO-VNN: from 0.1 to 1.0V Rise Time (Time from 10% to 90% of targeted value) tR 300 ns (Note 3) VPP = +90V, VNN =- 9 0 V , VCC = +6.5V, VSS = -6.0V, CL =3p F , Test pulse: 1V, 1μs pulse width 1. V PP and VPPO 2. V NN and VNNO 740 ns VPP = +90V, VNN =- 9 0 V , VCC = +6.5V, VSS = -6.0V, CL =2 0p F , Test pulse: 1V, 1μs pulse width 1. V PP and VPPO 2. V NN and VNNO VPPSENSE/VNNSENSE Output Load RLOAD 10 M  Note 2 CLOAD 3p F Note 2 SPI Interface Digital Input Clock Frequency f CLK 32 MHz 3.3V logic input High-Level Input Logic Voltage V IH 0.8VLL V Low-Level Input Logic Voltage V IL 00 . 2 V LL V Logic I/O Pin Rise and Fall Time t R, tF 5n s C L =1 5p F (Note 3) TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all limits apply for TA = TJ = 25°C; Boldface specifications apply over the full operating temperature range of TA =T J = -40°C to 125°C. Typical values are at +25°C. VPP = +135V, VNN = -135V, VPF = +123V, VNF = -123V, VCC = +6.5V, VSS = -6.0V, VLL = +3.3V unless otherwise specified. Parameter Sym. Min. Typ. Max. Units Conditions Note 1: Recommended operating conditions: VLL =+ 3 . 3 V , VCC = +6.5V, VSS = -6.0V, VPP = +135V, VNN = -135V all input pins = 0V unless noted. TJ =2 5 °.C 2: Design guidance only. 3: Specification is obtained by characterization and is not 100% tested.

 2021 Microchip Technology Inc. DS20006519A-page 9 HV53011 Sourced by any standard I/O pin Isource 10 mA Note 2 Sunk by any standard I/O pin Isink 10 mA Note 2 SPI Quiescent Current of Low Voltage Supplies with Shut- down asserted ILLQ1 0 0 A In shutdown mode. All logic input = 0V. V(SHDN) = VLL Time to Enter and Exit Shutdown tSHDN 1m s SCK = 32 MHz and SDI = 16 MHz pulse train. Time from Chip Select and SPI data tWAIT 20 50 - ns Refer to Figure 1-1 (Note 2) Time to Transfer 128 Bits of Data tPKT 4- - s Refer to Figure 1-1 (Note 2) Time from Last Clock Pulse to LATCHIN tH(LAT) 20 50 - ns Refer to Figure 1-1 (Note 2) Digital Interface Time SPI Latch Held Low t ab 20 50 - ns Refer to Figure 1-2 (Note 2) Time Between SPI Latches t ac 10 12 - s Refer to Figure 1-2 (Note 2) Time from SPI Latch Assert to Data Valid tae -1 0 2 0 n s Refer to Figure 1-2 (Note 2) Time from SPI Latch to Data Latch tak 20 50 - ns Refer to Figure 1-2 (Note 2) Time Latch Signal Held High t gk 20 50 - ns Refer to Figure 1-2 (Note 2) Time Latch Signal Held Low t mn 20 50 - ns Refer to Figure 1-2 (Note 2) Time Between Two Data Latch Events trs 80 100 - ns Refer to Figure 1-2 (Note 2) Propagation Delay from Data Register to Output Register tkv -1 0 2 0 n s Refer to Figure 1-2 (Note 2) TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all limits apply for TA = TJ = 25°C; Boldface specifications apply over the full operating temperature range of TA =T J = -40°C to 125°C. Typical values are at +25°C. VPP = +135V, VNN = -135V, VPF = +123V, VNF = -123V, VCC = +6.5V, VSS = -6.0V, VLL = +3.3V unless otherwise specified. Parameter Sym. Min. Typ. Max. Units Conditions Note 1: Recommended operating conditions: VLL =+ 3 . 3 V , VCC = +6.5V, VSS = -6.0V, VPP = +135V, VNN = -135V all input pins = 0V unless noted. TJ =2 5 °.C 2: Design guidance only. 3: Specification is obtained by characterization and is not 100% tested.

DS20006519A-page 10  2021 Microchip Technology Inc. TEMPERATURE SPECIFICATIONS Electrical Specifications: VPP = +135V, VNN = -135V, VPF = +123V, VNF = -123V, VCC = +6.5V, VSS = -6.0V, VLL = +3.3V unless otherwise specified. Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Operating Junction Temperature Range T J -40 — +125 °C Storage Temperature Range T A -65 — +150 °C Package Thermal Resistance Thermal Resistance, 59B 8x8 TFBGA JA —3 3 . 7 —° C / W

 2021 Microchip Technology Inc. DS20006519A-page 11 HV53011

1.1 Timing Diagrams

FIGURE 1-1: SPI and LATCHIN Timing Diagram. FIGURE 1-2: LATCHA, B, C, D and High Voltage Output Timing Diagram. SS SCK SDI 128 bits valid data tPKT tWAIT LATCHIN tH(LAT) LATCHIN Register D SPI buffer bit 127:96 Register C SPI buffer bit 95:64 Register B SPI buffer bit 63:32 Register A SPI buffer bit 31:0 LATCHA LATCHB LATCHC LATCHD Output Register Reg A HV Output Reg D Reg C Reg B Reg A Reg D Reg C Reg B ab e c nm s r g k v w tac tab tae tak tgk trs tmn tkv tkw

DS20006519A-page 12  2021 Microchip Technology Inc. FIGURE 1-3: High Voltage Output Test Pattern.

 2021 Microchip Technology Inc. DS20006519A-page 13 HV53011

1.2 Typical Performance Curves

FIGURE 1-4: Typical HVOUT Output Waveform VPP=135V, VNN=-135V, Load = 100 pF . FIGURE 1-5: Typical HVOUT from 0V to 135V, Load = 100 pF FIGURE 1-6: Typical HVOUT from 135V to 0V, Load = 100 pF . FIGURE 1-7: Typical HVOUT from 0V to -135V, Load = 100 pF . FIGURE 1-8: Typical HVOUT from -135V to 0V, Load = 100 pF. FIGURE 1-9: Typ. HVOUT Rise Time Distribution, from 0V to 90V, Load = 250 pF. Note: The graphs and tables provided below are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g. outside specified power supply range) and therefore outside the warranted range.

DS20006519A-page 16  2021 Microchip Technology Inc.

2.0 PIN DESCRIPTION

The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Symbol Description E11 V PP Positive High-Voltage Supply C9 V PPO Positive High-Voltage Current Sense G11 V NN Negative High-Voltage Supply J9 V NNO Negative High-Voltage Current Sense D7 V CC Positive Low-Voltage Supply E7 V SS Negative Low-Voltage Supply C7 V LL VLL Logic Voltage J3-7, H4-7,G5-7, F6-7, E6, D3, E3 HVGND High-Voltage Ground E9 V PF Positive floating voltage supply reference to VPP level G9 V NF Negative floating voltage supply reference to VNN level J11 FILN 0.1 μF Capacitor across FILN and VNNO C11 FILP 0.1 μF Capacitor across FILP and VPPO C3 VPPSENSE Positive High-Volt age Sense Analog Output F3 VNNSENSE Negative High-Voltage Sense Analog Output G3 NC No connection (Do not connect. Keep the pin floating.) H3 NC No connection (Do not connect. Keep the pin floating.) A11 HV OUT0 High-Voltage Output 0 A9 HV OUT1 High-Voltage Output 1 A7 HV OUT2 High-Voltage Output 2 A5 HV OUT3 High-Voltage Output 3 A3 HV OUT4 High-Voltage Output 4 A1 HV OUT5 High-Voltage Output 5 C1 HV OUT6 High-Voltage Output 6 E1 HV OUT7 High-Voltage Output 7 G1 HV OUT8 High-Voltage Output 8 J1 HV OUT9 High-Voltage Output 9 L1 HV OUT10 High-Voltage Output 10 L3 HV OUT11 High-Voltage Output 11 L5 HV OUT12 High-Voltage Output 12 L7 HV OUT13 High-Voltage Output 13 L9 HV OUT14 High-Voltage Output 14 L11 HV OUT15 High-Voltage Output 15 C5 SS SPI Chip Select D5 SDI SPI Data In E5 SDO SPI Data Out (for daisy chain) F5 SCK SPI Clock G4 LATCHIN Latch SPI Data (SPI -> Latch A, B, C, D) F4 LATCHA Latch A -> Output Register E4 LATCHB Latch B -> Output Register D4 LATCHC Latch C -> Output Register C4 LATCHD Latch D -> Output Register

 2021 Microchip Technology Inc. DS20006519A-page 17 HV53011 C6 SHDN Shutdown Mode D6 Reserved Reserved Pin. Connect to Ground. TABLE 2-1: PIN FUNCTION TABLE (CONTINUED) Pin Symbol Description

DS20006519A-page 18  2021 Microchip Technology Inc.

3.0 DEVICE DESCRIPTION

3.1 Serial Peripheral Interface

The SPI interface is used to transfer data of the channel settings from the microcontroller to the high-voltage driver. The HV53011 operates as an SPI slave device and receives 128 bits of da ta from the master device (microcontroller). The HV53011 SPI interface is designed to be compatible with all Microchip 8-bit, 16-bit and 32-bit SPI data transmission formats. This SPI interface has a 128-bit shift register buffer to store 128 bits of data. The SS pin is a chip select function which is similar to the enable function to guard the clock and data input signal. The SCK contains the bus clock signal from the microcontroller or host processor. The SDI and SDO are the data input and data output pins of the SPI shift register buffer. The SDI and SDO can be used to cascade multiple HV53011 or HV53011 drivers together if only a single SPI port is available. This SPI interface is compatible with 3.3V logic input voltage with a maximum clock fre- quency of 32 MHz. The SPI shift register captures the data at the SDI input in the rising edge of the SCK clock and pushes out the data from the buffer to the SDO output in the falling edge of the SCK clock. When the SPI bus is at idle sta- tus, the SS pin stays in logic “1” and the SCK clock is expected to stay at “0”. FIGURE 3-1: SPI Signal Diagram. The bit order of the SDI data input is defined as follows. The first and second data bits represent bit 1 and bit 0 of channel 15 in register D, respectively. The third and fourth bits represent bit 1 and bit 0 of channel 14 in reg- ister D. The similar pattern is extended all the way to channel 0. Hence, there are 32 data bits to control register D to cover all sixteen channels. The next 32 data bits are arranged in the same fashion for register C. Similarly, the exact pattern repeats itself for register B and A. Since each register (A, B, C and D) contains 32 bits of data, the SPI shift register buffer is 128 bits long. Bit 1 of channel 15 in register D is defined as the MSb (Most Significant bit) and bi t 0 of channel 0 in register A as the LSb (Least Significant bit) in this SPI shift register buffer definition. FIGURE 3-2: SPI Bit Pattern Diagram. SS SCK SDI ReceiveDatatoSPIShiftRegisterBuffer SDO TransmitDatafromSPIShiftRegisterBuffer MSb LSb

 2021 Microchip Technology Inc. DS20006519A-page 19 HV53011 The following table shows the summary of the SPI shift register buffer. TABLE 3-2: SPI_SR 128-BIT BUFFER SUMMARY

3.2 Quad-Latched Two-Bit per

In the Quad-Latched 2-bit per channel architecture, each channel is controlled by a 2-bit encoding for each of the four possible states: “ 00” = (Hi-Z) high imped- ance, “01” = Pull-down to V NN, “10” = Pull-up to VPP, “11” = Driven to Ground. Since there are 16 channels on each HV53011 device, a 32-bit output control register is required. Four separate latched arrays (A, B, C, & D) hold four possible 32-bit output c onfigurations. The data is loaded from the arrays into the output control register by four separate external control signals (LATCHA , B, C, D ). When the output cont rol register is being TABLE 3-1: REGISTER LEGEND Sym Description Sym Description R Readable bit HC Cleared by Hardware only W Writable bit HS Set by Hardware only U Unimplemented bit, read as ‘0’ 1 Bit is set at Reset P Programmable bit 0 Bit is cleared at Reset S Settable bit x Bit is unknown at Reset C Clearable bit Example: R/W - 0 indicates the bit is both readable or writable, and reads ‘0’ after a Reset. Register Name Bit Range Bit 127/119/111/ 103 Bit 126/118/110/ 102 Bit 125/117/109/ 101 Bit 124/116/108/ 100 Bit 123/115/107/ Bit 122/114/106/ Bit 121/113/105/ Bit 120/112/104/ LATCHD <127:120> CH15<1:0> CH14<1:0> CH13<1:0> CH12<1:0> Register Name Bit Range Bit 95/87/79/71 Bit 94/86/78/70 Bit 93/85/77/69 Bit 92/84/76/68 Bit 91/83/75/67 Bit 90/82/74/66 Bit 89/81/73/65 Bit 88/80/72/64 LATCHC <95:88> CH15<1:0> CH14<1:0> CH13<1:0> CH12<1:0> Register Name Bit Range Bit 63/55/47/39 Bit 62/54/46/38 Bit 61/53/45/37 Bit 60/52/44/36 Bit 59/51/43/35 Bit 58/50/42/34 Bit 57/49/41/33 Bit 56/48/40/32 LATCHB Register Name Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 LATCHA

DS20006519A-page 20  2021 Microchip Technology Inc. updated using one of the latch signals, the output will go to a not driven state temporarily to avoid shoot-through. The data in these four latched arrays can be updated using the SPI shift register buffer. The 128 bits of data is first transmitted from the host processor to this device via the SPI interface. The data format has been discussed in the previous section. After this 128 bits transaction has completed, the data will stay in the SPI shift register buffer. Then the user sends an activation signal at the LATCHIN pin to initiate the transfer of the data from the SPI shift register to the four 32-bit regis- ters (A, B, C and D). When the application requires more output channels, the user can cascade more driver devices in a daisy chain configuration. The SDO pin is used to pass the data from the SPI shift register buffer to the cascaded driver IC. The SPI signal pins (SCK, SS , SDI and SDO) are used to control the data flow of th e SPI shift register buffer. The five latch control signals (LATCHIN, LATCHA , LATCHB, LATCHC and LATCHD) are used to control the data selection of the hi gh-voltage output from the four 32-bit regist ers. The SPI interface and latch functions are two independent operation blocks. To achieve some power savings when idling for a period of time, a shutdown pin is available to reduce the quiescent current draw as much as possible. FIGURE 3-3: Quad-Latched Two Bits per Channel Architecture. TABLE 3-3: 2-BIT CONTROL AND OUTPUT VOLTAGE LOGIC TABLE CONTROL BITS HVOUT OUTPUT Bit 1 Bit 0 0 0 High Impedance (Hi-Z) 0 1 Driven Low (V NN) 1 0 Driven High (V PP) 1 1 Driven to Ground (0V) SPI 128 bits shift register buffer 32-bit LATCHD32-bit LATCHC32-bit LATCHB32-bit LATCHA SS SDI SDO LATCHIN 32323232 32323232 LATCHA,B,C,D 32-bit OUTPUT CONTROL REGISTER 2HVOUT15 2HVOUT14 2HVOUT1 2HVOUT0 SHDN SWITCHES Clock ControlSCK

 2021 Microchip Technology Inc. DS20006519A-page 21 HV53011

3.3 Driver Shutdown Mode

When the shutdown (SHDN) pin is at logic “ 1”, any unnecessary circuit in the line driver will be disabled to minimize power consumption. It includes the level translator, bias current, volt age reference, driver out- put, SPI interface, and combinational logic. During shutdown, the quiescent current will be less than 100 μA. The system response time is less than 1 ms to switch between shutdown and active modes when a new signal is asserted at the shutdown pin.

3.4 Driver Power On Reset

The Power-on Reset function resets all high-voltage HVOUT output to high impedance when the device is initially powered on. It also resets and clears the SPI buffer registers, registers A, B, C and D to logic “0”.

3.5 Driver Output Current Sensing

Some system designs require a load sensing function to determine the size or any change of the capacitive load. One simple scheme is to place a series current sensing resistor on the power supply rail and measure the voltage drop across this resistor. This solution is very effective as long as the voltage drop is small enough not to affect the operation of the system. The HV53011 driver IC provides this function by which users can monitor the supply current flowing through both high-voltage positive and negative supplies. Two external current sensing resistors are connected to V PP and VNN supply rails, respectively, as high side current sensing. The voltage drop across these resistors are fed to two pin pairs, V PP-VPPO and V NN-VNNO. Since this voltage drop is referenced to the VPP and VNN sup- ply rails, it is not practical for any low-voltage ADC to measure this voltage. Henc e, two internal difference amplifiers in the driver IC convert these voltage drops to ground reference. The difference amplifier accepts maximum input volt- age of 1V. The amplifier gain of 3.1 amplifies this input and send the output to the VPPSENSE and VNN- SENSE pins. These amplifiers are designed using high-voltage and high value resistors to minimize its power consumption. These amplifier outputs are high impedance in nature, so an external high bandwidth (200 MHz) unity gain buffer is recommended. The high bandwidth is needed to capture the fast current pulse during the transition. The user selects the value of the sensing resistor to fit the system requirement. The speed of the difference amplifier is its highest pr iority because the charge or discharge current appear in a short period of time. The amplifier output accuracy is less important. Both VPPSENSE and VNNSENSE outputs have a tolerance of ±14%. FIGURE 3-4: Current Sensing Topology. TABLE 3-4: QUAD-LATCHED TWO-BIT LOGIC STATE TABLE LATCHIN LATCHA LATCHB LATCHC LATCHD Description ↓ XXXX S P I b i t [ 127:96] into Latch Register D SPI bit[95:64] into Latch Register C SPI bit[63:32] into Latch Register B SPI bit[31:0] into Latch Register A X* ↓ X X X Register A to output X* X ↓ X X Register B to output X* X X ↓ X Register C to output X * XXX ↓ Register D to output Note: * = Delay LATCHX appropriately if a register update from LATCHIN is still in progress. ↓ = Negative edge-triggered. X = Don’t care. +135V VPP HVOUT0 HVOUT1 HVOUT14 HVOUT15 VPPO Av x3.1 V+ V- Difference Amplifier VPPSENSE (Reference to GND) Sense Resistor

DS20006519A-page 22  2021 Microchip Technology Inc. TABLE 3-5: ACCEPTABLE POWER-ON SEQUENCES Steps Description 1 Connect ground. 2 Keep shutdown pin to low. 3 Set all driver inputs to low.

4 Power-on supplies in this sequence: V LL, VNN, VNF, VSS, VCC, VPF and then VPP

5 Set all inputs to a known state. TABLE 3-6: ACCEPTABLE POWER-OFF SEQUENCES Steps Description 1 Set all inputs and shutdown pin to low. 2 Power-off supplies in this sequence: V PP, VPF, VCC, VSS, VNF, VNN and then VLL.

3 Disconnect ground

 2021 Microchip Technology Inc. DS20006519A-page 23 HV53011

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

Legend: XX...X Product Code or Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part nu mber cannot be marked on one line, it will be carried over to the next line, th us limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo. 59-Ball TFBGA (8x8x1.2 mm) Example HV53011 2008256

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 2021 Microchip Technology Inc. DS20006519A-page 25 HV53011 )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWS ZZZPLFURFKLSFRPSDFNDJLQJ 1RWH %DOO7KLQ)LQH3LWFK%DOO*ULG$UUD\\ .9; [PP%RG\\>7)%*$@ 5() 5HIHUHQFH'LPHQVLRQXVXDOO\\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\\ %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV Notes: 3LQYLVXDOLQGH[IHDWXUHPD\\YDU\\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 3DFNDJHLVVDZVLQJXODWHG 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 1XPEHURI7HUPLQDOV 2YHUDOO+HLJKW 7HUPLQDO'LDPHWHU 2YHUDOO:LGWK 2YHUDOO7HUPLQDO6SDFLQJ 3LWFK 6WDQGRII 8QLWV 'LPHQVLRQ/LPLWV E H %6& 0,//,0(7(56 0,1 120 0$; 2YHUDOO/HQJWK 2YHUDOO7HUPLQDO6SDFLQJ %6& %6& 0ROG7KLFNQHVV $ %6& %6& 5() 6XEVWUDWH7KLFNQHVV $ 5()

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 2021 Microchip Technology Inc. DS20006519A-page 27 HV53011 APPENDIX A: REVISION HISTORY Revision A (March 2021)

  • Original Release of this Document.

DS20006519A-page 28  2021 Microchip Technology Inc. NOTES:

 2021 Microchip Technology Inc. DS20006519A-page 29 HV53011 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X- Media TypeDevice Device: HV53011: 16-Channel, ±135V Push-Pull Driver with RTZ Media Type: blank = 260/Tray for KVX Package T = 1000/Reel for KVX Package Temperature Range: E =-40°C to +125°C (Extended) RoHS Compliant Package: KVX = Thin Fine Pitch Ball Grid Array 59-Ball TFBGA (8 x 8 x 1.2 mm) Examples: a) HV53011-E/KVX: 16-Channel, ±135V Push-Pull Driver with RTZ. Thin Fine Pitch Ball Grid Array, 59-Ball TFBGA (8 x 8 x 1.2mm) Package, 260/Tray b) HV53011T-E/KVX:16-Channel, ±135V Push-Pull Driver with RTZ. Thin Fine Pitch Ball Grid Array, 59-Ball TFBGA (8x 8 x 1.2mm) Package, 1000/Reel X Temperature /XXX Package Tape and Reel Range Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.

DS20006519A-page 30  2021 Microchip Technology Inc. NOTES:

 2021 Microchip Technology Inc. DS20006519A-page 31 Information contained in this publication is provided for the sole purpose of designing with and using Microchip products. Infor- mation regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ens ure that your application meets with your specifications. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WAR- RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON- INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI- RECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUEN- TIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life sup- port and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectu al property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP , SimpliPHY , SmartBuffer, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2021, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-7930-7 Note the following details of the code protection feature on Microchip devices:

  • Microchip products meet the specifications c ontained in their particular Microchip Data Sheet.
  • Microchip believes that its family of products is secu re when used in the intended manner and under normal conditions.
  • There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished without violating Microchip's intellectual property rights.
  • Microchip is willing to work with any customer who is concerned about the integrity of its code.
  • Neither Microchip nor any other semic onductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

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