HV53001

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Document overview

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Technical content

Features

• 16-Channel Push-Pull Output
• Return-To-Zero (RTZ) and High-Impedance (Hi-Z) Function
• Up to ±135V Output Voltage
• 24 mA Minimum Source Sink Output Current
• 250 pF Maximum Output Load
• Current Sensor Output
• SPI Interface with Quad-Latched 2-bit per Chan- nel Architecture
• Power-on Reset Function
• DC/DC Boost Converter with Power MOSFET
• 2.7 to 5.5V Converter Input Voltage
• Short Circuit Protection
• Overtemperature Monitor
• Power ON/OFF Sequence Control
• Shutdown Function
• 105-ball 9 x 9 mm TFBGA Package Application
• Surface Haptic Application
• MEMS Driver
• Piezo Driver General Description The HV53001 device is an integrated driver solution for various applications, which consists of three main functional blocks (1) high-voltage driver, (2) SPI inter- face and (3) DC/DC boost controller with power MOSFET. The high-voltage driver block includes 16 push-pull drivers capable of ±135V output swing with Return-To- Zero (RTZ) function. Each output driver is capable of sourcing and sinking at least 24 mA. Each high-volt- age output is capable of driving up to 250 pF capaci- tive load. A global current sensor function is also integrated into this device to monitor the charge and discharge currents. The me asured current is mapped to a low-voltage analog output with a scale factor of 3.1 V/V via a current sensing resistor. The SPI interface is used to communicate between the host processor and the high-voltage drivers. This inter- face accepts a 3.3V logic I/O signal up to clock speed of 32 MHz. Five digital LATCH control signals manage the data flow and the firing pattern. It establishes the output to one of four possible states: V PP, VNN, 0V or high impedance. This IC also includes an integrated DC/DC controller with power MOSFET. The controller is used in a fly- back configuration to generat e four high-voltage rails, ±135V and ±123V, for the high-voltage driver block. The ±123V rails are created from two 12V floating sup- plies referenced to the ±135V supply rails. The converter accepts input voltage from a single 2.7V-5.5V input voltage rail. A built-in positive charge pump and a simple external negative charge pump convert the input supply to +6.5V and -6.0V supplies to power the high-voltage driver block. A proper power on and off sequence is critical to ensure the operation of the high-voltage driver. A power sequence control circuit is included for the user to con- trol the power supplies to power up or down the high- voltage driver. It is used in conjunction with the external high-voltage FET transistors. Safety features are added to the DC/DC converter. The overvoltage protection monitors both high-voltage rails to protect the driver again st an overvoltage condition. Short circuit protection detects any short circuit event at the high-voltage rails by monitoring the current flow 16-Channel, ±135V Push-Pull Driver with RTZ, Current Sensor and Built-in Boost Converter

DS20006518A-page 2  2021 Microchip Technology Inc. through the power FET transistor. When a short circuit is detected, the DC/DC c ontroller will shut down the converter and send a fault signal at the SHORT pin. An overtemperature monitor function is also added in the converter IC. It sends a fault signal at the TEMP pin when it detects a temperature over the threshold temperature. The HV53001 device is packaged in a 9x9mm 105 ball TFBGA package. All high-voltage I/Os are arranged to have sufficient clearance for safety. Typical Application Diagram CCP2 CCP1 2.7 to 12V DC/DC CONTROLLER GATE DRIVER POWER MOSFET VPP OOVPP FBNDVIN HVOUT0 HVOUT15 STDBY REF RT TON SDO SCK SS EN SDI actuator DATA FROM MCU VREF Power On Sequence Control VDD HV53001 HVGND S FBP SPI Interface VNNO VSSPUL Driver 2.7V to 5.5V VPPSENSE VNNSENSE Sensor Circuit Low Voltage High Voltage OVPN Temp Sensor VBOVP TEMP VPP VNN Rsense Control Logic POR VSSPUL VSS LATCHA LATCHIN CONTROL FROM MCU CHARGE PUMP REGULATOR Overvoltage Protection LATCHB LATCHC LATCHD LATCHIN LATCHA LATCHB LATCHC LATCHD HVGND LVGND AGND PGND SHDNSEQ[0:3] Short Circuit Protection RSHT SHTPSHTN SHORT SHTEN TRIG VLL Logic voltage supply VBFB VCC VNF VPF FILPFILN VBFB VBOVP VLDO Rsense +VE LDO -VE LDO

 2021 Microchip Technology Inc. DS20006518A-page 3 HV53001 Package Types (Top View) HV53001 9 x 9 TFBGA* G A E N B D J H F C L K M 715 1 3 24 1 0 98631 1 1 2 * see Table 2-1. 715 1 3 24 1 0 98631 1 1 2 G A E N B D J H F C L K M HVOUT2HVOUT5H V OUT3 FILPHVOUT1HVOUT4 HVOUT0 VLLHVOUT6 SS VPPOLATCHD VSSAGNDVCCSHDNVPP VSSPUL OVPPSDILATCHC FBNFBPOVPNReservedHVGND VBFB ReservedHVOUT7 SDO VPPLATCHB VLDOVBOVPNCHVGNDHVGND REF STDBYSCKLATCHA TEMPSHORTSHTENHVGNDVNN AGND SEQ3HVOUT8 HVGND VPFLATCHIN SEQ0SEQ1SEQ2HVGNDNC CSEQ SHTNHVGNDHVGND TRIG TONVINHVGNDNC CCP1N SHTPHVOUT9D VNFSR T ENVDDDS CCP1P DDSP G N D DDDS CCP2N DHVOUT10 D VNNSP G N D DDDS CCP2P HVOUT14HVOUT11 HV OUT13 VNNOHVOUT15HVOUT12 FILN SENSE SENSE

DS20006518A-page 4  2021 Microchip Technology Inc. Block Diagram SPI 32-bit LATCHD32-bit LATCHC32-bit LATCHB32-bit LATCHA SS SCK SDI SDO LATCHIN LATCHA,B,C,D 32-bit OUTPUT CONTROL REGISTER

2 HVOUT0

2 HVOUT1

2 HVOUT14

2 HVOUT15

VPP, VNN, VPF, VNF Surface Haptics Element HV53001 MCU Analog Inputs SPI GPIOs

 2021 Microchip Technology Inc. DS20006518A-page 5 HV53001

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings † † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: OPERATING SUPPLY VOLTAGES Electrical Specifications: Unless otherwise specified: TA = TJ = +25°C. Boldface specifications apply over the TA= TJ = range of -40°C to +125°C. Parameter Sym. Min. Typ. Max. Units Conditions Input Supply Voltage V IN 2.7 - 5.5 V Note 1 High Positive Supply Voltage V PP 48 135 V High Negative Supply Voltage V NN -135 -48 V Low Positive Supply Voltage (High-Voltage Driver) VCC 6.0 6.5 7.0 V Low Negative Supply Voltage (High-Voltage Driver) VSS -6.5 -6.0 -5.5 V Logic Input Supply Voltage (SPI Interface) VLL 3.0 3.3 3.6 V Negative Floating Supply Voltage V NF VNN + 9V - V NN+13.2V V Positive Floating Supply Voltage VPF VPP-13.2V - V PP - 9V V High-Level Input Logic Voltage (DC/DC Controls) VIH 2.0 VHigh-Level Input Logic Voltage (High-Voltage Driver Controls) 0.8VLL Low-Level Input Logic Voltage (DC/DC Controls) VIL 00 . 8 VLow-Level Input Logic Voltage (High-Voltage Driver Controls) 00 . 2 V LL Note 1: Specification is obtained by characterization and is not 100% tested.

DS20006518A-page 6  2021 Microchip Technology Inc. TABLE 1-2: ELECTRICAL CHARACTERISTICS Electrical Specifications: unless otherwise specified, all limits apply for TA = TJ = 25°C; Boldface specifications apply over the full operating temperature range of TA= TJ = -40°C to 125°C. Typical values are at +25°C. RT = 200k, unless otherwise specified. Parameter Sym. Min. Typ. Max. Units Conditions Low Current Standby Mode Low Threshold for EN Pin V IL 00 . 8 V High Threshold for EN Pin V IH 2.0 V IN V Pull Down Resistor at EN Pin 500 k  EN = 3.3V Quiescent Current Draw from VIN Pin IINQ5 A EN = open Charge Pump Converter Io = 10mA Output IDD Load Current I DD 10 mA Output Ripple Voltage V RIPPLE 150 mV V IN = 3.3V, Io = 10mA, CVDD = 10F (Note 3) VDD Under Voltage Lockout (Rising Edge) VDDUVLO 4.25 4.75 V (Note 2) VDD Hysteresis (Falling) 0.25 V (Note 2) Low Dropout Linear Regulator Internal LDO Output Voltage V LDO 5 . 05 . 2 55 . 5 V Clock Generation Minimum Switching Frequency f s,min 160 200 240 kHz RT = 400k  Maximum Switching Frequency fs,max 320 400 480 kHz RT = 200k  Clock Ramp Maximum V TS 3.75 V (Note 2) Clock Ramp Minimum V RST 0.2 V (Note 2) Output Voltage Reference Internally Set Reference VREF INT -3% 1.19 +3% V (Note 2) VIN = 3.7V Internal Reference to Select External Reference External Reference Range REF 0.6 2.4 V (Note 2) Output Current Feedback OCP Threshold VREF2 40 60 mV (Note 2) Ton Generation T ON Voltage Range VT ON 03 V TON Ceiling Voltage LIMIT CL 0.8VTS 3V TON Floor Range LIMIT FL 0.25VTS 3V Minimum TON Time T ON(min) 250 ns (Note 2) Internal Gain in TON Generation KTON 40 s/V (Note 2) Note 1: Recommended Operating Conditions: VIN=3.3V, VCC=+6.5V, VSS=-6.0V, VPP=+135V, VNN= -135V all input pins =0V unless noted. TJ=25°C 2: Design guidance only. 3: Specification is obtained by characterization and is not 100% tested.

 2021 Microchip Technology Inc. DS20006518A-page 7 HV53001 Over Voltage Protection OVPP Set Point OVPP R -3% 1.19 +3% VV IN = 3.7V OVPN Set Point OVPN R -3% 1.07 +3% VV IN = 3.7V OVP Hysteresis OVP HYS 0.12 V OVP Comparator Delay Time OVP DLY 50 ns 100 mV overdrive (Note 2) VSSPUL DRIVER VSSPUL Switching Frequency f PUL 500 kHz VSSPUL High Level Output V OH 5.75 V V DD = 6.5V, IO = 5 mA VSSPUL Low Level Output V OL 0.25 V V DD = 6.5V, IO = 5 mA Pull Up Resistance RON(UP) 10  VDD = 5.75V (Note 2) Pull Down Resistance RON(DN) 5  VDD = 5.75V (Note 2) Source and Sink Current IPUL 11 mA IL = 5mA at -6.0V out- put (Note 2) Temp Sensor Threshold Temperature T TH 135 °C Note 2 Power FET Drain to Source Breakdown voltage BVDSS 80 VV GS = 0V, ID = 250 . Drain to Source ON-Resis- tance RDS(ON) 60 m  VGS = 5V, VDS=12V. (Note 2) High-Voltage Driver Quiescent VPP Supply Current (Sum of Current at VPP and VPPO Pins) IPPQ 3.7 5.6 mA Quiescent VNN Supply Current (Sum of Current at VNN and VNNO Pins) INNQ -5.8 -3.8 mA Quiescent VPF Supply Current (Source) IPFQ -5.2 -3.6 mA Quiescent VNF Supply Cur- rent (Source) INFQ 3.7 5.4 mA Quiescent High-Voltage Posi- tive Supply Resultant Cur- rent, IPPQ + IPFQ IPPRQ 0.4 mA Quiescent High-Voltage Nega- tive Supply Resultant Cur- rent, INNQ + INFQ INNRQ -0.4 mA TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: unless otherwise specified, all limits apply for TA = TJ = 25°C; Boldface specifications apply over the full operating temperature range of TA= TJ = -40°C to 125°C. Typical values are at +25°C. RT = 200k, unless otherwise specified. Parameter Sym. Min. Typ. Max. Units Conditions Note 1: Recommended Operating Conditions: VIN=3.3V, VCC=+6.5V, VSS=-6.0V, VPP=+135V, VNN= -135V all input pins =0V unless noted. TJ=25°C 2: Design guidance only. 3: Specification is obtained by characterization and is not 100% tested.

DS20006518A-page 8  2021 Microchip Technology Inc. VPP Supply Current (Sum of current at VPP and VPPO pins) IPP 7.5 mA VPP=+90V, VNN=-90V, VPF=+78V, VNF=-78V, fHVOUT = 20kHz,CL= 250 pF, Running two channels. Test pattern = Figure 1-3 with 12.5s pulse width V NN Supply Current (Sum of current at VNN and VNNO pins) INN -7.5 mA High-Voltage Positive Supply Resultant Current, IPP + IPF IPPR 2 mA VPP=+90V, VNN=-90V, VPF=+78V, VNF=-78V, fHVOUT = 20kHz,CL= 250 pF, Running two channels. Test pattern = Figure 1-3 with 12.5s pulse width High-Voltage Negative Supply Resultant Current, I NN + INF INNR -2 mA VCC Operating Supply Current I CC 0.2 mA VPP=+90V, VNN=-90V, VPF=+78V, VNF=-78V, Test pattern = Figure 1-3 with 12.5s pulse widthVSS Operating Supply Current I SS -0.2 mA VLL Operating Supply Current I LL 25 mA VLL = +3.3V SCK = 32MHz, SDI =

16 MHz pulse train

VPF Operating Supply Current I PF -5.5 mA VPP=+90V, VNN=-90V, VPF=+78V, VNF=-78V, fHVOUT = 20kHz,CL= 250 pF, Running two channels. Test pattern = Figure 1-3 with 12.5 s pulse width V NF Operating Supply Current I NF 5.5 mA VNF Negative Floating Supply Voltage VNF VNN+9V - VNN+13.2V V VPF Positive Floating Supply Voltage VPF VPP-13.2V - VPP-9V V TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: unless otherwise specified, all limits apply for TA = TJ = 25°C; Boldface specifications apply over the full operating temperature range of TA= TJ = -40°C to 125°C. Typical values are at +25°C. RT = 200k, unless otherwise specified. Parameter Sym. Min. Typ. Max. Units Conditions Note 1: Recommended Operating Conditions: VIN=3.3V, VCC=+6.5V, VSS=-6.0V, VPP=+135V, VNN= -135V all input pins =0V unless noted. TJ=25°C 2: Design guidance only. 3: Specification is obtained by characterization and is not 100% tested.

 2021 Microchip Technology Inc. DS20006518A-page 9 HV53001 HVOUT Switching Frequency f HVOUT 02 5 kHz VPP=+90V, VNN=-90V, VPF=+78V, VNF=-78V, CL=250pF, Test pat- tern = Figure 1-3 with 12.5s pulse width HVOUT Output Source and Sink urrent IHVOUT 24 mA VPP=+90V, VNN=-90V, VPF=+78V, VNF=-78V Return-To-Zero Slew Rate 90% to 10% (i) from VPP to 0V (ii) from VNN to 0V SR 40 100 200 V/s VPP=+90V,VNN=-90V, VPF=+78V,VNF=-78V, VCC=+6.5V,VSS=-6.0V CL = 250 pF Delay time for output to start rise/fall (from LATCHA, B, C, D to 1V of HVOUT) td(ON/OFF) 100 ns VPP = +135 V, VNN = - 135 V, VCC= 6.5V, VSS = -6.0V No load. (Note Variation of delay time (channel to channel) td 40 ns (Note 3) Shutdown pin input enable voltage VIH(SHDN) 2.5 V VPPSENSE and VNNSENSE Current Sensor VPPSENSE/VNNSENSE Out- put Voltage V out (VPPSENSE/ VNNSENSE) 03 . 6 V VPP = +135V, VNN = - 135V, VCC = +6.5V, VSS = -6.0V Voltage Gain of Current Sen- sor AVSENSE (-40°C to 125°C) -14% 3.1 +14% V/V VPP = +135V, VNN = - 135V, VCC = +6.5V, VSS = -6.0V, VPP-VPPO and VNNO-VNN: from 0.1V to 1.0V Sensing Amplifier Output Offset VOS -280 +280 mV VPP = +135V, VNN = - 135V, VCC = +6.5V, VSS = -6.0V, VPP-VPPO and VNNO-VNN: from 0.1V to 1.0V TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: unless otherwise specified, all limits apply for TA = TJ = 25°C; Boldface specifications apply over the full operating temperature range of TA= TJ = -40°C to 125°C. Typical values are at +25°C. RT = 200k, unless otherwise specified. Parameter Sym. Min. Typ. Max. Units Conditions Note 1: Recommended Operating Conditions: VIN=3.3V, VCC=+6.5V, VSS=-6.0V, VPP=+135V, VNN= -135V all input pins =0V unless noted. TJ=25°C 2: Design guidance only. 3: Specification is obtained by characterization and is not 100% tested.

DS20006518A-page 10  2021 Microchip Technology Inc. Rise Time (Time from 10% to 90% of targeted value) tR 300 ns (Note 3) VPP = +90V, VNN = - 90V, VCC = +6.5V, VSS = -6.0V, CL=3pF, Test pulse: 1V, 1s pulse width 1. V PP and VPPO 2. V NN and VNNO Rise Time (Time from 10% to 90% of targeted value) tR 740 ns VPP = +90V, VNN = - 90V, VCC = +6.5V, VSS = -6.0V, CL=20pF, Test pulse: 1V, 1s pulse width 1. V PP and VPPO 2. V NN and VNNO VPPSENSE/VNNSENSE Output Load RLOAD 10 M  (Note 2) CLOAD 3 pF (Note 2) SPI Interface Digital Input Clock frequency f CLK 32 MHz Note: 3.3V logic input High-level input logic voltage V IH 0.8VLL V Low-level input logic voltage V IL 00 . 2 V LL V Logic I/O pin rise and fall time t R, tF 5 ns (Note 3) C L=15pF Sourced by any standard I/O pin Isource 10 mA (Note 2) Sunk by any standard I/O pin Isink 10 mA (Note 2) SPI Quiescent current of low- voltage supplies with Shut- down asserted I LLQ1 0 0 A In shutdown mode. All logic input = 0V. V (SHDN) = VLL Time to enter and exit shut- down tSHDN 1m s SCK=32MHz and SDI = 16MHz pulse train. Time from chip select and SPI data tWAIT 20 50 - ns Refer to Figure 1-1 (Note 2) Time to transfer 128-bits of data tPKT 4-- s Refer to Figure 1-1 (Note 2) Time from last clock pulse to LATCHIN tH(LAT) 20 50 - ns Refer to Figure 1-1 (Note 2) Digital Interface Time SPI latch held low t ab 20 50 - ns Refer to Figure 1-2 (Note 2) Time between SPI latches t ac 10 12 - s Refer to Figure 1-2 (Note 2) TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: unless otherwise specified, all limits apply for TA = TJ = 25°C; Boldface specifications apply over the full operating temperature range of TA= TJ = -40°C to 125°C. Typical values are at +25°C. RT = 200k, unless otherwise specified. Parameter Sym. Min. Typ. Max. Units Conditions Note 1: Recommended Operating Conditions: VIN=3.3V, VCC=+6.5V, VSS=-6.0V, VPP=+135V, VNN= -135V all input pins =0V unless noted. TJ=25°C 2: Design guidance only. 3: Specification is obtained by characterization and is not 100% tested.

 2021 Microchip Technology Inc. DS20006518A-page 11 HV53001 Time from SPI latch assert to data valid tae -1 0 2 0 n s Refer to Figure 1-2 (Note 2) Time from SPI latch to data latch tak 20 50 - ns Refer to Figure 1-2 (Note 2) Time latch signal held high t gk 20 50 - ns Refer to Figure 1-2 (Note 2) Time latch signal held low t mn 20 50 - ns Refer to Figure 1-2 (Note 2) Time between two data latch events trs 80 100 - ns Refer to Figure 1-2 (Note 2) Propagation delay from data register to output register tkv -1 0 2 0 n s Refer to Figure 1-2 (Note 2) TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: unless otherwise specified, all limits apply for TA = TJ = 25°C; Boldface specifications apply over the full operating temperature range of TA= TJ = -40°C to 125°C. Typical values are at +25°C. RT = 200k, unless otherwise specified. Parameter Sym. Min. Typ. Max. Units Conditions Note 1: Recommended Operating Conditions: VIN=3.3V, VCC=+6.5V, VSS=-6.0V, VPP=+135V, VNN= -135V all input pins =0V unless noted. TJ=25°C 2: Design guidance only. 3: Specification is obtained by characterization and is not 100% tested.

DS20006518A-page 12  2021 Microchip Technology Inc.

1.1 Timing Diagrams

FIGURE 1-1: SPI and LATCHIN Timing Diagram TEMPERATURE SPECIFICATIONS Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Operating Junction Temperature Range T J -40 — +125 °C Storage Temperature Range T A -65 — +150 °C Package Thermal Resistance Thermal Resistance, 105B-9x9 TFBGA JA — 38.1 — °C/W

DS20006518A-page 14  2021 Microchip Technology Inc.

1.2 Typical Performance Curves

FIGURE 1-4: Typical HVOUT output waveform VPP=135V VNN=-135V, Load = 100pF FIGURE 1-5: Typical HVOUT from 135V to 0V, Load = 100pF FIGURE 1-6: Typical HVOUT from -135V to 0V, Load = 100pF FIGURE 1-7: Typical HVOUT from 0V to 135V, Load = 100pF FIGURE 1-8: Typical HVOUT from 0V to - 135V, Load = 100pF FIGURE 1-9: Typ. HVOUT Rise Time Distribution, HVOUT from 0V to 90V, Load = 250pF Note: The graphs and tables provided below are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g. outside specified power supply range) and therefore outside the warranted range.

DS20006518A-page 18  2021 Microchip Technology Inc.

2.0 PIN DESCRIPTION

The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Symbol Description E13 V PP Positive High-Voltage Supply C13 V PPO Positive High-Voltage Current Sense L13 V NN Negative High-Voltage Supply N13 V NNO Negative High-Voltage Current Sense C8 V CC Positive Low-Voltage Supply C10 V SS Negative Low-Voltage Supply C7 V LL VLL Logic Voltage D3, E3, H4-6, G5-6.E6, F6 HVGND High-Voltage Ground G13 V PF Positive floating voltage supply reference to VPP level J13 V NF Negative floating voltage supply reference to VNN level N11 FILN 0.1uF cap across FILN and VNNO A13 FILP 0.1uF cap across FILP and VPPO C3 VPPSENSE Positive High-Voltage Sense Analog Output F3 VNNSENSE Negative High-Voltage Sense Analog Output E10 VLDO LDO output pin G3 NC No Connection. (Do not connect. Keep the pin floating) H3 NC No Connection. (Do not connect. Keep the pin floating) A11 HV OUT0 High-Voltage Output 0 A9 HV OUT1 High-Voltage Output 1 A7 HV OUT2 High-Voltage Output 2 A5 HV OUT3 High-Voltage Output 3 A3 HV OUT4 High-Voltage Output 4 A1 HV OUT5 High-Voltage Output 5 C1 HV OUT6 High-Voltage Output 6 E1 HV OUT7 High-Voltage Output 7 G1 HV OUT8 High-Voltage Output 8 J1 HV OUT9 High-Voltage Output 9 L1 HV OUT10 High-Voltage Output 10 N1 HV OUT11 High-Voltage Output 11 N3 HV OUT12 High-Voltage Output 12 N5 HV OUT13 High-Voltage Output 13 N7 HV OUT14 High-Voltage Output 14 N9 HV OUT15 High-Voltage Output 15 C5 SS SPI Chip Select D5 SDI SPI Data In

 2021 Microchip Technology Inc. DS20006518A-page 19 HV53001 E5 SDO SPI Data Out (for daisy chain) F5 SCK SPI Clock G4 LATCHIN Latch SPI Data (SPI -> Latch A, B, C, D) F4 LATCHA Latch A -> Output Register E4 LATCHB Latch B -> Output Register D4 LATCHC Latch C -> Output Register C4 LATCHD Latch D -> Output Register H8 V IN Input Voltage J8 V DD Positive Low-Voltage Supply K10,L10 PGND Power Ground C9,F11 AGND Analog Ground K11 CCP2N Charge Pump 2 NEG L11 CCP2P Charge Pump 2 POS H11 CCP1N Charge Pump 1 NEG J11 CCP1P Charge Pump 1 POS H9 T ON TON pin J10 RT RT pin D11 VBFB FB Bias E9 VBOVP OVP Bias E11 REF Controller Voltage Reference C11 VSSPUL VSS Pulse Train F10 TEMP Temp Sensor Output F9 SHORT Short circuit indicator F8 SHTEN Short circuit protection enable C6 SHDN Shutdown Mode F7 STDBY Standby Mode J9 EN DC/DC Enable G7 SEQ3 Power Sequence Channel 3 G8 SEQ2 Power Sequence Channel 2 G9 SEQ1 Power Sequence Channel 1 G10 SEQ0 Power Sequence Channel 0 H10 TRIG Power ON/OFF Sequence Trigger G11 CSEQ Sequence timer. External capacitor to ground J7 SHTP Short Sense POS H7 SHTN Short Sense NEG D7 OVPP Over-voltage POS D8 OVPN Over-voltage NEG D9 FBP Feedback POS D10 FBN Feedback NEG TABLE 2-1: PIN FUNCTION TABLE (CONTINUED) Pin Symbol Description

DS20006518A-page 20  2021 Microchip Technology Inc. E8 NC No Connection (Do not connect. Keep the pin floating) E7 Reserved Reserved pin. Connect to Ground. D6 Reserved Reserved pin. Connect to Ground. J3-4, K3-4,L3-4 S Source of Power FET J5-6, K5-9,L5-9 D Drain of Power FET TABLE 2-1: PIN FUNCTION TABLE (CONTINUED) Pin Symbol Description

 2021 Microchip Technology Inc. DS20006518A-page 21 HV53001

3.0 DEVICE DESCRIPTION

3.1 Serial Peripheral Interface

The SPI interface is used to transfer data of the chan- nel settings from the host controller to the high-voltage driver. The HV53001 operates as an SPI slave device and receives 128 bits of data from the master device (host controller). The HV53001 SPI interface is designed to be compatible with all Microchip 8-bit, 16- bit and 32-bit SPI data transmission formats. This SPI interface has a 128-bit shift register buffer to store 128 bits of data. The SS pin is a chip select function which is similar to the enable function to guard the clock and data input signal. The SCK contains the bus clock signal from the host processor. The SDI and SDO are the data input and data output pins of the SPI shift register buffer. SDI and SDO can be used to cascade multiple HV53001 or HV53011 drivers together if only a single SPI port is available. This SPI interface is compatible with 3.3V logic input volt age with its maximum clock frequency of 32 MHz. The SPI shift register captures the data at the SDI input in the rising edge of the SCK clock and pushes out the data from the buffer to the SDO output in the falling edge of the SCK clock. When the SPI bus is at idle status, the SS pin stays in logic “ 1” and the SCK clock is expected to stay at “0”. FIGURE 3-1: SPI Signal Diagram. The bit order of the SDI data input is defined in the following. The first and second data bits represent bit 1 and bit 0 of channel 15 in register D, respectively. The third and fourth bits represent bit 1 and bit 0 of channel 14 in register D. This pattern is extended all the way to channel 0. Hence, there are 32 data bits to control register D to cover all sixteen channels. The next 32 data bits are arranged in the same fashion for register C. Similarly, the exact pattern repeats itself for register B and A. Since each register (A, B, C and D) contains 32 bits of data, the SPI shift register buffer is 128 bits long. Bit 1 of channel 15 in register D is defined as the MSb (Most Significant bit) and bit 0 of channel 0 in register A as the LSb (Least Significa nt bit) in this SPI shift register buffer definition. FIGURE 3-2: SPI Bit Pattern Diagram. SDI 128 clock cycle MSb… Data < D_CH15[1], D_CH15[0], D_CH14[1], ……. A_CH0[1], A_CH0[0] > … LSb For example, D_CH15[1] = Setting of Register D, Channel 15, Bit 1

DS20006518A-page 22  2021 Microchip Technology Inc. The following table shows the summary of the SPI shift register buffer. TABLE 3-1: REGISTER LEGEND TABLE 3-2: SPI_SR 128-BIT BUFFER SUMMARY

3.2 Quad-Latched Two-Bit per

In the Quad-Latched 2-bit per channel architecture, each channel is controlled by a 2-bit encoding for each of the four possible states: “ 00” = (Hi-Z) high imped- ance, “01” = pull-down to VNN, “10” = pull-up to VPP, “11” = driven to ground. Since there are 16 channels on each HV53001 device, a 32-bit output control register is required. Four separate latched arrays (A, B, C and D) hold four possible 32-bit output c onfigurations. The data is loaded from the arrays into the output control register by four separate external control signals (LATCHA, B, C, D ). When the output cont rol register is being updated using one of the latch signals, the output will go to a not driven state temporarily to avoid shoot- through. The data in these four latc hed arrays can be updated by the SPI shift register buffer. The 128 bits of data is first transmitted from the host process to this device via the SPI interface. The data format has been dis- cussed in the previous section. After the 128 bits transaction completes, the data will stay in the SPI shift register buffer. The user then sends an activation signal at the LATCHIN pin to initiate the transfer of the data from the SPI shift register to the four 32-bit registers (A, B, C and D). Sym Description Sym Description R Readable bit HC Cleared by Hardware only W Writable bit HS Set by Hardware only U Unimplemented bit, read as ‘0’ 1 Bit is set at Reset P Programmable bit 0 Bit is cleared at Reset S Settable bit x Bit is unknown at Reset C Clearable bit Example: R/W - 0 indicates the bit is both readable or writable, and reads ‘0’ after a Reset. Register Name Bit Range Bit 127/119/111/ 103 Bit 126/118/110/ 102 Bit 125/117/109/ 101 Bit 124/116/108/ 100 Bit 123/115/107/ Bit 122/114/106/ Bit 121/113/105/ Bit 120/112/104/ LATCHD <127:120> CH15<1:0> CH14<1:0> CH13<1:0> CH12<1:0> Register Name Bit Range Bit 95/87/79/71 Bit 94/86/78/70 Bit 93/85/77/69 Bit 92/84/76/68 Bit 91/83/75/67 Bit 90/82/74/66 Bit 89/81/73/65 Bit 88/80/72/64 LATCHC <95:88> CH15<1:0> CH14<1:0> CH13<1:0> CH12<1:0> Register Name Bit Range Bit 63/55/47/39 Bit 62/54/46/38 Bit 61/53/45/37 Bit 60/52/44/36 Bit 59/51/43/35 Bit 58/50/42/34 Bit 57/49/41/33 Bit 56/48/40/32 LATCHB Register Name Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 LATCHA

 2021 Microchip Technology Inc. DS20006518A-page 23 HV53001 When the application requires more output channels, the user can cascade more driver devices in a daisy chain configuration. The SDO pin is used to pass the data from the SPI shift register buffer to the cascaded driver. The SPI signal pins (SCK, SS , SDI and SDO) are used to control the data flow of th e SPI shift register buffer. The five latch control signals (LATCHIN , LATCHA , LATCHB, LATCHC and LATCHD) are used to control the data selection of the hi gh-voltage output from the four 32-bit registers. Th e SPI interface and latch functions are two independent operation blocks. To achieve some power savings when idling for a period of time, a shutdown pin is available to reduce the quiescent current draw as much as possible. TABLE 3-1: 2-BIT CONTROL AND OUTPUT VOLTAGE LOGIC TABLE FIGURE 3-3: Quad-Latched Two-Bit per Channel Architecture. TABLE 3-3: QUAD-LATCHED TWO-BIT LOGIC STATE TABLE CONTROL BITS HVOUT OUTPUT Bit 1 Bit 0 0 0 High impedance (Hi-Z) 0 1 Driven Low (V NN) 1 0 Driven High (V PP) 1 1 Driven to Ground (0V) LATCHIN LATCHA LATCHB LATCHC LATCHD Description ↓ XXXXS P I b i t [ 1 2 7 : 9 6 ] i n t o L a t c h R e g i s t e r D SPI bit[95:64] into Latch Register C SPI bit[63:32] into Latch Register B SPI bit[31:0] into Latch Register A X* ↓ X X X Register A to output X* X ↓ X X Register B to output X* X X ↓ X Register C to output X * XXX ↓ Register D to output Note: * = LATCHX should be delayed appropriately if a register update from LATCHIN is still in progress. ↓ = Negative edge-triggered X = Don’t care SPI 128 bits shift register buffer 32-bit LATCHD32-bit LATCHC32-bit LATCHB32-bit LATCHA SS SDI SDO LATCHIN 32323232 32323232 LATCHA,B,C,D 32-bit OUTPUT CONTROL REGISTER 2HVOUT15 2HVOUT14 2HVOUT1 2HVOUT0 SHDN SWITCHES Clock ControlSCK

DS20006518A-page 24  2021 Microchip Technology Inc.

3.3 Driver Shutdown Mode

When the shutdown (SHDN) pin is at logic “ 1”, any unnecessary circuit in the line driver is disabled to min- imize the power consumption. It includes the level translator, bias current, volt age reference, driver out- put, SPI interface and combinational logic. During shutdown, the I LL quiescent current is less than 100 A. The system response time is less than 1 ms to switch between shutdown and active states when a new signal is asserted at the shutdown pin.

3.4 Driver Power On Reset

The Power-on Reset function resets all high-voltage HVOUT output to high impedance when the device is initially powered on. It also resets and clears the SPI buffer registers, registers A, B, C and D, to logic “0”.

3.5 Positive Charge Pump Regulator

The device is targeted to operate with a standard bat- tery voltage range of 2.7V to 5.5V. An internal 3X charge pump converter is integrated to generate a reg- ulated output at high-voltage level. This regulated out- put supply rail powers the gate driver to drive the power MOSFET transistor. It is recommended to use 1 F 16V X7R 0603 ceramic capacitors for the two CCP capacitors and a 10 F 25V X5R 0805 ceramic capacitor for the output storage capacitor. Note: Please consider the operating temperature for component selection. FIGURE 3-4: Positive Charge Pump Converter Conceptual Diagram FIGURE 3-5: HV53001 Positive Charge Pump Connections

3.6 Negative Charge Pump

A continuous pulse train is created at the VSSPUL output and is used in conjunction with a few external components to create a negative charge pump circuit. The pulse train is a 0 to 6.5V square wave with a fixed oscillation frequency. This -6.0V negative low supply voltage is generated at the output of the external circu- ity and is capable of supplying a minimum of 5 mA. This negative supply provides enough power to operate the high-voltage driver device. It is recommended to use 10 F 25V X5R 0805 ceramic capacitors and B0530WS 400 mV 500 mA 30V Schottky diodes for this circuit. Note: Please consider the operating temperature for component selection. FIGURE 3-6: Negative Charge Pump Converter

3.7 Standby Mode

Standby mode is used to guard the PWM pulses from the DC/DC controller to the power FET. It momentarily disables the gate driver of the power FET to minimize the noise level so that t he output current sensor can measure the output current precisely. While the device is in Standby mode, all ot her circuits are expected to be in their operating condition.

3.8 Enable Function

The enable function is used to switch the DC/DC con- troller on/off completely. When it is set to Off mode, all internal circuits of the DC/DC converter are turned off and minimum current is drawn. When the DC/DC con- verter is disabled, the boost converter, charge pump converter and linear regulator shut off. The SHDN and EN are two separate controls. SHDN is for the high-voltage driver, and EN is for the DC/DC converter. +6.5V to high voltage driver HV53001 Positive Charge Pump Converter CCP1+/- CCP2+/- 2.7 to 5.5V VIN VDD

 2021 Microchip Technology Inc. DS20006518A-page 25 HV53001

3.9 Power-On/Off Sequence Control

The HV53001 DC/DC converter generates multiple rails to power the high-voltage driver IC. The power-on sequence is important to the high-voltage IC because any incorrect power-on/off sequence may cause damage to the high-voltage driver IC. A sequence control block is included in this device to avoid an incorrect sequence caused by user error which could damage the driver IC. When a single pulse is asserted at the TRIG pin, the four sequence control outputs generate a logic “ 1” in sequential order. First, a logic “1” will appear in SEQ0, and then in SEQ1, SEQ2 and SEQ3. When a second pulse is asserted at the TRIG pin, a logic “ 0” appears in SEQ3, SEQ2, SEQ1 and SEQ0 sequentially in reverse order. The timing between each is controlled by an external capacitor connected at the CSEQ pin. The sequence switch time period is calculated in the following equation. Tseq = 2 x ln(2) x R x CSEQ where R = 100 k The four sequence logic output signals, SEQ[3:0], can be used to control the en able function of the power module or external analog power switches to control the supply voltage rails. FIGURE 3-7: Power-On/Off Sequence Control FIGURE 3-8: Sequence On/Off Control State Diagram. FIGURE 3-9: Example of Power Switch Circuit TABLE 3-2: ACCEPTABLE POWER-ON SEQUENCES SEQX +135V VPP SEQY -135V VNN Logic voltage supply Steps Description 1 Connect ground. 2 Keep shutdown pin to low. 3 Set all driver inputs to low. 4A p p l y V IN. 5 Set all converter inputs to a known state.

6 The power-on sequence will enable supplies in this sequence: V LL, VNN, VNF, VSS, VCC, VPF and

VPP. 7 Set all inputs to a known state.

DS20006518A-page 26  2021 Microchip Technology Inc. TABLE 3-3: ACCEPTABLE POWER-OFF SEQUENCES

3.10 Built-in DC/DC Converter

A hysteretic step-up DC/DC converter is integrated in this driver IC to generate two high-voltage rails, one positive and one negative. In normal operation, this converter operates at a fixed duty cycle and frequency. The controller monitors both positive and negative voltage rails alternately to regulate the output voltage. The positive supply feedback input is a typical DC/DC feedback which monitors the feedback voltage from a resistor divider referenced to ground. When the sens- ing voltage is higher than the internal reference volt- age, it deactivates the pulse in the next cycle. When the sensing voltage is lower, it activates the pulse. For the negative supply feedback input, the controller provides a low DC bias vo ltage to map the feedback voltage above ground because the controller is pow- ered by a low-voltage positive power rail. Hence, the negative supply feedback voltage is referenced to the bias voltage VBFB pin via the resistor divider network. The negative supply feedback path works differently from the positive supply feedback path since it senses the negative voltage. When the sensing voltage is higher than the internal refe rence voltage, it activates the pulse in the next cycle. When the sensing voltage is lower, it deactivates the pulse. Based on the operation described above, the controller basically regulates the mid-point of the V PP and V NN voltage rails. As long as the two transformers are closely matched, the two high-voltage outputs can be coupled within a few percentage of each other. For matching the transformers, their absolute values are not important. The important factor is the difference between the two transformers. Since both transformers are built the same way, their secondary effects are very similar. The major factor is their primary parameter, magnetizing inductance. In addition to the two extreme high-voltage rails, the driver requires two floating voltage rails. Both floating supplies are referenced to one of the extreme high-volt- age outputs. These two floating supply rails are created using the multi-winding transformer and two 12V regu- lators. The positive voltage rail requires a negative 12V regulator referenced to V PP. The negative voltage rail uses a positive 12V regulator reference to VNN. The following schematic diagram shows how this DC/DC converter can be configured. VPP, VPF, VNN and VNF represent all output rails. VIN is the main supply rail to the DC/DC converter. Steps Description 1 Set all inputs and shutdown pin to low.

2 The power-off sequence will disable supplies in this sequence: V PP, VPF, VCC, VSS, VNF, VNN and

VLL. 3 Disconnect V IN.

4 Disconnect ground

 2021 Microchip Technology Inc. DS20006518A-page 27 HV53001 FIGURE 3-10: HV53001 DC-DC converter configuration

3.10.1 T ON SETTING

The TON pin is used to set the duty cycle of the DC-DC converter. An internal ramp generator in the DC-DC converter creates a ramp between 0 and 3.75V. A low- to-high transition starts at 0V. When this ramp voltage reaches the same voltage level presented at the T ON pin, it triggers the internal comparator and sets the pulse high-to-low transition. The voltage present at the TON pin sets the duty cycle of the pulses. An internal lower bound and upper bound of the duty cycle are set to avoid any malfunction. The user can select any TON voltage between 0 and 3V. For example, the duty cycle is set to 80% for VTON = 3V.

3.10.2 CONVERTER SWITCHING

The converter switching frequency is set by an external resistor RT. The frequency is set by the following equa- tion. fSW = 1/ (C * RT) where C = 12pF

3.10.3 OVERVOLTAGE PROTECTION

Overvoltage protection is to monitor the output voltage of the boost converter. If the output voltage of the DC/DC converter reaches above the threshold volt- age, it will pause the DC/DC converter operation for safety purpose. The DC/DC stays in Standby mode until the monitored voltage drops below the threshold. Then, the DC/DC controller exits Standby mode and resumes normal operation. The overvoltage protection is intended to guard any momentarily overvoltage condition for a short period of time and does not require any user interaction. The threshold voltage can be set by the external resistor network. The OVPP and OVPN pins are used to monitor the feedback voltage from the V PP and V NN supplies via two sets of voltage divider networks. The sampled voltage from VPP and VNN are compared with the inter- VIN POWER MOSFET FBN D S FBP VPP VNN SHTP SHTN VBFB VNF VPF VIN Vi Neg LDO Vo GND Vi Pos LDO Vo GND VPP VNN Coilcraft WA8775-BE Coilcraft WA8775-BE HV53001 DC/DC converter 4.49 0.58 4.49 0.58 DutyCycle VTON

DS20006518A-page 28  2021 Microchip Technology Inc. nal reference voltage. If the sampled V PP or VNN volt- age is above the threshold, the controller will turn off the pulses until V PP and VNN drop below the threshold.

3.10.4 SHORT CIRCUIT PROTECTION

A short circuit at the flyback transformer output may cause damage to the power supply circuit and gener- ate a lot of heat. This may create a hazardous situa- tion for the end user. A short circuit protection scheme is implemented in the DC/DC controller by monitoring the current of the power FET transistor. This DC/DC controller is running in Discontinuous Conduction mode (DCM). When a short circuit situa- tion happens, the converter goes into Continuous Conduction mode (CCM). This causes the FET current at turn on to be non-zero. The controller detects this and shuts down the pulse to the power FET and sets a logic '1' at the SHORT pin. The user toggles the EN signal to restart the converter. The short circuit protection function can be bypassed by inserting a logic “ 0” to the short circuit enable pin (SHTEN).

3.11 Driver Output Current Sensing

Some system designs require a load sensing function to determine the size or change of the capacitive load. One simple scheme is to place a series current sensing resistor on the power supply rail and measure the volt- age drop across this resistor. This solution is very effec- tive if the voltage drop is small enough not to affect the operation of the system. The HV53001 driver IC provides this function and the user can monitor the supply current flowing through both high-voltage positive and negative supplies. Two external current sensing resistors are connected to the V PP and V NN supply rails, respectively, as high side current sensing. The voltage drop across these resis- tors are connected to two pin pairs, V PP-VPPO and VNN- VNNO. Since these voltage drops are referenced to VPP and VNN supply rails, it is not practical for a low-voltage ADC to measure these voltages. Hence, two internal difference amplifiers in the driver IC convert these volt- age drops to near ground potential. The difference amplifier accepts a maximum input volt- age of 1V. The amplifier gain of 3.1 amplifies this input and sends the output to th e VPPSENSE and VNN- SENSE pins. These amplifiers are designed using high-voltage and high value resistors to minimize its power consumption. These amplifier outputs are high impedance in nature, so an external high bandwidth (200MHz) unity gain buffer is highly recommended. The high bandwidth is needed to capture the fast current pulse during the transition. The user selects the value of the sensing resistor to fit the system requirement. The speed of difference ampli- fier is a high priority parameter because the charge or discharge current appears for a short period of time. The amplifier output accuracy is less important. Both VPPSENSE and VNNSENSE outputs have a tolerance of ±14%. FIGURE 3-11: Current Sensing Topology. +135V VPP HVOUT0 HVOUT1 HVOUT14 HVOUT15 VPPO Av x3.1 V+ V- Difference Amplifier VPPSENSE (Reference to GND) Sense Resistor

 2021 Microchip Technology Inc. DS20006518A-page 29 HV53001

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

Legend: XX...X Product Code or Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part nu mber cannot be marked on one line, it will be carried over to the next line, th us limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo. 105-Ball TFBGA(9x9x1.2 mm) Example HV53001 1508256

DS20006518A-page 30  2021 Microchip Technology Inc. '$780$ 6($7,1* 3/$1( 127( 7239,(: 6,'(9,(: %277209,(: 127( 0LFURFKLS7HFKQRORJ\\'UDZLQJ& 5HY$6KHHWRI H )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWS ZZZPLFURFKLSFRPSDFNDJLQJ 1RWH %DOO7KLQ)LQH3LWFK%DOO*ULG$UUD\\ .:; PP%RG\\>7)%*$@ H '$780%

 2021 Microchip Technology Inc. DS20006518A-page 31 HV53001 0LFURFKLS7HFKQRORJ\\'UDZLQJ& 5HY$6KHHWRI )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWS ZZZPLFURFKLSFRPSDFNDJLQJ 1RWH %DOO7KLQ)LQH3LWFK%DOO*ULG$UUD\\ .:; PP%RG\\>7)%*$@ 5() 5HIHUHQFH'LPHQVLRQXVXDOO\\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\\ %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV Notes: 3LQYLVXDOLQGH[IHDWXUHPD\\YDU\\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 3DFNDJHLVVDZVLQJXODWHG 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 1XPEHURI7HUPLQDOV 2YHUDOO+HLJKW 7HUPLQDO'LDPHWHU 2YHUDOO:LGWK 2YHUDOO7HUPLQDO6SDFLQJ 3LWFK 6WDQGRII 8QLWV 'LPHQVLRQ/LPLWV E H %6& 0,//,0(7(56 0,1 120 0$; 2YHUDOO/HQJWK 2YHUDOO7HUPLQDO6SDFLQJ %6& %6& 0ROG7KLFNQHVV $ %6& %6& 5() 6XEVWUDWH7KLFNQHVV $ 5()

DS20006518A-page 32  2021 Microchip Technology Inc. %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 1RWHV 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 )RUEHVWVROGHULQJUHVXOWVWKHUPDOYLDVLIXVHGVKRXOGEHILOOHGRUWHQWHGWRDYRLGVROGHUORVVGXULQJ UHIORZSURFHVV )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWS ZZZPLFURFKLSFRPSDFNDJLQJ 1RWH 0LFURFKLS7HFKQRORJ\\'UDZLQJ& 5HY$ \\> @ 6,/.6&5((1 'LPHQVLRQ/LPLWV 8QLWV &2YHUDOO&RQWDFW3DG6SDFLQJ &RQWDFW3LWFK 0,//,0(7(56 %6& 0,1 0$; &RQWDFW3DG:LGWK 120 &2YHUDOO&RQWDFW3DG6SDFLQJ &RQWDFW3DGWR&RQWDFW3DG *

 2021 Microchip Technology Inc. DS20006518A-page 33 HV53001 NOTES:

DS20006518A-page 34  2021 Microchip Technology Inc.

 2021 Microchip Technology Inc. DS20006518A-page 35 HV53001 APPENDIX A: REVISION HISTORY Revision A (March 2021)

• Original Release of this Document.

DS20006518A-page 36  2021 Microchip Technology Inc. NOTES:

 2021 Microchip Technology Inc. DS20006518A-page 37 HV53001 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Device: HV53001: 16-Channel, +/-135V Push-Pull Driver with RTZ, Current Sensor and Built-in Boost Converter Media Type: blank = 260/Tray for KWX Package T = 1000/Reel for KWX Package Temperature Range: E =-40°C to +125°C (Extended) RoHS Compliant Package: KWX =Thin Fine Pitch Ball Grid Array 105-Ball TFBGA (9 x 9 x 1.2 mm) Examples: a) HV53001-E/KWX:16-Channel, ±135V Push-Pull Driver with RTZ, Current Sensor and Built-in Boost Converter. Thin Fine Pitch Ball Grid Array, 105-Ball TFBGA (9 x 9 x 1.2mm) Package, 260/Tray b) HV53001T-E/KWX:16-Channel, ±135V Push-Pull Driver with RTZ, Current Sensor and Built-in Boost Converter. Thin Fine Pitch Ball Grid Array, 105-Ball TFBGA (9 x 9 x 1.2mm) Package, 1000/Tape & Reel Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. PART NO. X- Media TypeDevice X Temperature /XXX Package Tape and Reel Range

DS20006518A-page 38  2021 Microchip Technology Inc. NOTES:

 2021 Microchip Technology Inc. DS20006518A-page 39 Information contained in this publication is provided for the sole purpose of designing with and using Microchip products. Infor- mation regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ens ure that your application meets with your specifications. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WAR- RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON- INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI- RECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUEN- TIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life sup- port and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectu al property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP , SimpliPHY , SmartBuffer, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2021, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-7936-9 Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specifications c ontained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is secu re when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished without violating Microchip's intellectual property rights.
• Microchip is willing to work with any customer who is concerned about the integrity of its code.
• Neither Microchip nor any other semic onductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

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