HV276

HV276 MICROCHIP | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 29

Technical content

Features

• 16 Channels of High-Voltage Output
• 16 Channels of 11-bit Digital-to-Analog Converters (DACs)
• Up to ±75V Output Voltage
• 1.0 µs Typical Rise/Fall Time
• 250 pF Fixed-Output Load
• 33 MHz Data Shift Register Speed
• 2.5V and 3.3V CMOS Compatible Logic Inputs
• Independent Serial Input Loading Protocol With Global Safety Control
• 80-Lead Single 11 x 11 x 0.9 mm VQFN Package Application
• OLED Print Head Driver General Description The HV276 is a 16-channel, high-voltage amplifier array. Each channel consists of a low-voltage digital-to- analog converter and a fixed-gain high-voltage opera- tional amplifier. The DAC has 11-bit resolution, and the DAC output is connected to the fixed-gain high-voltage operational amplifier with a maximum output voltage swing of ±75 V for a 250 pF capacitive load. Each receive channel has its own internal detection cir- cuit and individual receiver to validate the data from the serial-to-parallel interface using the SAFETY control signal and its protocol. This device consists of 16 11-bit shift registers, control logic functions and Power-on Reset (POR). Four power supplies are required, ±5.0V and ±90V. An external 3.0V voltage reference is needed for precision output. The system supports both 3.3 V or 2.5 V logic input. Typical Application Circuit CLK DIN1 DIN16 RST SAFETY 11Serial-to-Parallel Interface Hi-V Amp 11-bit DAC 11Serial-to-Parallel Interface Hi-V Amp 11-bit DAC Piezo Print Head CLK DIN1 DIN16 RST SAFETY 11Serial-to-Parallel Interface Hi-V Amp 11-bit DAC 11Serial-to-Parallel Interface Hi-V Amp 11-bit DAC Microcontroller 16 channels 16 channels Data, CLK, RST, SAFETY Ext Reference Voltage Ext Reference Voltage HV276 HV276 16-Channel, 11-Bit DACs and ±75V High-Voltage Amplifier Array Obsolete Device

DS20005662B-page 2  2016-2026 Microchip Technology Inc. and its subsidiaries Package Types (Top View) HV276 11 x 11 VQFN* DIN5 DVDD DIN3 DIN11 DIN14 DIN16 Heat NC DIN2 DIN8 DIN7 DIN6 DIN4 DIN1 DIN9 DIN10 DIN12 DIN13 DIN15 DVDD NC HVOUT7 HVOUT1 HVOUT5 HVOUT9 HVOUT12 HVOUT14 HVOUT2 HVOUT4 NC HVOUT8 HVOUT6 HVOUT3 RBIAS HVOUT10 HVOUT11 HVOUT16 HVOUT15 RBIAS NC HVOUT13 VREF DGND AVDD VREF VPP NC RST AGND AVDD NC NC AGND AVDD VSS AGND NC NC NC NC VNN AGND DGND AGND VREF VPP NC SAFETY AVDD AVDD NC VREF AVDD CLK VSS AGND NC NC NC NC VNN GND * Includes Exposed Thermal Pad (EP); see Table 3-1.

 2016-2026 Microchip Technology Inc. and its subsidiaries DS20005662B-page 3 HV276 Block Diagram 11-bit DAC VPP VNN VREF Hi-V Opamp HVOUT1 CLK DIN1 Bias Circuit HVOUT16 AVDD VSS VPP VNN GND 11-bit DAC VPP VNN Hi-V Opamp Bias Circuit DIN16 *Detector & 11-bit Shift Register RST SAFETY Detector & 11-bit Shift Register DVDD Power-RnReset RBIAS 16 channels

DS20005662B-page 4  2016-2026 Microchip Technology Inc. and its subsidiaries NOTES:

 2016-2026 Microchip Technology Inc. and its subsidiaries DS20005662B-page 5 HV276

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings † † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Electrical Specifications: unless otherwise specified, AVDD = 5.0V, DVDD = 5.0V, VSS = -5.0V, VPP = +90V, VNN = -90V, VREF = 3.0V ±0.1%, RST = 3.3V, TJ = +25°C. Parameter Symbol Min. Typ. Max. Units Conditions High-Level Input Voltage V IH 2.0 — DV DD V Low-Level Input Voltage V IL 0— 0 . 8 V Digital VDD Supply Current DI DD —2 53 8 m A f CLK = 33 MHz, all DIN = 16.5 MHz, no load. DIN = 0 to 3.3V logic input. Analog VDD Supply Current AI DD —2 74 5 m A f CLK = 33 MHz See test waveform in Figure 1-2. All 16 channels. VSS Supply Current I SS — 12 24 mA See test waveform in Figure 1-2. All 16 channels. VPP Supply Current I PP —1 63 2 m A C L = 250 pF. See test waveform in Figure 1-2. All 16 channels. V NN Supply Current I NN —1 73 4 m A C L = 250 pF. See test waveform in Figure 1-2. All 16 channels. Digital V DD Supply Quiescent Current DIDDQ — 112 200 µA All D IN = 0V, all input logic pins = 0V Analog VDD Supply Quiescent Current AIDDQ —2 43 9 m A A l l D IN = 0V, all input logic pins = 0V, HVOUT = 0V, DAC = 400h VSS Supply Quiescent Current ISSQ —91 8 m A A l l D IN = 0V, all input logic pins = 0V VPP Supply Quiescent Current IPPQ —1 . 5 3m A H V OUT = 0V, DAC = 400h VNN Supply Quiescent Current INNQ —2 4 m A H V OUT = 0V, DAC = 400h Note 1: Specification is obtained by characterization and is not 100% tested. 2: Design guidance only. 3: Specification is obtained by characterization and the high-voltage output is 100% tested for monotonicity.

DS20005662B-page 6  2016-2026 Microchip Technology Inc. and its subsidiaries High-Level Logic Input Cur- rent IIH —— 1 . 0 µ A V IH = DVDD Low-Level Logic Input Cur- rent IIL -1.0 — — µA V IL = 0V Quiescent Input Current at the VREF pin IREFQ ——1 0 m A V REF = 3.0V ±0.1%, DAC = 400h Input Current at the VREF pin I REF —51 0 m A V REF. = 3.0V ±0.1%, fCLK = 33 MHz, DAC = 555h High-Voltage Amplifier Minimum HVOUT High-Voltage Positive Output HVOH(min) +75 — — V V PP = 90V, VNN = -90V, CL= 250 pF, DAC = 7FFh, VREF = 3.3V Maximum HVOUT High-Voltage Negative Out- put HVOL(max) — — -75 V V PP = 90V, VNN = -90V, CL = 250 pF, DAC = 000h, VREF = 3.3V Range of HVOUT HVOUT Range VNN + 5 — V PP - 5 V HVOUT High-voltage Output Offset HVOFFSET — — ±830 mV V PP = 90V, VNN = -90V, CL = 250 pF, DAC = 400h DAC Differential Nonlinearity DNL — — ±0.75 LSB V DD = 5.0V, VSS = -5.0V VREF = 3.0V (Note 3) Integral Nonlinearity INL — — ±2.0 LSB V DD = 5.0V, VSS = -5.0V VREF = 3.0V (Note 3) TABLE 1-1: DC CHARACTERISTICS (CONTINUED) Electrical Specifications: unless otherwise specified, AVDD = 5.0V, DVDD = 5.0V, VSS = -5.0V, VPP = +90V, VNN = -90V, VREF = 3.0V ±0.1%, RST = 3.3V, TJ = +25°C. Parameter Symbol Min. Typ. Max. Units Conditions Note 1: Specification is obtained by characterization and is not 100% tested. 2: Design guidance only. 3: Specification is obtained by characterization and the high-voltage output is 100% tested for monotonicity.

 2016-2026 Microchip Technology Inc. and its subsidiaries DS20005662B-page 7 HV276 TABLE 1-2: AC CHARACTERISTICS Electrical Specifications: unless otherwise specified, AVDD = 5.0V, DVDD = 5.0V, VSS = -5.0V, VPP = +90V, VNN = -90V, VREF = 3.0V ±0.1%, RST = 3.3V, tR(rise time) = 5 ns, tF(fall time) = 5 ns, TJ = +25°C. Parameter Symbol Min. Typ. Max. Units Conditions Digital logic input capacitance C IN — — 15 pF Note 1 Clock high pulse width t WH 15 — — ns Note 1 Clock low pulse width t WL 10 — — ns Note 1 Data setup time before clock falls tSU 12 — — ns Note 1 Data hold time after clock falls t H 5—— n s Note 1 High-Voltage Amplifier Bias Resistor R BIAS 57.0 57.6 58.2 k  VPP = 90V, VNN = -90 V, VDD = 5.0V, VSS = -5.0 V (Note 2) Feedback Impedance R FB 320 — k  (Note 2) Amplifier Closed Loop Gain A v —5 0 — V / V (Note 2) Output Tolerance Tolerance — — ±3 % ±75V full scale, VPP = 90V, VNN = -90V, CL = 250 pF, VREF = 3.0V ±0.1%. Measured with 0V output offset. Overshoot Voltage Overshoot — — 10 % V PP = 90V, VNN = -90V, CL= 250 pF, DAC from 400h to 7FFh. Maximum of final output. Undershoot Voltage Undershoot — — 10 % V PP = 90V, VNN = -90V, CL = 250 pF, DAC from 400h to 000h. Maximum of final output. HVOUT Drift over temperature — — ±200 mV From T J = +25°C to +70°C (Note 1) HVOUT Drift due to aging — — ±800 mV T J = +125°C for 168 hours (Note 1) Total Drift — — ±1000 mV Sum of both over temperature and aging (Note 1) Pulse Frequency f PULSE — — 20 kHz Pulse frequency is for power dissipation estimation (Note 2) HVOUT Fixed Capacitive Load C LOAD 237 250 263 pF V PP = 90V, VNN = -90V (Note 2) Rise Time and Fall Time t RT/tFT — 1 1.65 µs V PP = 90V, VNN= -90V, CL = 250 pF tRT: 10% to 90% of final value. tFT: 90% to 10% of initial value. Temperature range from 0°C to +100°C. See Figure 1-1. Note 1: Specification is obtained by characterization and is not 100% tested. 2: Design guidance only.

DS20005662B-page 8  2016-2026 Microchip Technology Inc. and its subsidiaries Settling Time t ST — 1 2.20 µs V PP = 90V, VNN= - 90V, CL= 250 pF. Temperature range from 0°C to +100°C. See Figure 1-1. Latency from end of data frame (15th clock cycle) to 10% of HVOUT tdHL/tdLH — — 1000 ns V DD = 5.0V, VSS = -5.0V, VPP = 90V, VNN = -90V, CL= 250 pF. See Figure 1-4. HVOUT Latency Tolerance td — — ±500 ns V DD = 5.0V, VSS = -5.0V, VPP = 90V, VNN = -90V, CL= 250 pF. See Figure 1-4. TEMPERATURE SPECIFICATIONS Electrical Specifications: unless otherwise specified, AVDD = 5.0V, DVDD = 5.0V, VSS = -5.0V, VPP = +90V, VNN = -90V, VREF = 3.0V ±0.1%, RST = 3.3V, TJ = +25°C. Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Operating Junction Temperature Range T J 0— + 1 0 0 ° C Storage Temperature Range T A -55 — +150 °C Maximum Junction Temperature T J —— + 1 2 5 ° C Package Thermal Resistances Thermal Resistance, 80L-11x11 VQFN R ,JA —1 7 . 3 5 — ° C / W Thermal Resistance (with thermal pad), 80L-11x11 VQFN R,JC — 2.15 — °C/W TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Electrical Specifications: unless otherwise specified, AVDD = 5.0V, DVDD = 5.0V, VSS = -5.0V, VPP = +90V, VNN = -90V, VREF = 3.0V ±0.1%, RST = 3.3V, tR(rise time) = 5 ns, tF(fall time) = 5 ns, TJ = +25°C. Parameter Symbol Min. Typ. Max. Units Conditions Note 1: Specification is obtained by characterization and is not 100% tested. 2: Design guidance only.

 2016-2026 Microchip Technology Inc. and its subsidiaries DS20005662B-page 9 HV276

1.1 Timing Diagrams

FIGURE 1-1: High-Voltage Output Settling Time Diagram. FIGURE 1-2: Test Waveform Pattern. FIGURE 1-3: Switching Waveform Diagram. Overshoot Undershoot Undershoot Overshoot +HV -HV tST tST 90% 10% tST 90% tST 10% +1% +1% +1% +1% 90% 10% 10% 90% +75V -75V 10 μs 10 μs 50 μs HVOUT 50%50% Data VIL VIH tHtSU CLK Data Input or Control 'ata ,nput 50%50%50%50% tWH tWL VIL VIH

DS20005662B-page 10  2016-2026 Microchip Technology Inc. and its subsidiaries FIGURE 1-4: HVOUT Output Latency. 1 234567 89 10 11 12 13 14 15 10% 10% +ve -ve HVOUT HVOUT CLK tdLH tdHL /g39td /g39td Valid Data Frame DAC Output Available at Rising Edge

 2016-2026 Microchip Technology Inc. and its subsidiaries DS20005662B-page 11 HV276

2.0 TYPICAL PERFORMANCE DIAGRAMS

FIGURE 2-1: Typical Output Waveform of the Test Waveform Pattern (VDD = +5.0V, VSS = -5.0V, VREF = +3.0V, VPP = +90V, VNN = -90V). FIGURE 2-2: Typical 0V to +75V Rise Time (VDD = +5.0V, VSS = -5.0V, VREF = +3.0V, VPP = +90V, VNN = -90V). FIGURE 2-3: Typical -75V to 0V Rise Time (VDD = +5.0V, VSS = -5.0V, VREF = +3.0V, VPP = +90V, VNN = -90V). FIGURE 2-4: Typical +75V to 0V Fall Time (VDD = +5.0V, VSS = -5.0V, VREF = +3.0V, VPP = +90V, VNN = -90V). FIGURE 2-5: Typical 0 to -75V Fall Time (VDD = +5.0V, VSS = -5.0V, VREF = +3.0V, VPP = +90V, VNN = -90V). Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or ta bles, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

 2016-2026 Microchip Technology Inc. and its subsidiaries DS20005662B-page 13 HV276

3.0 PIN DESCRIPTION

The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Pin Symbol Description 1D V DD Digital low-voltage supply

2 NC No connect

3 DIN1 Data Input #1

4 DIN2 Data Input #2

5 DIN3 Data Input #3

6 DIN4 Data Input #4

7 DIN5 Data Input #5

8 DIN6 Data Input #6

9 DIN7 Data Input #7

10 DIN8 Data Input #8

11 DIN9 Data Input #9

12 DIN10 Data Input #10

13 DIN11 Data Input #11

14 DIN12 Data Input #12

15 DIN13 Data Input #13

16 DIN14 Data Input #14

17 DIN15 Data Input #15

18 DIN16 Data Input #16

19 NC No connect

DD Digital low-voltage supply

21 DGND Digital circuit ground

22 R ST Reset bar

23 AV DD Analog POS low-voltage supply

24 AGND Analog circuit ground

25 AV DD Analog POS low-voltage supply (DAC)

26 AGND Analog circuit ground (DAC)

REF Voltage reference input (DAC)

28 NC No connect

29 NC No connect

DD Analog POS low-voltage supply (AMP)

31 VSS Analog NEG low-voltage supply

32 AGND Analog circuit ground (AMP)

REF Voltage reference input (AMP)

34 NC No connect

35 NC No connect

PP POS high-voltage supply

37 NC No connect

38 NC No connect

39 V NN NEG high-voltage supply

40 NC No connect

41 HVOUT16 High-voltage output #16

DS20005662B-page 14  2016-2026 Microchip Technology Inc. and its subsidiaries

42 HVOUT15 High-voltage output #15

43 HVOUT14 High-voltage output #14

44 HVOUT13 High-voltage output #13

45 HVOUT12 High-voltage output #12

46 HVOUT11 High-voltage output #11

47 HVOUT10 High-voltage output #10

48 HVOUT9 High-voltage output #9

49 NC No connect

50 RBIAS Connect to ground through R

51 RBIAS Connect to ground through R BIAS resistor

52 NC No connect

53 HVOUT8 High-voltage output #8

54 HVOUT7 High-voltage output #7

55 HVOUT6 High-voltage output #6

56 HVOUT5 High-voltage output #5

57 HVOUT4 High-voltage output #4

58 HVOUT3 High-voltage output #3

59 HVOUT2 High-voltage output #2

60 HVOUT1 High-voltage output #1

61 NC No connect

NN NEG high-voltage supply

63 NC No connect

64 NC No connect

PP POS high-voltage supply

66 NC No connect

67 NC No connect

REF Voltage reference input (AMP)

69 AGND Analog circuit ground (AMP)

SS Analog NEG low-voltage supply

71 AV DD Analog POS low-voltage supply (AMP)

72 NC No connect

REF Voltage reference input (DAC)

74 AGND Analog circuit ground (DAC)

75 AV DD Analog POS low-voltage supply (DAC)

76 AGND Analog circuit ground

77 AV DD Analog POS low-voltage supply

78 C LK Clock Input

79 SAFETY Safety control input

80 DGND Digital circuit ground

Heat GND Connect to ground TABLE 3-1: PIN FUNCTION TABLE (CONTINUED) Pin Symbol Description

 2016-2026 Microchip Technology Inc. and its subsidiaries DS20005662B-page 15 HV276

4.0 FUNCTIONAL DESCRIPTION

4.1 Power-Up, Power-Down and

To power-up HV276, perform the following power-up sequence: 1. Connect ground. 2. Set all inputs to low. 3. Enable power supplies in this sequence: VNN, VSS, DVDD, AVDD, VREF, VPP. 4. Set all inputs to a known state. To power-down HV276, perform the following power- down sequence: 1. Set all inputs to low. 2. Disconnect power supplies in this sequence: VPP, VREF, AVDD, DVDD, VSS, VNN. 3. Disconnect ground. FIGURE 4-1: Input Equivalent Circuits. TABLE 4-1: RECOMMENDED OPERATING CONDITIONS (T J = 0°C to +100°C) Parameter Symbol Min. Typ. Max. Units Positive High-Voltage Supply V PP 35 — 90 V Negative High-Voltage Supply V NN -90 — -35 V Analog Circuit Low Positive Supply Voltage AV DD 4.75 5.00 5.25 V Digital Circuit Low Positive Supply Voltage DV DD 4.75 5.00 5.25 V Negative Low-Voltage Supply Voltage V SS -5.25 -5.00 -4.75 V Reference Voltage Input V REF 0.6 3.0 3.3 V Clock Frequency f CLK 0— 3 3 M H z VDD Input GND

DS20005662B-page 16  2016-2026 Microchip Technology Inc. and its subsidiaries

4.2 Communication Protocol

The data transmission from the microcontroller to the HV276 device conforms to a custom communication protocol, as shown below. Both header bits and a trailer bit are added to the data packet to improve its error rate. The state machine diagram in Figure 4-2 shows how the HV276 receiver accepts and validates the received data. Each DAC data input receives its data from a 11-bit shift register. The DAC read process is controlled by an internal detection circuit. The detector stays idle until there is a trigger signal at SAFETY control input. Within the window of this trigger si gnal, the detector at the serial input waits for two transitions, a low-to-high transition followed by a high-to-low transition. The 11 bits of serial data follow after the high-to-low transition is observed. A “0” will be inserted at the end of the data stream. After the frame da ta has completed, the system will automatically latc h into the shift-register output and to the DAC. The HV OUT will start its transition at the rising edge of the 15th clock cycle. The detector can start its next detection operation at the falling edge of the 15 th clock cycles. Therefore, the DAC update take s 14 clock cycles. With a clock frequency of 33 MHz, the refresh rate will be 424 ns. The SAFETY signal is shared by all sixteen channels; however, each channel loads the data independently at any time based on the status of the detector. After the detector has activated to accept the data stream, the SAFETY signal will be ignored during the read process. It will resume the detection process after the data frame has been completed. FIGURE 4-2: State Machine Diagram of the HV276 Receiver. IDLE MARK RX LOAD DAC END FRAME START DIN = 1 and SAFETY = 1 DIN = 0 DIN = 1 (Invalid frame detected) DIN = 0 SHIFT_DONE = 1 DIN = 1 (Invalid frame detected) Output: LD_DAC =0 SHIFT_ACTIVE =1 Output: LD_DAC =0 SHIFT_ACTIVE =0 Output: LD_DAC =0 SHIFT_ACTIVE =0 Output: LD_DAC =0 SHIFT_ACTIVE =0 Output: LD_DAC = 1 SHIFT_ACTIVE =0 START: Set DAC to 400h from the START state RX: Receive and store 11 bits from DIN data stream Load DAC: Load 11 bis of data stored in RX state to DAC DIN = 1 and SAFETY = 1

 2016-2026 Microchip Technology Inc. and its subsidiaries DS20005662B-page 17 HV276 FIGURE 4-3: Data Pattern Diagram. CLK SAFETY DIN Ignore cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HVOUT DATA FRAME VIL VIH VIL VIH VIL VIH VOL VOH DAC output available at rising edge

DS20005662B-page 18  2016-2026 Microchip Technology Inc. and its subsidiaries

4.3 DAC Settings

The HVOUT output voltage is a function of the reference voltage V REF. Equation 4-1 is used to compute its typical output voltage. EQUATION 4-1: TYPICAL HV OUT OUTPUT VOLTAGE (VOLTS)

4.4 V REF Input Reference Voltage

An external reference V REF provides a reference voltage to the DAC block. The DAC output is linearly proportional to the voltage reference V REF. Since the output amplifier has a fixed gain, this reference voltage will directly affect the scaling factor of the output within the operating voltage. Consequently, the reference voltage V REF can be used as a global gain adjustment for the device. This feature provides the flexibility to adjust the output scale without any change to the software and DAC bit resolution. This reference voltage supplies to all 16 channels of DACs. The stability and accuracy of this reference are very important to the performance of the system. The tolerance of the reference will create an equal amount of variation at the DAC output. One important factor to consider for a suitable external voltage reference is its loading capability. Since all 16 DACs are running independently, the V REF operating current may become difficult to predict. Therefore, a decoupling capacitor is recommended to connect to the V REF pin to provide a stable reference voltage.

4.5 R BIAS External Bias Resistor

An external bias resistor is used to set the bias current of the operational amplifier. A high-precision resistor will improve the amplifier out put tolerance. A resistor with less than ±1% tolerance is recommended. The two R BIAS pins of the device should be connected together externally to ground through a single R BIAS resistor. Furthermore, a high-quality 0.1 µF ceramic capacitor should be added in parallel with the reference resistor to suppress any noise. FIGURE 4-4: RBIAS Resistor Connection

4.6 Power On Reset (POR) and RST

Power-on Reset (POR) function will reset the DAC input to 400h and set the HVOUT output to 0V when the device is initially powered. This initialization happens Note: Equation 4-1 is for reference only. The output accuracy and tolerance are only for VREF = 3.0V ± 0.1%.

50 V REF DAC decimal 1024–

Where: DAC (decimal) = 0 – 2047 VREF = 0.6 – 3.0V TABLE 4-2: EXAMPLE OF DAC SETTINGS AND HV OUT 11-bit Setting (HEX) Typical HV OUT Output Voltage Units Conditions 000h -75.0 V VREF = 3.0V ± 0.1%400h 0 V 7FFh 74.93 V GND HV276 RBIA S (pin 51) RBIA S RBIA S (pin 50) 0.1 μF

 2016-2026 Microchip Technology Inc. and its subsidiaries DS20005662B-page 19 HV276 without any user interactio n. The POR function will avoid any output pins to pull to either power rails or any undetermined voltage level during startup. When the device is in operation, the user can pull the RST pin to 0V to reset the DAC to 400h and all HVOUT to 0V. In addition, both PORT and RST functions will also reset the receiver state machine to its initial idle state.

4.7 Continuous Operation Mode

Figure 4-5 shows the data pattern when the device is running continuously with new updated data. A valid frame data will latch to the DAC at the rising edge of the 15th clock cycle, and the HV OUT will start its transition at the same time. The receiver state machine can go to the MARK state if both SAF ETY and DIN are logic “1” at the falling edge of the 15 th clock cycle, so the next normal detection process can start at the 15 th clock cycle. The next HV OUT transition can happen at the rising edge of the 29 th clock cycle. This operation can reduce the propagation delay of the HVOUT output, and the DAC update is completed every 14 clock cycles. FIGURE 4-5: Continuous Operation Mode. 1 2 3 14 15 16 17 18 28 29 30 31 SAFETY HVOUT CLK Valid Data Frame Valid Data FrameDIN

DS20005662B-page 20  2016-2026 Microchip Technology Inc. and its subsidiaries NOTES:

 2016-2026 Microchip Technology Inc. and its subsidiaries DS20005662B-page 21 HV276

5.0 PACKAGING INFORMATION

5.1 Package Marking Information

Legend: XX...X Product Code or Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part num ber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo. 80-Lead VQFN (11 x 11 x 0.9 mm) Example HV276K6^^ 1640256

DS20005662B-page 22  2016-2026 Microchip Technology Inc. and its subsidiaries BA 0.15 C 0.15 C

0.10 C A B

(DATUM B) (DATUM A) NOTE 1 TOP VIEW SIDE VIEW BOTTOM VIEW For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: NOTE 1 N 0.10 C 0.08 C Microchip Technology Drawing C04-301A Sheet 1 of 2 80-Lead Plastic Quad Flat, No Lead Package (8FX) – 11x11x0.9 mm Body [VQFN] 80X D E N e 80X L 80X K 80X b (A3)A C SEATING PLANE

 2016-2026 Microchip Technology Inc. and its subsidiaries DS20005662B-page 23 HV276 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Dimension Limits Units D Overall Width Overall Length Exposed Pad Length Exposed Pad Width Terminal Thickness E 9.70 MILLIMETERS

0.203 REF

(A3) MAX

11.00 BSC

L b 0.50 0.30 Notes: KTerminal-to-Exposed Pad 0.20 NOM BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Standoff A1 - Overall Height A 0.85 Pitch e 0.50 BSC Number of Terminals N8 0 0.30 0.18 9.50 0.00 0.80 0.25 0.40 9.60 0.05 0.90 Pin 1 visual index feature may vary, but must be located within the hatched area. Dimensioning and tolerancing per ASME Y14.5M. Package is saw singulated. Microchip Technology Drawing C04-301A Sheet 2 of 2 80-Lead Plastic Quad Flat, No Lead Package (8FX) – 11x11x0.9 mm Body [VQFN] 9.709.50 9.60

DS20005662B-page 24  2016-2026 Microchip Technology Inc. and its subsidiaries RECOMMENDED LAND PATTERN For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Dimension Limits Units Optional Center Pad Width Contact Pad Spacing Optional Center Pad Length Contact Pitch 9.70 9.70 MILLIMETERS

0.50 BSC

E MAX 11.00 Contact Pad Length (X20) Contact Pad Width (X80) 0.80 0.30 Microchip Technology Drawing C04-2301A NOM SILK SCREEN E C1Contact Pad Spacing 11.00 Contact Pad to Center Pad (X80) G2 0.20 Thermal Via Diameter V Thermal Via Pitch EV 0.33 1.200 ØV EV EV 80-Lead Plastic Quad Flat, No Lead Package (8FX) – 11x11x0.9 mm Body [VQFN] Contact Pad to Contact Pad (X76) G1 0.20 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process

 2016-2026 Microchip Technology Inc. and its subsidiaries DS20005662B-page 25 HV276 APPENDIX A: REVISION HISTORY Revision B (January 2026)

• Added the Obsolete Device label on the first page. Revision A (November 2016)
• Original Release of this Document.

DS20005662B-page 26  2016-2026 Microchip Technology Inc. and its subsidiaries NOTES:

 2016-2026 Microchip Technology Inc. and its subsidiaries DS20005662B-page 27 HV276 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX PackageDevice Device: HV276: 16-Channel, 11-Bit DACs and ±75V High-Voltage Amplifier Array Package Options: K6 = Very Thin Plastic Quad Flat Pack, No Lead Package – 11.00x11.00x0.9 mm Body, 0.50 mm Pitch, 80-Lead (VQFN) Environmental: G = Lead (Pb)-free/ROHS-compliant package Media Type: = 176/Tray for K6 Package Examples: a) HV276K6-G: 16-Channel, 11-Bit DACs and ±75V High-Voltage Amplifier Array, 80-lead 11 x1 1 x 0.9 mm VQFN, 176/Tray Environmental Options Media Type

DS20005662B-page 28  2016-2026 Microchip Technology Inc. and its subsidiaries. NOTES:

 2016-2026 Microchip Technology Inc. and its subsidiaries DS20005662B-page 29 Microchip Information Trademarks The “Microchip” name and logo, the “M” logo, and other names, logos, and brands are registered and unregistered trademarks of Microchip Technology Incorporated or its affiliates and/or subsidiaries in the United States and/or other countries (“Microchip Trademarks”). Information regarding Microchip Trademarks can be found at https://www.microchip.com/en-us/about/legal-information/microchip- trademarks. ISBN: 979-8-3371-2689-0 Legal Notice This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this information in any other manner violates these terms. Information regarding device applications is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at www.microchip.com/en-us/support/design-help/client-support-services. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL, OR CONSEQUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Microchip Devices Code Protection Feature Note the following details of the code protection feature on Microchip products:

• Microchip products meet the specifications cont ained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions.
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