HV2721

HV2621 MICROCHIP | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 26

Technical content

Features

• 300V,16-Channel High-Voltage Analog Switch
• 3.3V or 5.0V CMOS Input Logic Level
• 33 MHz Data Shift Clock Frequency
• Very Low Quiescent Current (10 µA)
• Low Parasitic Capacitance
• DC to 50 MHz Analog Small-Signal Frequency
• -60 dB Typical Off Isolation at 5.0 MHz
• Excellent Noise Immunity
• Cascadable Serial Data Register with Latches
• Flexible Operating Supply Voltage
• Integrated Bleed Resistors on the Outputs (both sides for HV2721, one side only for HV2722)

Applications

• Medical Ultrasound Imaging
• Nondestructive Testing (NDT) Metal Flaw Detection
• Multi-Layer Printed Circuit Board (PCB) Tester
• Piezoelectric Transducer Drivers
• Inkjet Printer Head
• Optical MEMS Module General Description The HV2621/HV2721/HV2722 devices are 300V, low-charge injection, 16-channel, high-voltage analog switches. These devices are designed for use in applications requiring high-voltage switching controlled by low-voltage control signals, such as medical ultrasound imaging, piezoelectric transducer drivers. HV2621/HV2721 are almost identical to HV2601/2701 but have larger signal range. If the V PP/VNN = ±150V, HV2621/HV2721/HV2722 can pass the analog signal up to ±135V. The HV2721 has integrated bleed resistors on both sides of the switches. HV2722 has integrated bleed resistors on one side, SWxA only. HV2621 has no bleed resistors. The bleed resistor eliminates voltage build-up on capacitive loads such as piezoelectric transducers. Input data are shifted into a 16-bit shift register that can then be retained in a 16-bit latch. To change all the switch state at the same time, the latch enable bar should be left high until all bits are clocked in. The input data are clocked in at the rising edge of the clock. After all bits are clocked in to the shift register, a negative pulse of the latch enable bar changes all the switch ON/OFF states defined by input data at the same time. Using the HVCMOS technology, these devices combine 300V high-voltage bilateral DMOS switches and low-power CMOS logic to provide efficient control of high-voltage analog signals. These devices are suitable for various combinations of high-voltage supplies, e.g., V PP/VNN: +60V/-240V, +150V/-150V, and +260V/-40V. Package Types HV2621/HV2721/HV2722 9x9x1.0mm QFN (TOP VIEW) 300V , Low-Charge Injection, 16-Channel, High-Voltage Analog Switch

DS20006082A-page 2  2019 Microchip Technology Inc. Block Diagram VNNCLR CLK DIN GNDVDD DOUT Bleed Resistors RGNDLE Latches 16-Bit Shift Register Level Shifter Output Switches SW0A SW0B D LE CLR SW1A SW1B D LE CLR SW2A SW2B D LE CLR SW14A SW14B D LE CLR SW15A SW15B D LE CLR HV2721 has bleed resistors at SWxA and SWxB HV2722 has bleed resistors at SWxA only VPP

 2019 Microchip Technology Inc. DS20006082A-page 3 HV2621/HV2721/HV2722

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings † † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (NOTES 1, 2, 3) Parameter Sym. Min. Typ. Max. Units Conditions Logic Supply Voltage V DD 3— 5 . 5 V Differential Supply Voltage V PP-VNN 60 — 300 V Positive Supply Voltage V PP 60 — 260 V Negative Supply Voltage V NN -240 — 0 V High-Level Input Voltage V IH 0.9VDD —V DD V Low-Level Input Voltage V IL 0— 0 . 1 V DD V Analog Signal Voltage Peak-to-Peak V SIG VNN+15 — V PP-15 V Note 1: Recommended power up sequence is VDD, VPP and VNN. Power down is in reverse order. 2: VSIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transition. 3: Rise and fall times of power supplies, VDD, VPP and VNN should be greater than 1.0 ms. DC ELECTRICAL CHARACTERISTICS Unless otherwise specified, VPP = +150V, VNN = -150V, VDD = 5.0V, TA =2 5°C. Boldface specifications apply over the full operating temperature range. Parameter Sym. Min. Typ. Max. Units Conditions/Comments Small Signal Switch On-Resistance R ONS —2 6 48 Ω ISIG = 5 mA VPP = +60V, VNN = -240V—2 2 32 Ω ISIG = 150 mA —2 2 30 Ω ISIG = 5 mA VPP = +150V, VNN = -150V—1 8 27 Ω ISIG = 150 mA —2 0 30 Ω ISIG = 5 mA VPP = +260V, VNN = -40V—1 6 27 Ω ISIG = 150 mA Small Signal Switch On-Resistance Matching ∆RONS —5 20 % ISIG = 5 mA, VPP = +150V, VNN = -150V Large Signal Switch On-Resistance R ONL —1 7— Ω VSIG = VPP-15V, ISIG =1A Value of Output Bleed Resistor (HV2721/HV2722 Only) RINT 30 50 70 k Ω Output switch to RGND, IRINT = 0.5 mA Switch Off Leakage per Switch I SOL —1 15 μA VSIG = VPP-15V, VNN+15V. See Figure 3-1 DC Offset Switch Off VOS —1 10 mV RLOAD =3 5k Ω (HV2621), 70 kΩ (HV2722), No load (HV2721), see Figure 3-2DC Offset Switch On — 1 10

DS20006082A-page 4  2019 Microchip Technology Inc. Quiescent VPP Supply Current I PPQ —1 0 50 μA All switches offQuiescent VNN Supply Current I NNQ —1 0 50 μA Quiescent VPP Supply Current I PPQ —1 0 50 μA All switches on, ISW = 5.0 mAQuiescent VNN Supply Current I NNQ —1 0 50 μA Switch Output Peak Current I SW 2.0 3.0 — A V SIG duty cycle <0.1% (Note 1) Output Switching Frequency f SW — — 50 kHz Duty cycle = 50% ( Note 1) Average VPP Supply Current I PP —— 3 mA VPP =+ 6 0 V , VNN = -240V All output switches are turning on and off at 10 kHz with no load —— 4 mA V PP = +150V, VNN = -150V — — 6 mA VPP = +260V, VNN =- 4 0 V Average VNN Supply Current I NN —— 3 mA VPP =+ 6 0 V , VNN = -240V All output switches are turning on and off at 10 kHz with no load —— 4 mA V PP = +150V, VNN = -150V — — 6 mA VPP = +260V, VNN =- 4 0 V Average VDD Supply Current I DD —— 4 mA f CLK =5M H z , fDIN=2 . 5M H z Quiescent VDD Supply Current I DDQ —— 10 μA All logic inputs are static Data Out Source Current I SOR 8 —— m A V OUT = VDD -0.7V Data Out Sink Current I SINK 12 —— m A V OUT = 0.7V Logic Input Capacitance C IN — — 10 pF Note 2 Note 1: Specification is obtained by characterization and is not 100% tested. 2: Design guidance only. AC ELECTRICAL CHARACTERISTICS Unless otherwise specified, VPP = +150V, VNN = -150V, VDD = 5.0V, tR =t F ≤ 5.0 ns, 50% duty cycle, CLOAD =2 0p F , TA =2 5°C, Boldface specifications apply over the full operating temperature range. Setup Time before LE rises t SD 25 ——n s Note 1 Time Width of LE tWLE 56 ——n s VDD = 3.3V (Note 1) 12 ——n s VDD = 5.0V (Note 1) Clock Delay Time to Data Out t DO -— 45 ns VDD = 3.3V -— 25 ns VDD = 5.0V Time Width of CLR t WCLR 55 —— ns Note 1 Setup Time Data to Clock t SU 7 —— ns VDD = 3.3V (Note 1) 7 —— ns VDD = 5.0V (Note 1) Hold Time Data from Clock t H 4 —— ns VDD = 3.3V (Note 1) 3.5 ns VDD = 5.0V (Note 1) DC ELECTRICAL CHARACTERISTICS (CONTINUED) Unless otherwise specified, VPP = +150V, VNN = -150V, VDD = 5.0V, TA =2 5°C. Boldface specifications apply over the full operating temperature range. Parameter Sym. Min. Typ. Max. Units Conditions/Comments

 2019 Microchip Technology Inc. DS20006082A-page 5 HV2621/HV2721/HV2722 Clock Frequency f CLK —— 16 MHz V DD = 3.3V (Note 1) —— 33 MHz V DD = 5.0V (Note 1) Clock Rise and Fall Time t R, tF —— 50 ns Note 1 Turn-On Time t ON —— 6 μs VSIG = VPP-15V, RLOAD = 20 kΩ See Figure 3-3Turn-Off Time t OFF —— 6 Maximum VSIG Slew Rate dV/dt ——2 0 V/ns VPP = +60V, VNN = -240V (Note 1) ——2 0 V PP = +150V, VNN = -150V (Note 1) ——2 0 V PP = +260V, VNN = -40V (Note 1) Off Isolation K O —- 5 5 - 5 0 dB f = 5.0 MHz,1.0 kΩ//15 pF load See Figure 3-4 (Note 1) —- 6 0 - 5 8 f = 5.0 MHz, 50Ω load See Figure 3-4 (Note 1) Switch Crosstalk K CR —- 7 0 - 6 0d B f = 5.0 MHz, 50Ω load See Figure 3-5 (Note 1) Output Switch Isolation Diode Current IID — — 200 mA 300 ns pulse width, 2.0% duty cycle, See Figure 3-6 (Note 1) Off Capacitance SW to GND C SG(OFF) —1 0— pF VSIG = 50 mV@1MHz, no load (Note 1)On Capacitance SW to GND C SG(ON) —1 8— Output Voltage Spike at SWA, SWB +VSPK — — 250 mV VPP = +60V, VNN = -240V, RLOAD = 50Ω, see Figure 3-7 (Note 1)-VSPK -250 — — +VSPK — — 250 VPP = +150V, VNN = -150V, RLOAD = 50Ω, see Figure 3-7 (Note 1)-VSPK -250 — — +VSPK — — 250 VPP = +260V, VNN = -40V, RLOAD = 50Ω, see Figure 3-7 (Note 1)-VSPK -250 — — Charge Injection QC — 1000 — pC VPP = +60V, VNN = -240V, VSIG = 0V, see Figure 3-8 (Note 1) — 770 — VPP = +150V, VNN = -150V, VSIG = 0V, see Figure 3-8 (Note 1) — 360 — VPP = +260V, VNN = -40V, VSIG=0V, see Figure 3-8 (Note 1) Note 1: Specification is obtained by characterization and is not 100% tested. AC ELECTRICAL CHARACTERISTICS (CONTINUED) Unless otherwise specified, VPP = +150V, VNN = -150V, VDD =5 . 0 V , tR =t F ≤ 5.0 ns, 50% duty cycle, CLOAD =2 0p F , TA =2 5°C, Boldface specifications apply over the full operating temperature range. TEMPERATURE SPECIFICATION Parameters Sym Min Typ Max Units Conditions Temperature Range Operating Temperature Range T A 0— + 7 0 °C Storage Temperature Range T S -65 — +150 °C Maximum Junction Temperature T J — — +125 °C Package Thermal Resistance Thermal Resistance, 64L QFN Θ JA —2 1— °C/W

DS20006082A-page 6  2019 Microchip Technology Inc. TABLE 1-1: TRUTH TABLE ( NOTES 1, 2, 3, 4, 5, 6) ... ... —L L O F F — ... ... X X X X X X X H L HOLD PREVIOUS STATE XXXXXXXXH A L L S W I T C H E S O F F Note 1: The 16 switches operate independently. 2: Serial data is clocked in on the L to H transition of the CLK. 3: All 16 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low, the shift registers data flow through the latch. 4: DOUT is high when data in the register 15 is high. 5: Shift register clocking has no effect on the switch states if LE is high. 6: The CLR clear input overrides all the inputs.

 2019 Microchip Technology Inc. DS20006082A-page 7 HV2621/HV2721/HV2722

1.1 Typical Timing Diagrams

Figure 1-1 shows the timing of the AC characteristic parameters graphically. FIGURE 1-1: Logic Input Timing Diagram. '$7$ '1 '1 '1 &/2&. W:/( W6' W+W68 W'2 '$7$ 287 W21W2)) 9RXW W\\S &/5 W:&/5 2))

DS20006082A-page 8  2019 Microchip Technology Inc.

2.0 PIN DESCRIPTION

This section details the pin description for 64-lead QFN package (Figure 2-1).The descriptions of the pins are listed in Table 2-1. FIGURE 2-1: 64-Lead QFN Package - Top View. TABLE 2-1: PIN FUNCTION TABLE Pin Number Symbol

Description

1 SW5A SW5A Analog Switch 5 Terminal A

2 NC NC No Connection

3 SW4B SW4B Analog Switch 4 Terminal B

4 SW4A SW4A Analog Switch 4 Terminal A

5 NC NC No Connection

6 SW3B SW3B Analog Switch 3 Terminal B

7 SW3A SW3A Analog Switch 3 Terminal A

8 NC NC No Connection

9 SW2B SW2B Analog Switch 2 Terminal B

10 SW2A SW2A Analog Switch 2 Terminal A

11 NC NC No Connection

 2019 Microchip Technology Inc. DS20006082A-page 9 HV2621/HV2721/HV2722

12 SW1B SW1B Analog Switch 1 Terminal B

13 SW1A SW1A Analog Switch 1 Terminal A

14 NC NC No Connection

15 SW0B SW0B Analog Switch 0 Terminal B

16 SW0A SW0A Analog Switch 0 Terminal A

NN VNN Negative Supply Voltage

18 NC NC No Connection

PP VPP Positive Supply Voltage

20 NC NC No Connection

21 CLR CLR Latch Clear Logic Input

LE Latch Enable Logic Input

23 GND GND Ground

24 V DD VDD Logic Supply Voltage

25 D IN DIN Data In Logic Input

26 CLK CLK Clock Logic Input for Shift Register

27 D OUT DOUT Data Out Logic Output

28 NC NC No Connection

29 V PP VPP Positive Supply Voltage

30 NC NC No Connection

NN VNN Negative Supply Voltage

32 NC NC No Connection

33 NC RGND No Connection/Ground for Bleed Resistor

34 NC NC No Connection

35 SW15B SW15B Analog Switch 15 Terminal B

36 SW15A SW15A Analog switch 15 Terminal A

37 NC NC No Connection

38 SW14B SW14B Analog Switch 14 Terminal B

39 SW14A SW14A Analog Switch 14 Terminal A

40 NC NC No Connection

41 SW13B SW13B Analog Switch 13 Terminal B

42 SW13A SW13A Analog switch 13 Terminal A

43 NC NC No Connection

44 SW12B SW12B Analog Switch 12 Terminal B

45 SW12A SW12A Analog Switch 12 Terminal A

46 NC NC No Connection

47 SW11B SW11B Analog Switch 11 Terminal B

48 SW11A SW11A Analog Switch 11 Terminal A

49 SW10B SW10B Analog Switch 10 Terminal B

50 SW10A SW10A Analog Switch 10 Terminal A

51 NC NC No Connection

52 SW9B SW9B Analog Switch 9 Terminal B

53 SW9A SW9A Analog Switch 9 Terminal A

54 NC NC No Connection

DS20006082A-page 10  2019 Microchip Technology Inc.

55 SW8B SW8B Analog Switch 8 Terminal B

56 SW8A SW8A Analog Switch 8 Terminal A

57 NC NC No Connection

58 SW7B SW7B Analog Switch 7 Terminal B

59 SW7A SW7A Analog Switch 7 terminal A

60 NC NC No Connection

61 SW6B SW6B Analog Switch 6 Terminal B

62 SW6A SW6A Analog Switch 6 Terminal A

63 NC NC No Connection

64 SW5B SW5B Analog Switch 5 Terminal B

VSUB (Thermal Pad) The central thermal pad on the bottom of package must be connected to VNN externally Pin Number Symbol

 2019 Microchip Technology Inc. DS20006082A-page 11 HV2621/HV2721/HV2722

3.0 TEST CIRCUIT EXAMPLES

This section details a few example of test circuits. FIGURE 3-1: Switch Off Leakage per Switch. FIGURE 3-2: DC Offset Switch On/Off. FIGURE 3-3: TON/TOFF Test Circuit. FIGURE 3-4: Off Isolation. FIGURE 3-5: Switch Crosstalk. I FIGURE 3-6: Isolation Diode Current. VPP -1V RGNDOpen VPP 5V VNN VPP VNN VDD Open ISOL GND RGND VPP 5V VNN VPP VNN VDD GND VOUT RLOAD RGND GND VPP -1V 0kΩ VOUT RLOAD VPP VNN VPP VNN VDD RGND KO = 20Log VOUT VIN VIN = 10VP-P @5MHz GND VOUT RLOAD VPP VNN VPP VNN VDD RGND VIN = 10VP-P @5MHz NC GND 50Ω 50Ω VPP VNN VPP VNN VDD KCR = 20Log VOUT VIN RGND IID GND VNN VSIG VPP VNN VPP VNN VDD

DS20006082A-page 12  2019 Microchip Technology Inc. FIGURE 3-7: Output Voltage Spike. FIGURE 3-8: Charge Injection. RGND GND VOUT 1kΩ RLOAD 50Ω +VSPK –VSPK VPP VNN VPP VNN VDD RGND Q = 1000pF x ΔVOUT GND VPP VNN VPP VNN VDD VOUT ΔVOUT 1000pF VSIG

 2019 Microchip Technology Inc. DS20006082A-page 13 HV2621/HV2721/HV2722

4.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, VPP = +150V, VNN = -150V, VDD = 5.0V, TA =2 5°C. FIGURE 4-1: IPP/INN vs. Switching Frequency. FIGURE 4-2: IPPQ/INNQ vs. Temperature. FIGURE 4-3: IDDQ vs. Temperature. FIGURE 4-4: TON/TOFF vs. Temperature. FIGURE 4-5: IDD vs. CLK Frequency. FIGURE 4-6: KO vs. Frequency with 50Ω Load. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. ,33,11 6ZLWFKLQJ)UHTXHQF\\ N+] ,SS ,QQ ,33 ,11 ,334,114 7HPSHUDWXUH ,3346:2II ,1146:2II ,3346:2Q ,1146:2Q ,3346:2II ,1146:2II ,3346:2Q ,1146:2Q ,''4 7HPSHUDWXUH ,''4,''4 72172)) 7HPSHUDWXUH 7RQ 7RII72)) 721 ,'' &ORFN)UHTXHQF\\ 0+] &ORFN)UHTXHQF\\ 0+]

DS20006082A-page 14  2019 Microchip Technology Inc.

5.0 DETAILED DESCRIPTION AND

APPLICATION INFORMATION

5.1 Device Overview

The HV2621/HV2721/HV2722 are 300V, low-charge injection, 16-channel, high-voltage analog switches. The high-voltage analog switches are used for multiplexing a piezoelectric transducer array in a probe to multiple channel transmitters (Tx) arrays in a medical ultrasound system. The HV2621/HV2721/HV2722 are distinguished by bleed resistors that eliminate voltage build-up in capacitance load such as piezoelectric transducers. These devices can pass ±135V high-voltage large signal with V PP/VNN = ±150V. These devices have typical 18Ω on-resistance and 50 MHz bandwidth for small-signals. Figure 5-1 shows a typical medical ultrasound image system consisting 64-channels of transmit pulsers, 64-channels of receivers (LNA and ADC) and 64-channels of T/R switches connecting to 192 ele- ments of an ultrasound probe via a HV2XXX high-voltage analog switch array. FIGURE 5-1: Typical Medical Ultrasound Imaging System.

5.2 Logic Input Timing

The HV2621/HV2721/HV2722 have digital serial interface consisting of Data In (DIN), Clock (CLK), Data Out (D OUT), Latch Enable (LE ), and Clear (CLR) to control 16 switches individually. The digital circuits are supplied by V DD. The serial clock frequency is up to 33 MHz. The switch state configuration data is shifted into the shift registers at the rising edge (low-to-high transition) of the clock. The switch configuration bit of SW15 is shifted in first and the configuration bit of SW0 is shifted in last. To change all the switch states at the same time, the Latch Enable Input (LE ) should remain high while the 16-bit Data In signal is shifted into the 16-bit register. After the valid 16-bit data completes shifting into the shift registers, the high-to-low transi- tion of the LE signal transfers the contents of the shift registers into the latches. Finally, setting the LE high again, allows all the latches to keep the current state while new data can now be shifted into the shift registers without disturbing the latches. It is recommended to change all the latch states at the same time through this method to avoid possible clock feed through noise (see Figure 5-2 for details). When the CLR input is set high, it resets the data of all 16 latches to low. Consequently, all the high-voltage switches are set to OFF state. However, the CLR signal does not affect the contents of the shift register, so the shift register can operate regardless of the CLR signal. Therefore, when the CLR input is low, the shift register still retains the previous data. Tx Rx Tx Rx Tx Rx FPGA Ctrl Logic CPU MEMORY E65 E192 E128 VIDEO E129 E66 E130 E64 CH1 CH2 CH64 ADC ADC ADC HV 2XXX SW Array PZT Array Tx / Rx Array T/R Switch T/R Switch T/R Switch

 2019 Microchip Technology Inc. DS20006082A-page 15 HV2621/HV2721/HV2722 FIGURE 5-2: Latch Enable Timing Diagram.

5.3 Multiple Devices Connection

The digital serial interface of the HV2621/ HV2721/HV2722 allows multiple devices to make a daisy-chain together. In this configuration, D OUT of a device is connected to the D IN of the subsequent device, and so forth. The last D OUT of the daisy-chained HV2621/HV2721/HV2722 can be either floating or fed back to an FPGA to check the previously stored data in the shift registers. To control all the high-voltage analog switch states in daisy-chained N devices, N-times 16 clocks and N-times 16 bits of data are shifted into shift registers, while LE remains high and CLR remains low. After all the data finishes shifting in, one single negative pulse of LE transfers the data from all the shift registers to all the latches simultaneously. Consequently, all N-times 16 high-voltage analog switches change states simultaneously.

5.4 Power Up/Down Sequence and

The recommended power up sequence is V DD, V PP and V NN. The power down sequence is in reverse order. We also recommend the rise time and fall time of power supplies are greater than 1 msec. During the power up/down period, all the analog switch inputs should be within between V PP and VNN or floating. It is recommended that 0.1 µF or larger ceramic decoupling capacitors, with the appropriate voltage ratings, be connected between GND and other supplies (V PP, V NN and V DD). These decoupling capacitors should be placed as close as possible to the device. W:/( W6' W+W68 W'2 6KLIW5HJLVWHU'DWDIURP3UHYLRXV'DWD,QSXWVDUH6KLIWHG2XW &/. '287 ',1

DS20006082A-page 16  2019 Microchip Technology Inc.

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

Legend: XX...X Product Code or Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo. 64-Pin QFN (9 x 9 mm) Example XXXXXXXXXXX XXXXXXXXXXX YYWWNNN XXXXXXXXXXX PIN 1 PIN 1 HV2621 1826256

 2019 Microchip Technology Inc. DS20006082A-page 17 HV2621/HV2721/HV2722 BA 0.25 C 0.25 C

0.10 C A B

0.05 C (DATUM B) (DATUM A) C SEATING PLANE NOTE 1 N 2X TOP VIEW SIDE VIEW BOTTOM VIEW NOTE 1 N 0.10 C 0.08 C Microchip Technology Drawing C04-149D [R4X] Sheet 1 of 2 64X For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 64-Lead Very Thin Plastic Quad Flat, No Lead Package (R4X) – 9x9x0.9 mm Body [VQFN] With 7.15 x 7.15 Exposed Pad [Also called QFN] 9.00 9.00 e e 64X b K L A (A3)

DS20006082A-page 18  2019 Microchip Technology Inc. REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 0.500.30 0.40Contact Length L Contact-to-Exposed Pad K - 0.20 - Overall Height Overall Length Exposed Pad Width Contact Thickness Number of Pins Contact Width Exposed Pad Length Overall Width Standoff Pitch b D E 7.257.05 7.15

9.00 BSC

0.25 7.157.05 0.18 7.25 0.30 0.02

0.20 REF

0.00 0.05 Dimension Limits e A N Units MAXMIN NOM

0.50 BSC

0.90 0.80 1.00 MILLIMETERS Microchip Technology Drawing C04-149D [R4X] Sheet 2 of 2 64-Lead Very Thin Plastic Quad Flat, No Lead Package (R4X) – 9x9x0.9 mm Body [VQFN] With 7.15 x 7.15 Exposed Pad [Also called QFN]

 2019 Microchip Technology Inc. DS20006082A-page 19 HV2621/HV2721/HV2722 RECOMMENDED LAND PATTERN Dimension Limits Units Optional Center Pad Width Contact Pad Spacing Optional Center Pad Length Contact Pitch 7.25 7.25 MILLIMETERS E MAX 9.00 Contact Pad Length (X64) Contact Pad Width (X64) 0.95 0.30 Microchip Technology Drawing C04-149C [R4X] NOM C1Contact Pad Spacing 9.00 Contact Pad to Center Pad (X64) G1 0.40 Thermal Via Diameter V Thermal Via Pitch EV 0.33 1.20 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: E E EV EV Spacing Between Contact Pads (X60) G2 0.20 ØV SILK SCREEN 64-Lead Very Thin Plastic Quad Flat, No Lead Package (R4X) – 9x9x0.9 mm Body [VQFN] With 7.15 x 7.15 Exposed Pad [Also called QFN]

DS20006082A-page 20  2019 Microchip Technology Inc. NOTES:

 2019 Microchip Technology Inc. DS20006082A-page 21 HV2621/HV2721/HV2722 APPENDIX A: REVISION HISTORY Revision A (September 2019)

• Original release of this document

DS20006082A-page 22  2019 Microchip Technology Inc. NOTES:

 2019 Microchip Technology Inc. DS20006082A-page 23 HV2621/HV2721/HV2722 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. /XX PackageDevice Device: HV2621: 300V, Low-Charge Injection 16-Channel High- Voltage Analog Switch HV2721: 300V, Low-Charge Injection 16-Channel High- Voltage Analog Switch with Bleed Resistor at Both Sides of Switch HV2722: 300V, Low-Charge Injection 16-Channel High- Voltage Analog Switch with Bleed Resistor at One Side of Switch Package: R4X= Very Thin Plastic Quad Flat Pack, No Lead Package – 9x9x0.9 mm Body, 64-Lead (QFN) Examples: a) HV2621/R4X: 16-Channel High-Voltage Analog Switch, 64-lead QFN

DS20006082A-page 24  2019 Microchip Technology Inc. NOTES:

 2019 Microchip Technology Inc. DS20006082A-page 25 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP , INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2019, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-5019-1 Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions.
• There are dishonest and possibly illegal me thods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

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