HV2662

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Document overview

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• PDF pages: 16

Technical content

Features

• 24 Channels of high voltage analog switch
• 3.3 or 5.0V CMOS input logic level
• 24 Channel SPST configuration
• 20 MHz data shift clock frequency
• HVCMOS technology for high performance
• Very low quiescent power dissipation-10µA
• Low parasitic capacitance
• DC to 50 MHz analog signal frequency
• -60dB typical OFF-isolation at 5.0 MHz
• CMOS logic circuitry for low power
• Excellent noise immunity
• Cascadable serial data register with latches
• Flexible operating supply voltages
• Integrated bleed resistors on outputs (HV2762 only)

Applications

• Medical ultrasound imaging
• Piezoelectric transducer drivers
• Inkjet printer heads
• Optical MEMS modules

Description

HV2662/HV2762 are low-charge injection, 24-channel, hi gh-voltage analog switch in tegrated circuits (ICs). These ICs excel in applications requiring high-voltage switching controlled by low-voltage control signals such as medical ultrasound imaging, piezoelectric trans - ducer driver, and printers. HV2762 provides integrated bl eed resistors that eliminate voltage build-up on capacitive loads such as piezoelectric transducers. HV2662 does not have integrated bleed resistors. HV2662/HV2762 shift input data into a 24-bit shift reg- ister that can then be retained in a 24-bit latch. To redu ce any possible clock feed through noise, the latch-enable bar should be left high until all bits are clocked in during the rising edge of the clock. Using High Voltage CMOS technology, these ICs combine high-voltage, bilateral DMOS switches and low-power CMOS logic to provide efficient control of high voltage analog signals. The device is suitable for various combinations of high volt age supplies, e.g., V PP/VNN: +40V/-160V, +100V/- 100V, and +160V/-40V. Package Types 64-ball VFBGA See Table 2-1 for pin information 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K Top View HV2662 / HV2762 Low Harmonic Distortion, 24-Channel SPST High Voltage Analog Switch

DS20005372A-page 2  2016 Microchip Technology Inc. Block Diagram SW0 SW1 SW2 Level ShiftersLatches 24-Bit Shift Register CLK DIN DOUT VDD GND LE CLR VPP VNN RGND Output Switches D LE CLR D LE CLR D LE CLRD LE CLR D LE CLR SW22 SW23 Bleed Resistors Note: Bleed resistors and RGND only apply to HV2762.

 2016 Microchip Technology Inc. DS20005372A-page 3 HV2662 / HV2762

1.0 ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS† † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Notes 1– 3) Symbol Parameter Value VDD Logic power supply voltage 3.0V to 5.5V (Note 2) VPP Positive high voltage supply +40V to VNN +200V (Note 2) VNN Negative high voltage supply -40V to -160V (Note 2) VIH High level input voltage 0.9VDD to VDD VIL Low level input voltage 0V to 0.1 VDD VSIG Analog signal voltage peak-to-peak VNN +10V to VPP -10V (Note 3) TA Operating free air temperature 0°C to 70°C Note 1: Power up /down sequence is arbitrary except GND must be powered-up first and powered-down last. 2: Rise an d fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. 3: VSIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transition. DC ELECTRICAL CHARACTERISTICS Electrical Specifications: Over recommended operating conditions unless otherwise specified.  See test circuits Figure 3-2 Parameter Symbol 0°C 25°C 70°C Units Conditions Min Max Min Typ Max Min Max Small signal switch  ON-resistance RONS - - - 26 - - - Ω ISIG = 5.0mA VPP = +40V, VNN = -160V- - - 22 - - - ISIG = 200mA - - - 22 - - - ISIG = 5.0mA VPP = +100V, VNN = -100V- - - 18 - - - ISIG = 200mA - - - 20 - - - ISIG = 5.0mA VPP = +160V, VNN = -40V- - - 16 - - - ISIG = 200mA Small signal switch ON-resistance matching ∆RONS - 20 - 5.0 20 - 20 % ISIG = 5.0mA, VPP = +100V, VNN = -100V Large signal switch ON-resistance RONL - - - 30 - - - Ω VSIG = VPP -10V, ISIG = 1A (Note 1) Output-switch shunt resist ance (HV2762 onl RINT - - 20 35 50 - - KΩ Output switch to RGND, IRINT =0.5 mA

DS20005372A-page 4  2016 Microchip Technology Inc. Note 1: Specification is obtained by characterization and is not 100% tested. 2: Design guidance only Switch OFF-leakage per switch ISOL - 5.0 - 1.0 10 - 15 μA VSIG = VPP -10V, VNN +10V DC offset switch OFF VOS - 300 - 100 300 - 300 mV No load for HV2762.  RLOAD = 100 KΩ for HV2662 DC offset switch ON - 500 - 100 500 - 500 Quiescent VPP supply current IPPQ - - - 10 50 - - μA All switches OFF Quiescent VNN supply current Quiescent VPP supply current IPPQ - - - 10 50 - - μA All switches ON,  ISW = 5.0mA Quiescent VNN supply current Switch output peak current ISW - - - 2.0 1.3 - - A VSIG duty cycle < 0.1% (Note 1) Output switching fre- quency fSW - - - - 50 - - kHz Duty cycle = 50% (Note 1) Average VPP supply current VNN = -160V All output switches are turning ON and OFF at 50 kHz with no load VNN = -100V VNN = -40V Average VNN supply current VNN = -160V All output switches are turning ON and OFF at 50 kHz with no load VNN = -100V VNN = -40V Average VDD supply current Quiescent VDD supply current IDDQ - 10 - - 10 - 10 μA All logic inputs are static Logic input capacitance CIN - 10 - - 10 - 10 pF (Note 2) DC ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Over recommended operating conditions unless otherwise specified.  See test circuits Figure 3-2 Parameter Symbol 0°C 25°C 70°C Units Conditions Min Max Min Typ Max Min Max

AC ELECTRICAL CHARACTERISTICS Electrical Specifications: Over recommended operating conditions unless otherwise specified.  See test circuits Figure 3-2 Parameter Symbol 0°C 25°C 70°C Units Conditions Min Max Min Typ Max Min Max Set up time before LE rises tSD 25 - 25 - - 25 - ns (Note 1) Time width of LE tWLE 56 - 56 - - 56 - ns VDD = 3.0V (Note 1) 12 - 12 - - 12 - VDD = 5.0V (Note 1) Clock delay time to dat a out tDO 9.0 40 9.0 - 40 9.0 40 ns VDD = 3.0V (Note 1) 8.0 30 8.0 - 30 8.0 30 VDD = 5.0V (Note 1) Time width of CLR tWCLR 55 - 55 - - 55 - ns (Note 1) Set up time data to clock t SU 21 - 21 - - 21 - ns VDD = 3.0V (Note 1) Hold time data from clock t H 5.0 - 5.0 - - 5.0 - ns VDD = 3.0V (Note 1) Clock frequency fCLK - 8 - - 8 - 8 MHz VDD = 3.0V - 20 - - 20 - 20 VDD = 5.0V (Note 1) Clock rise and fall ti mes tR, tF - 50 - - 50 - 50 ns (Note 1) Turn ON time tON - 5.0 - - 5.0 - 5.0 μs VSIG = VPP -10V, RLOAD = 10kΩTurn OFF time tOFF - 5.0 - - 5.0 - 5.0 Maximum VSIG slew rate dv/dt - 20 - - 20 - 20 V/ns VPP = +40V, VNN = -160V (Note 1) - 20 - - 20 - 20 VPP = +100V, VNN = -100V (Note 1) - 20 - - 20 - 20 VPP = +160V, VNN = -40V (Note 1) OFF isolation KO -30 - -30 -33 - -30 - dB f = 5.0 MHz,

1.0 KΩ//15 p

F load (Note 1) -58 - -58 -60 - -58 - f = 5.0 MHz, 50Ω load (Note 1) Switch crosstalk KCR -60 - -60 -70 - -60 - dB f = 5.0 MHz, 50Ω load (Note 1) Output switch isola- tion diode current IID - 300 - - 300 - 300 mA 300 ns pulse width, 2.0% duty cycle (Note 1) OFF capacitance SW to GND CSG(OFF) - 14 - 9.0 14 - 14 pF VSIG = 0V, f = 1.0 MHz (Note 1) ON capacitance SW to GND CSG(ON) - 17 - 12 17 - 17 Output voltage spike (per switch) +VSPK - - - - 150 - - mV VPP = +40V, VNN = -160V RLOAD = 50Ω (Note 1)-VSPK - - - - 150 - - +VSPK - - - - 150 - - VPP = +100V, VNN = -100V RLOAD = 50Ω (Note 1)-VSPK - - - - 150 - - +VSPK - - - - 150 - - VPP = +160V, VNN = -40V RLOAD = 50Ω (Note 1)-VSPK - - - - 150 - - Charge injection (per switch) QC - - - 820 - - - pC VPP = +40V, VNN = -160V (Note 1) (Note 1) (Note 1)  2016 Microchip Technology Inc. DS20005372A-page 5 HV2662 / HV2762 Note 1: Specification is obtained by characterization and is not 100% tested.

TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise specified, for all specifications TA =TJ = +25°C Parameter Symbol Min Typ Max Units Conditions Temperature Ranges Storage Temperature TA -65 – 150 °C Package Thermal Resistances Thermal Resistance, 64-Ball VFBGA θ ja – 36 – °C/W HV2662 / HV2762 DS20005372A-page 6  2016 Microchip Technology Inc.

 2016 Microchip Technology Inc. DS20005372A-page 7 HV2662 / HV2762

2.0 PIN DESCRIPTION

The locations of the balls are listed in Package Types. TABLE 2-1: BALL DESCRIPTION 64-BALL VFBGA Pin # HV2662 HV2762 Description A1 SW22B SW22B Analog switch 22 terminal B A2 VNN VNN Negative supply voltage A3 SW21B SW21B Analog switch 21 terminal B A4 SW20B SW20B Analog switch 20 terminal B A5 SW19B SW19B Analog switch 19 terminal B A6 SW18B SW18B Analog switch 18 terminal B A7 SW17B SW17B Analog switch 17 terminal B A8 SW16B SW16B Analog switch 16 terminal B A9 SW15B SW15B Analog switch 15 terminal B A10 SW15A SW15A Analog switch 15 terminal A B1 SW23B SW23B Analog switch 23 terminal B B2 SW23A SW23A Analog switch 23 terminal A B3 SW22A SW22A Analog switch 22 terminal A B4 SW21A SW21A Analog switch 21 terminal A B5 SW20A SW20A Analog switch 20 terminal A B6 SW19A SW19A Analog switch 19 terminal A B7 SW18A SW18A Analog switch 18 terminal A B8 SW17A SW17A Analog switch 17 terminal A B9 SW16A SW16A Analog switch 16 terminal A B10 SW14B SW14B Analog switch 14 terminal B C1 NC NC No connect C2 VPP VPP Positive supply voltage C9 SW14A SW14A Analog switch 14 terminal A C10 SW13B SW13B Analog switch 13 terminal B D1 CLR CLR Latch clear logic input D2 NC RGND No connect/ Ground for bleed resistor D9 VNN VNN Negative supply voltage D10 SW13A SW13A Analog switch 13 terminal A E1 LE LE Latch-enable logic input, low active E2 CLK CLK Clock logic input for shift register E9 SW12B SW12B Analog switch 12 terminal B E10 SW12A SW12A Analog switch 12 terminal A F1 VDD VDD Logic supply voltage F2 GND GND Ground F9 SW11B SW11B Analog switch 11 terminal B F10 SW11A SW11A Analog switch 11 terminal A G1 DIN DIN Data-in logic input G2 DOUT DOUT Data-out logic output G9 SW10B SW10B Analog switch 10 terminal B G10 VNN VNN Negative supply voltage H1 NC RGND No connect/ Ground for bleed resistor H2 VPP VPP Positive supply voltage

DS20005372A-page 8  2016 Microchip Technology Inc. H9 SW10A SW10A Analog switch 10 terminal A H10 SW9B SW9B Analog switch 9 terminal B J1 SW0A SW0A Analog switch 0 terminal A J2 SW0B SW0B Analog switch 0 terminal B J3 SW1B SW1B Analog switch 1 terminal B J4 SW2B SW2B Analog switch 2 terminal B J5 SW3B SW3B Analog switch 3 terminal B J6 SW4B SW4B Analog switch 4 terminal B J7 SW5B SW5B Analog switch 5 terminal B J8 SW6B SW6B Analog switch 6 terminal B J9 SW7B SW7B Analog switch 7 terminal B J10 SW9A SW9A Analog switch 9 terminal A K1 SW1A SW1A Analog switch 1 terminal A K2 VNN VNN Negative supply voltage K3 SW2A SW2A Analog switch 2 terminal A K4 SW3A SW3A Analog switch 3 terminal A K5 SW4A SW4A Analog switch 4 terminal A K6 SW5A SW5A Analog switch 5 terminal A K7 SW6A SW6A Analog switch 6 terminal A K8 SW7A SW7A Analog switch 7 terminal A K9 SW8A SW8A Analog switch 8 terminal A K10 SW8B SW8B Analog switch 8 terminal B TABLE 2-1: BALL DESCRIPTION 64-BALL VFBGA (CONTINUED) Pin # HV2662 HV2762 Description

 2016 Microchip Technology Inc. DS20005372A-page 9 HV2662 / HV2762

3.0 FUNCTIONAL DESCRIPTION

FIGURE 3-1: LOGIC TIMING WAVEFORMS DATA IN DIN LE CLOCK DATA OUT DOUT OFF ON CLR VOUT (typ) 50% 50% 50% 50% tWLE tSD 50% 50% tSU th tOFF 50% tDO tON tWCL DN - 1DN DN + 1 50% 50% 90% 10% TABLE 3-1: TRUTH TABLE L - ... - - ... - L L OFF - ... - - ... X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X H ALL SWITCHES OFF Note 1: Serial data is clocked in on the L to H transition of the CLK 2: DOUT is high when data in the register 23 is high. 3: Shif t registers clocking has no effect on the switch states if LE is high. 4: Th e CLR clear input overrides all other inputs. 5: Th e 24 switches operate independently. 6: All 2 4 switches go to a state retaining th eir latched condition at the rising edge of LE. When LE is low, the shift registers data flow through the latch.

DS20005372A-page 10  2016 Microchip Technology Inc.

3.1 Application Information

FIGURE 3-2: TEST CIRCUITS DC Offset Switch ON/OFF VPP 5V VNN VPP VNN VDD GND VOUT TON/TOFF Test Circuit GND 10kΩ VOUT Output Switch Isolation Diode Current IID GND VNN VSIG Switch Crosstalk NC GND 50Ω Output Voltage Spike GND VOUT 1kΩ RLOAD 50Ω +VSPK –VSPK OFF Isolation GND VOUT 50Ω RLOAD RLOAD VPP VNN VPP VNN VDD VPP VNN VPP VNN VDD VPP VNN VPP VNN VDD VPP VNN VPP VNN VDDVPP VNN VPP VNN VDD KCR = 20Log VOUT VIN VPP -10V Switch Off Leakage per Switch RGNDOpen Q = 1000pF x ΔVOUT Charge Injection GND VPP VNN VPP VNN VDD VPP 5V VNN VPP VNN VDD Open ISOL GND VOUT ΔVOUT 1000pF RGND RGND RGND RGND RGND RGND RGND VPP -10V VIN =10VPP @5.0MHz KO = 20Log VOUT VIN VIN =10VPP @5.0MHz VSIG RLOAD 100kΩHV2662 only Note: RGND only applies to HV2762.

 2016 Microchip Technology Inc. DS20005372A-page 11 HV2662 / HV2762

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

Legend: XX...X Product Code or Cust omer-specific information Y Year code (last digit of calendar year)  YY Year code (last 2 digits of calendar year)  WW Week code (week of January 1 is week ‘01’)  NNN Alphanumeric traceability code  Pb-free JEDEC ® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part numbe r cannot be marked on one line, it will be carried over to the next line, t hus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo. 64-Ball VFBGA Example XXXXXXXXX XXXXXXX XXXXXXXXX YYWWNNN HV2662 03343e3 e3GA 15

Microchip Technology Drawing C04-370-GA Rev A Sheet 2 of 2 C NX Øb Ø0.15 C A B Ø0.05 C SOLDER BALL DETAIL A 0.10 C 0.08 C DETAIL A Number of Pins Overall Height Ball Diameter Overall Width Overall Length Overall Ball Pitch Overall Ball Pitch Molded Cap Thickness Pitch Standoff Units Dimension Limits A Øb D e E N

0.65 BSC

0.45 REF

0.25 0.16 0.30

7.00 BSC

5.85 BSC

0.35 1.00 0.25 MAX REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Dimensioning and tolerancing per ASME Y14.5M For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 64-Ball Very Thin Fine Pitch Ball Grid Array (GA) - 7x7x1.0 mm Body [VFBGA] Supertex Legacy HV2662 / HV2762 DS20005372A-page 12  2016 Microchip Technology Inc.

 2016 Microchip Technology Inc. DS20005372A-page 13 HV2662 / HV2762 APPENDIX A: REVISION HISTORY Revision A (May 2016)

• Converted Supertex Docs #’s DSFP-2662 and DSFP-HV2762 to Microchip DS20005372A.
• Merged HV2662 and HV2762 into one document.
• Updated “Product Identification System”. Removed parts with a package code of “LA”; Added package “GA”.
• EOL of 64-Ball LFGA package (LB).per PCN JAON-20WQKC840.
• Added information for 64-Ball VFBGA (GA) throughout.
• Minor text changes throughout.

DS20005372A-page 14  2016 Microchip Technology Inc. PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Device: HV2662 = 24-Channel, HV Analog Switch HV2762 = 24-Channel, HV Analog Switch with Bleed Resistors Package: GA = 64-ball VFBGA Environmental G = Lead (Pb)-free/RoHS-compliant package Media Type: (blank) = 120/Tray for GA package Examples: a) HV2662GA-G: 64-ball VFBGA package, 120/Tray b) HV2762GA-G: 64-ball VFBGA package, 120/Tray PART NO. X Device X Environmental XX Package Options Media - - Type

 2016 Microchip Technology Inc. DS20005372A-page 15 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application me ets with your specifications. MICROCHIP MAKES NO RE PRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting fr om such use. No licenses are conveyed, implicitly or ot herwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0648-8 Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal meth ods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC ® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==

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