HV2605FG-G-M931

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Document overview

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• PDF pages: 30

Technical content

Features

• 16-channel High-voltage Analog Switch
• Low Harmonic Distortion
• Integrated Bleed Resistors on the Outputs for HV2705
• 3.3V Input Logic Level Compatible
• –60 dB typical OFF-isolation at 5 MHz
• 20 MHz Data Shift Clock Frequency
• 10 µA Low-quiescent Power Dissipation
• Low Parasitic Capacitance
• DC to 50 MHz Small-signal Frequency Response
• CMOS logic Circuitry for Low Power
• Cascadable Serial Data Register with Latches
• Flexible Operating Supply Voltages

Applications

• Medical Ultrasound Imaging
• Non-destructive Metal Flaw Detection
• Piezoelectric Transducer Drivers
• Optical MEMS Modules

Description

The HV2605 and HV2705 are 16-channel low harmonic distortion hi gh-voltage analog switch integrated circuits (ICs). These devices are designed for applications requiring high-voltage switching controlled by low-voltage control signals, such as medical ultrasound imaging and other piezoelectric transducer drivers. The HV 2705 has integrated bleed resistors which eliminate voltage build-up on capacitive loads such as piezoelectric transducers. These ICs shift input data into a 16-bit Shift register that can then be retained in a 16-bit latch. To reduce any possible clock feed-through noise, the latch enable bar should be left high until all bits are clocked in. Data are clocked in during the rising edge of the clock. This device combines high-voltage, bilateral DMOS switches and low-power CMOS logic to provide efficient control of high-voltage analog signals. The device is suitable for various combinations of high- voltage supplies, e.g., V PP/VNN: +40V/–160V, +100V/–100V and +160V/–40V. Package Types† †N o t i c e : The LQFP package is not recommended for new designs. Please use TQFP package as an alternative. See Table 2-1 and Table 2-2 for pin information. 42-Ball Bumped Die (Top view) 123 89101213 4567 18 17 16 15 14 2526 2122 2324 1920 4142 3334 3940 3132 3738 2930 3536 2728 48-lead LQFP (Top view) 48-lead TQFP (Top view) HV2605/HV2705 16-Channel Low Harmonic Distortion High-Voltage Analog Switches

DS20005498C-page 2  2017-2022 Microchip Technology Inc. and its subsidiaries Functional Block Diagram D LE CLR Latches Level Shifters Output Switches SW0 SW1 SW2 SW14 SW15 16-Bit Shift Register RGNDVPPVNNCLRLEVDD GND D LE CLR D LE CLR D LE CLR D LE CLR DOUT CLK DIN Bleed Resistors HV2705 only

 2017-2022 Microchip Technology Inc. and its subsidiaries DS20005498C-page 3 HV2605/HV2705

1.0 ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS† Power Dissipation: Note 1: Power-up/power-down sequence is arbitrary except GND must be powered up first and powered down last. 2: VSIG must be within VNN VSIGVPP or floating during power-up/power-down transition. 3: Rise and fall times of power supplies VDD, VPP and VNN should not be less than 1 millisecond. †N o t i c e : Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Sym. Min. Typ. Max. Unit Conditions Logic Power Supply Voltage V DD 3— 5 . 5 V Note 1, Note 3 Positive High-voltage Supply V PP 40 — V NN+200V V Note 1, Note 3 Negative High-voltage Supply V NN –40 — –160 V Note 1, Note 3 High-level Input Voltage V IH 0.9 VDD —V DD V Low-level Input Voltage V IL 0 — 0.1 V DD V Analog Signal Voltage Peak-to-Peak V SIG VNN +10V — V PP–10V V Note 2

DS20005498C-page 4  2017-2022 Microchip Technology Inc. and its subsidiaries DC ELECTRICAL CHARACTERISTICS Electrical Specifications: Over recommended operating conditions unless otherwise noted. Parameter Sym. 0°C 25°C 70°C Unit Conditions Small Signal Switch ON-resistance RONS —3 0—2 63 8—4 8 Ω ISIG = 5 mA VPP = +40V VNN = –160V—2 5—2 22 7—3 2 Ω ISIG = 200 mA —2 5—2 22 7—3 0 Ω ISIG = 5 mA VPP = +100V VNN= –100V—1 8—1 82 4—2 7 Ω ISIG = 200 mA —2 3—2 02 5—3 0 Ω ISIG = 5 mA VPP = +160V VNN = –40V—2 2—1 62 5—2 7 Ω ISIG = 200 mA Small Signal Switch ON-resistance Matching ∆RONS —2 0— 5 2 0—2 0% ISIG = 5 mA, VPP = +100V, VNN = –100V Large Signal Switch ON-resistance RONL ——— 1 5——— Ω VSIG = VPP–10V, ISIG = 1A Output Bleed Resistor (HV2705 only) RINT — — 20 35 50 — — k Ω Output Switch to RGND IRINT = 0.5 mA Switch OFF Leakage per Switch ISOL —5—11 0 — 1 5 µ A VSIG = VPP–10V and VNN+10V (See Section 3.1 “Test Circuits”.) DC Offset Switch OFF VOS — 300 — 100 300 — 300 mV HV2605:100 kΩ load HV2705: No load (See Section 3.1 “Test Circuits”.) DC Offset Switch ON — 500 — 100 500 — 500 mV Quiescent V PP Supply Current IPPQ — — — 10 50 — — µA All switches off Quiescent VNN Supply Current INNQ — — — –10 –50 — — µA All switches off Quiescent VPP Supply Current IPPQ — — — 10 50 — — µA All switches on, I SW = 5 mA Quiescent VNN Supply Current INNQ — — — –10 –50 — — µA All switches on, I SW = 5 mA Switch Output Peak Current ISW —3—3 2—2A V SIG duty cycle < 0.1% Output Switching Frequency fSW — — — — 50 — — kHz Duty cycle = 50% Average VPP Supply Current I PP —6 . 5—— 7 — 8m A VPP = +40V VNN = –160V 50 kHz output switching frequency with no load PP = +100V VNN = –100V —4— —5— 5 . 5 m A VPP = +160V VNN = –40V Average VNN Supply Current I NN —6 . 5—— 7 — 8m A VPP = +40V VNN = –160V 50 kHz output switching frequency with no load PP = +100V VNN = –100V —4— —5— 5 . 5 m A VPP = +160V VNN = –40V Average VDD Supply Current I DD —4— —4—4 m A f CLK = 5 MHz, VDD = 5V Quiescent VDD Supply Current IDDQ — 10 — — 10 — 10 µA All logic inputs are static.

 2017-2022 Microchip Technology Inc. and its subsidiaries DS20005498C-page 5 HV2605/HV2705 Logic Input Capacitance CIN —1 0——1 0—1 0p F AC ELECTRICAL CHARACTERISTICS Electrical Specifications: VDD = 5V, tr = tf ≤ 5 ns, 50% duty cycle and CLOAD = 20 pF unless otherwise noted. Parameter Sym. 0°C 25°C 70°C Unit Conditions Set-up Time before Latch Enable Rises tSD 25 — 25 — — 25 — ns Time Width of LE tWLE 56 — — 56 — 56 — ns V DD = 3V 12 — — 12 — 12 — ns V DD = 5V Clock Delay Time to Data Out tDO 50 100 50 78 100 50 100 ns V DD = 3V 15 40 15 30 40 15 40 ns V DD = 5V Time Width of CLR t WCLR 55 — 55 — — 55 — ns Set-up Time Data to Clock t SU 21 — — 21 — 21 — ns V DD = 3V 7— —7—7— n s V DD = 5V Hold Time Data from Clock tH 2—2— —2— n s V DD = 3V or 5V Clock Frequency f CLK —1 0——1 0—1 0 M H z V DD = 3V —2 0——2 0—2 0 M H z V DD = 5V Clock Rise and Fall Times t r, tf — 50 — — 50 — 50 ns Turn ON Time T ON —5— —5—5µ s VSIG = VPP–10V, RLOAD = 10 kΩ (See Section 3.1 “Test Circuits”.) Turn OFF Time T OFF —5— —5—5µ s VSIG = VPP–10V, RLOAD = 10 kΩ (See Section 3.1 “Test Circuits”.) Maximum VSIG Slew Rate dv/dt — 20 — — 20 — 20 V/ns VPP = +40V, VNN = –160V — 20 — — 20 — 20 V/ns VPP = +100V, VNN = –100V — 20 — — 20 — 20 V/ns VPP = +160V, VNN = –40V OFF Isolation K O f = 5 MHz, 1 kΩ//15 pF load (See Section 3.1 “Test Circuits”.) f = 5 MHz, 50Ω load (See Section 3.1 “Test Circuits”.) Switch Crosstalk K CR –60 — –60 –70 — –60 — dB f = 5 MHz, 50Ω load (See Section 3.1 “Test Circuits”.) DC ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Over recommended operating conditions unless otherwise noted. Parameter Sym. 0°C 25°C 70°C Unit Conditions

DS20005498C-page 6  2017-2022 Microchip Technology Inc. and its subsidiaries Output Switch Isolation Diode Current IID — 300 — — 300 — 300 mA 300 ns pulse width, 2% duty cycle (See Section 3.1 “Test Circuits”.) OFF Capacitance SW to GND CSG(OFF) — 15 — 10 15 — 15 pF 0V, f = 1 MHz ON Capacitance SW to GND CSG(ON) — 18 — 13 18 — 18 pF 0V, f = 1 MHz Output Voltage Spike +VSPK ———— 150 —— mV VPP = +40V, VNN = –160V, RLOAD = 50Ω (See Section 3.1 “Test +VSPK ———— 150 —— mV VPP = +100V, VNN = –100V, RLOAD = 50Ω (See Section 3.1 “Test Circuits”.) +VSPK ———— 150 —— mV VPP = +160V, VNN = –40V, RLOAD = 50Ω (See Section 3.1 “Test Circuits”.) Charge Injection QC VPP = +40V, VNN = –160V, VSIG = 0V (See Section 3.1 “Test Circuits”.) VPP = +100V, VNN = –100V, VSIG = 0V (See Section 3.1 “Test Circuits”.) VPP = +160V, VNN = –40V, VSIG = 0V (See Section 3.1 “Test Circuits”.) AC ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: VDD = 5V, tr = tf ≤ 5 ns, 50% duty cycle and CLOAD = 20 pF unless otherwise noted. Parameter Sym. 0°C 25°C 70°C Unit Conditions

 2017-2022 Microchip Technology Inc. and its subsidiaries DS20005498C-page 7 HV2605/HV2705 TEMPERATURE SPECIFICATIONS Note 1: Mounted on an FR-4 board, 25 mm x 25 mm x 1.57 mm Timing Waveforms Electrical Specifications: Unless otherwise specified, for all specifications TA = TJ = +25°C. Parameter Sym. Min. Typ. Max. Unit Conditions TEMPERATURE RANGE Operating Ambient Temperature T A 0— 7 0° C Storage Temperature T S –65 — 150 °C PACKAGE THERMAL RESITANCE 48-lead LQFP θJA —5 2— ° C / W Note 1 DATA IN DIN LE CLOCK CLK DATA OUT DOUT OFF VOUT (typ) ON CLR 50% 50% 50% 50% tWLE tSD tSU th 50% 50% tOFF 50% tDO DO tON tWCL DN+1 DN DN-1 50%50% 90% 10%

DS20005498C-page 8  2017-2022 Microchip Technology Inc. and its subsidiaries

2.0 PIN DESCRIPTION

The description of pins in the 42-ball bumped die, 48- lead TQFP and 48-lead LQFP packages are listed on Table 2-1 and Table 2-2, respectively. The locations of the pads/balls are listed in Package Types†. TABLE 2-1: 42-BALL BUMPED DIE PIN FUNCTION TABLE Pin Number HV2605 Pin Name HV2705 Pin Name Description

1 NC — No connection

— RGND Ground for bleed resistor

2 VPP VPP Positive supply voltage

3 VNN VNN Negative supply voltage

4 DOUT DOUT Data out logic output

5 CLR CLR Latch clear logic input

6 CLK CLK Clock logic input for Shift register

7 GND GND Ground

8 SW15A SW15A Analog Switch 15 Terminal A

9 SW15B SW15B Analog Switch 15 Terminal B

LE Latch enable logic input, low active

11 VDD VDD Logic supply voltage

12 SW0A SW0A Analog Switch 0 Terminal A

13 SW0B SW0B Analog Switch 0 Terminal B

14 SW14A SW14A Analog Switch 14 Terminal A

15 SW14B SW14B Analog Switch 14 Terminal B

16 DIN DIN Data in logic input

17 SW1A SW1A Analog Switch 1 Terminal A

18 SW1B SW1B Analog Switch 1 Terminal B

19 SW13A SW13A Analog Switch 13 Terminal A

20 SW13B SW13B Analog Switch 13 Terminal B

21 SW2A SW2A Analog Switch 2 Terminal A

22 SW2B SW2B Analog Switch 2 Terminal B

23 SW12A SW12A Analog Switch 12 Terminal A

24 SW12B SW12B Analog Switch 12 Terminal B

25 SW3A SW3A Analog Switch 3 Terminal A

26 SW3B SW3B Analog Switch 3 Terminal B

27 SW11A SW11A Analog Switch 11 Terminal A

28 SW11B SW11B Analog Switch 11 Terminal B

29 SW9B SW9B Analog Switch 9 Terminal B

30 SW8B SW8B Analog Switch 8 Terminal B

31 SW7A SW7A Analog Switch 7 Terminal A

32 SW6A SW6A Analog Switch 6 Terminal A

33 SW4A SW4A Analog Switch 4 Terminal A

34 SW4B SW4B Analog Switch 4 Terminal B

35 SW10B SW10B Analog Switch 10 Terminal B

36 SW10A SW10A Analog Switch 10 Terminal A

37 SW9A SW9A Analog Switch 9 Terminal A

38 SW8A SW8A Analog Switch 8 terminal A

 2017-2022 Microchip Technology Inc. and its subsidiaries DS20005498C-page 9 HV2605/HV2705

39 SW7B SW7B Analog Switch 7 Terminal B

40 SW6B SW6B Analog Switch 6 Terminal B

41 SW5B SW5B Analog Switch 5 Terminal B

42 SW5A SW5A Analog Switch 5 Terminal A

TABLE 2-1: 42-BALL BUMPED DIE PIN FUNCTION TABLE Pin Number HV2605 Pin Name HV2705 Pin Name Description TABLE 2-2: 48-LEAD TQFP/LQFP PIN FUNCTION TABLE Pin Number HV2605 Pin Name HV2705 Pin Name Description

1 NC NC No connection

2 NC NC No connection

3 SW4B SW4B Analog Switch 4 Terminal B

4 SW4A SW4A Analog Switch 4 Terminal A

5 SW3B SW3B Analog Switch 3 Terminal B

6 SW3A SW3A Analog Switch 3 Terminal A

7 SW2B SW2B Analog Switch 2 Terminal B

8 SW2A SW2A Analog Switch 2 Terminal A

9 SW1B SW1B Analog Switch 1 Terminal B

10 SW1A SW1A Analog Switch 1 Terminal A

11 SW0B SW0B Analog Switch 0 Terminal B

13 VNN VNN Negative supply voltage

14 NC NC No connection

15 VPP VPP Positive supply voltage

16 NC NC No connection

17 GND GND Ground

18 VDD VDD Logic supply voltage

19 DIN DIN Data in logic input

20 CLK CLK Clock logic input for Shift register

LE Latch-enable logic input, low active

22 CLR CLR Latch clear logic input

23 DOUT DOUT Data out logic output

24 NC — No connection

— RGND Ground for bleed resistor

25 SW15B SW15B Analog Switch 15 Terminal B

26 SW15A SW15A Analog Switch 15 Terminal A

27 SW14B SW14B Analog Switch 14 Terminal B

28 SW14A SW14A Analog Switch 14 Terminal A

29 SW13B SW13B Analog Switch 13 Terminal B

30 SW13A SW13A Analog Switch 13 Terminal A

31 SW12B SW12B Analog Switch 12 Terminal B

32 SW12A SW12A Analog Switch 12 Terminal A

33 SW11B SW11B Analog Switch 11 Terminal B

34 SW11A SW11A Analog Switch 11 Terminal A

DS20005498C-page 10  2017-2022 Microchip Technology Inc. and its subsidiaries

35 NC NC No connection

36 NC NC No connection

37 SW10B SW10B Analog Switch 10 Terminal B

38 SW10A SW10A Analog Switch 10 Terminal A

39 SW9B SW9B Analog Switch 9 Terminal B

40 SW9A SW9A Analog Switch 9 Terminal A

41 SW8B SW8B Analog Switch 8 Terminal B

42 SW8A SW8A Analog Switch 8 Terminal A

43 SW7B SW7B Analog Switch 7 Terminal B

44 SW7A SW7A Analog Switch 7 Terminal A

45 SW6B SW6B Analog Switch 6 Terminal B

46 SW6A SW6A Analog Switch 6 Terminal A

47 SW5B SW5B Analog Switch 5 Terminal B

48 SW5A SW5A Analog Switch 5 Terminal A

TABLE 2-2: 48-LEAD TQFP/LQFP PIN FUNCTION TABLE Pin Number HV2605 Pin Name HV2705 Pin Name Description

 2017-2022 Microchip Technology Inc. and its subsidiaries DS20005498C-page 11 HV2605/HV2705

3.0 FUNCTIONAL DESCRIPTION

3.1 Test Circuits

Figure 3-1 to Figure 3-8 show the test circuits for HV2605/HV2705. FIGURE 3-1: Switch Off Leakage per Switch. FIGURE 3-2: Switch DC Offset. FIGURE 3-3: TON/TOFF Test Circuit. FIGURE 3-4: Off Isolation. FIGURE 3-5: Output Switch Isolation Diode Current. FIGURE 3-6: Switch Crosstalk. VPP -10V RGNDOpen VPP 5V VNN VPP VNN VDD Open ISOL GND RGND VPP 5V VNN VPP VNN VDD GND VOUT RLOAD (HV2605 only) RGND GND VPP -10V 10kΩ VOUT RLOAD VPP VNN VPP VNN VDD RGND KO = 20Log VOUT VIN VIN = 10VP-P @5MHz GND VOUT RLOAD VPP VNN VPP VNN VDD RGND IID GND VNN VSIG VPP VNN VPP VNN VDD RGND VIN = 10VP-P @5MHz NC GND 50Ω 50Ω VPP VNN VPP VNN VDD KCR = 20Log VOUT VIN

 2017-2022 Microchip Technology Inc. and its subsidiaries DS20005498C-page 13 HV2605/HV2705 Note 1: The 16 switches operate independently. 2: Serial data is clocked in on the low-to-high transition of the clock. 3: All 16 switches go to a state retaining th eir latched condition at the rising edge of LE . When LE is low, the Shift registers data flow through the latch. 4: DOUT is high when data in the Shift register 15 is high. 5: Shift registers clocking has no effect on the switch states if LE is high. 6: The CLR clear input overrides all other inputs. TABLE 3-1: TRUTH FUNCTION TABLE ... ... —L L O F F — ... ... X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X H ALL SWITCHES OFF

DS20005498C-page 14  2017-2022 Microchip Technology Inc. and its subsidiaries

4.0 PACKAGING INFORMATION †

4.1 Package Marking Information

†N o t i c e : The LQFP package is not recommended for new designs. Please use TQFP package as an alternative. Legend: XX...X Product Code or Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC ® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part nu mber cannot be marked on one line, it will be carried over to the next line, th us limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo. XXXXXXX XXXXX^^ YYWWNNN HV2605 BD^^ 2126256 HV2705 BD^^ 2126256 42-Ball Bumped Die Example Example XXXXXX XXXXXX ^^YYWW NNN HV 2605FG ^^2126 256 HV 2705FG ^^2126 256 48-Lead LQFP Example Example XXXXXX XXXXXX YYWWNNN HV 2605TQ 2126256 HV 2705TQ 2126256 48-Lead TQFP Example Example

 2017-2022 Microchip Technology Inc. and its subsidiaries DS20005498C-page 15 HV2605/HV2705 /g37/g36 /g19/g17/g20/g19/g38 /g19/g17/g20/g19/g38 /g19/g17/g19/g26/g38/g36/g37 /g19/g17/g19/g24/g38 /g38 /g21/g59 /g55/g50/g51/g3/g57/g44/g40/g58 /g54/g44/g39/g40/g3/g57/g44/g40/g58 /g37/g50/g55/g55/g50/g48/g3/g57/g44/g40/g58 /g49 /g19/g17/g20/g19/g38 /g19/g17/g19/g27/g38 /g54/g75/g72/g72/g87/g3/g20/g3/g82/g73/g3/g21 /g21/g59 /g23/g21/g59 /g41/g82/g85/g3/g87/g75/g72/g3/g80/g82/g86/g87/g3/g70/g88/g85/g85/g72/g81/g87/g3/g83/g68/g70/g78/g68/g74/g72/g3/g71/g85/g68/g90/g76/g81/g74/g86/g15/g3/g83/g79/g72/g68/g86/g72/g3/g86/g72/g72/g3/g87/g75/g72/g3/g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g51/g68/g70/g78/g68/g74/g76/g81/g74/g3/g54/g83/g72/g70/g76/g73/g76/g70/g68/g87/g76/g82/g81/g3/g79/g82/g70/g68/g87/g72/g71/g3/g68/g87 /g75/g87/g87/g83/g29/g18/g18/g90/g90/g90/g17/g80/g76/g70/g85/g82/g70/g75/g76/g83/g17/g70/g82/g80/g18/g83/g68/g70/g78/g68/g74/g76/g81/g74 /g49/g82/g87/g72/g29 /g23/g21/g16/g37/g68/g79/g79/g3/g38/g75/g76/g83/g3/g54/g70/g68/g79/g72/g3/g51/g68/g70/g78/g68/g74/g72/g3/g11/g26/g24/g59/g12/g3/g16/g3/g24/g17/g21/g28/g91/g24/g17/g22/g19/g91/g20/g17/g19/g21/g3/g80/g80/g3/g37/g82/g71/g92/g3/g62/g38/g54/g51/g64 /g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g55/g72/g70/g75/g81/g82/g79/g82/g74/g92/g3/g39/g85/g68/g90/g76/g81/g74/g3/g38/g19/g23/g16/g24/g22/g22/g16/g26/g24/g59/g3/g53/g72/g89/g3/g37 /g54/g40/g36/g55/g44/g49/g42 /g51/g47/g36/g49/g40 /g11/g39/g36/g55/g56/g48/g3/g36/g12 /g11/g39/g36/g55/g56/g48/g3/g37/g12 /g49/g50/g55/g40/g3/g20 /g19/g17/g19/g19 /g19/g17/g22/g19 /g19/g17/g25/g19 /g20/g17/g21/g19 /g20/g17/g24/g19 /g21/g17/g20/g19 /g19/g17/g25/g19 /g19/g17/g22/g19 /g19/g17/g28/g19 /g20/g17/g24/g19 /g21/g17/g20/g19 /g21/g17/g21/g23 /g20/g17/g26/g21 /g20/g17/g21/g19 /g19/g17/g25/g27 /g19/g17/g25/g19 /g19/g17/g19/g19 /g19/g17/g25/g19 /g20/g17/g21/g19 /g20/g17/g27/g19 /g39/g20 /g40/g20 /g39 /g40 /g72 /g72 /g72 /g72/g20 /g72 /g72/g20 /g23/g21/g59/g3/g145/g69 /g36 /g36/g21 /g36 /g20 /g20

DS20005498C-page 16  2017-2022 Microchip Technology Inc. and its subsidiaries /g41/g82/g85/g3/g87/g75/g72/g3/g80/g82/g86/g87/g3/g70/g88/g85/g85/g72/g81/g87/g3/g83/g68/g70/g78/g68/g74/g72/g3/g71/g85/g68/g90/g76/g81/g74/g86/g15/g3/g83/g79/g72/g68/g86/g72/g3/g86/g72/g72/g3/g87/g75/g72/g3/g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g51/g68/g70/g78/g68/g74/g76/g81/g74/g3/g54/g83/g72/g70/g76/g73/g76/g70/g68/g87/g76/g82/g81/g3/g79/g82/g70/g68/g87/g72/g71/g3/g68/g87 /g75/g87/g87/g83/g29/g18/g18/g90/g90/g90/g17/g80/g76/g70/g85/g82/g70/g75/g76/g83/g17/g70/g82/g80/g18/g83/g68/g70/g78/g68/g74/g76/g81/g74 /g49/g82/g87/g72/g29 /g53/g40/g41/g29/g3/g53/g72/g73/g72/g85/g72/g81/g70/g72/g3/g39/g76/g80/g72/g81/g86/g76/g82/g81/g15/g3/g88/g86/g88/g68/g79/g79/g92/g3/g90/g76/g87/g75/g82/g88/g87/g3/g87/g82/g79/g72/g85/g68/g81/g70/g72/g15/g3/g73/g82/g85/g3/g76/g81/g73/g82/g85/g80/g68/g87/g76/g82/g81/g3/g83/g88/g85/g83/g82/g86/g72/g86/g3/g82/g81/g79/g92/g17 /g37/g54/g38/g29/g3/g37/g68/g86/g76/g70/g3/g39/g76/g80/g72/g81/g86/g76/g82/g81/g17/g3/g55/g75/g72/g82/g85/g72/g87/g76/g70/g68/g79/g79/g92/g3/g72/g91/g68/g70/g87/g3/g89/g68/g79/g88/g72/g3/g86/g75/g82/g90/g81/g3/g90/g76/g87/g75/g82/g88/g87/g3/g87/g82/g79/g72/g85/g68/g81/g70/g72/g86/g17 /g49/g82/g87/g72/g86/g29 /g20/g17 /g21/g17 /g51/g76/g81/g3/g20/g3/g89/g76/g86/g88/g68/g79/g3/g76/g81/g71/g72/g91/g3/g73/g72/g68/g87/g88/g85/g72/g3/g80/g68/g92/g3/g89/g68/g85/g92/g15/g3/g69/g88/g87/g3/g80/g88/g86/g87/g3/g69/g72/g3/g79/g82/g70/g68/g87/g72/g71/g3/g90/g76/g87/g75/g76/g81/g3/g87/g75/g72/g3/g75/g68/g87/g70/g75/g72/g71/g3/g68/g85/g72/g68/g17 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g76/g81/g74/g3/g68/g81/g71/g3/g87/g82/g79/g72/g85/g68/g81/g70/g76/g81/g74/g3/g83/g72/g85/g3/g36/g54/g48/g40/g3/g60/g20/g23/g17/g24/g48 /g54/g75/g72/g72/g87/g3/g21/g3/g82/g73/g3/g21 /g49/g88/g80/g69/g72/g85/g3/g82/g73/g3/g55/g72/g85/g80/g76/g81/g68/g79/g86 /g50/g89/g72/g85/g68/g79/g79/g3/g43/g72/g76/g74/g75/g87 /g55/g72/g85/g80/g76/g81/g68/g79/g3/g58/g76/g71/g87/g75 /g50/g89/g72/g85/g68/g79/g79/g3/g58/g76/g71/g87/g75 /g40/g91/g83/g82/g86/g72/g71/g3/g51/g68/g71/g3/g58/g76/g71/g87/g75 /g55/g72/g85/g80/g76/g81/g68/g79/g3/g55/g75/g76/g70/g78/g81/g72/g86/g86 /g55/g72/g85/g80/g76/g81/g68/g79/g3/g51/g76/g87/g70/g75 /g54/g87/g68/g81/g71/g82/g73/g73 /g56/g81/g76/g87/g86 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g3/g47/g76/g80/g76/g87/g86 /g36/g20 /g36 /g69 /g40/g20 /g36/g21 /g72 /g40 /g49 /g19/g17/g25/g19/g3/g37/g54/g38 /g19/g17/g26/g21/g24 /g19/g17/g21/g28 /g19/g17/g28/g20 /g19/g17/g21/g20 /g19/g17/g22/g21 /g23/g17/g19/g23/g3/g37/g54/g38 /g19/g17/g28/g25/g24 /g19/g17/g21/g23 /g24/g17/g22/g19/g3/g37/g54/g38 /g48/g44/g47/g47/g44/g48/g40/g55/g40/g53/g54 /g48/g44/g49/g49/g50/g48 /g23/g21 /g19/g17/g22/g24 /g20/g17/g19/g21 /g19/g17/g21/g26 /g48/g36/g59 /g50/g89/g72/g85/g68/g79/g79/g3/g47/g72/g81/g74/g87/g75 /g40/g91/g83/g82/g86/g72/g71/g3/g51/g68/g71/g3/g47/g72/g81/g74/g87/g75 /g39 /g39/g20 /g24/g17/g21/g28/g3/g37/g54/g38 /g23/g17/g21/g19/g3/g37/g54/g38 /g55/g72/g85/g80/g76/g81/g68/g79/g3/g51/g76/g87/g70/g75 /g72/g20 /g19/g17/g24/g21/g3/g37/g54/g38 /g19/g17/g26/g19 /g19/g17/g26/g24 /g23/g21/g16/g37/g68/g79/g79/g3/g38/g75/g76/g83/g3/g54/g70/g68/g79/g72/g3/g51/g68/g70/g78/g68/g74/g72/g3/g11/g26/g24/g59/g12/g3/g16/g3/g24/g17/g21/g28/g91/g24/g17/g22/g19/g91/g20/g17/g19/g21/g3/g80/g80/g3/g37/g82/g71/g92/g3/g62/g38/g54/g51/g64 /g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g55/g72/g70/g75/g81/g82/g79/g82/g74/g92/g3/g39/g85/g68/g90/g76/g81/g74/g3/g38/g19/g23/g16/g24/g22/g22/g16/g26/g24/g59/g3/g53/g72/g89/g3/g37

 2017-2022 Microchip Technology Inc. and its subsidiaries DS20005498C-page 17 HV2605/HV2705 /g53/g40/g38/g50/g48/g48/g40/g49/g39/g40/g39/g3/g47/g36/g49/g39/g3/g51/g36/g55/g55/g40/g53/g49 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g3/g47/g76/g80/g76/g87/g86 /g56/g81/g76/g87/g86 /g38/g21/g38/g82/g81/g87/g68/g70/g87/g3/g51/g68/g71/g3/g54/g83/g68/g70/g76/g81/g74 /g38/g82/g81/g87/g68/g70/g87/g3/g51/g76/g87/g70/g75 /g48/g44/g47/g47/g44/g48/g40/g55/g40/g53/g54 /g19/g17/g25/g19/g3/g37/g54/g38 /g48/g44/g49 /g48/g36/g59 /g23/g17/g19/g23/g3/g37/g54/g38 /g38/g82/g81/g87/g68/g70/g87/g3/g51/g68/g71/g3/g58/g76/g71/g87/g75/g3/g11/g59/g81/g81/g12 /g59 /g19/g17/g21/g24 /g49/g50/g48 /g38/g20/g38/g82/g81/g87/g68/g70/g87/g3/g51/g68/g71/g3/g54/g83/g68/g70/g76/g81/g74 /g23/g17/g21/g19/g3/g37/g54/g38 /g37/g54/g38/g29/g3/g37/g68/g86/g76/g70/g3/g39/g76/g80/g72/g81/g86/g76/g82/g81/g17/g3/g55/g75/g72/g82/g85/g72/g87/g76/g70/g68/g79/g79/g92/g3/g72/g91/g68/g70/g87/g3/g89/g68/g79/g88/g72/g3/g86/g75/g82/g90/g81/g3/g90/g76/g87/g75/g82/g88/g87/g3/g87/g82/g79/g72/g85/g68/g81/g70/g72/g86/g17 /g49/g82/g87/g72/g86/g29 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g76/g81/g74/g3/g68/g81/g71/g3/g87/g82/g79/g72/g85/g68/g81/g70/g76/g81/g74/g3/g83/g72/g85/g3/g36/g54/g48/g40/g3/g60/g20/g23/g17/g24/g48/g20/g17 /g41/g82/g85/g3/g87/g75/g72/g3/g80/g82/g86/g87/g3/g70/g88/g85/g85/g72/g81/g87/g3/g83/g68/g70/g78/g68/g74/g72/g3/g71/g85/g68/g90/g76/g81/g74/g86/g15/g3/g83/g79/g72/g68/g86/g72/g3/g86/g72/g72/g3/g87/g75/g72/g3/g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g51/g68/g70/g78/g68/g74/g76/g81/g74/g3/g54/g83/g72/g70/g76/g73/g76/g70/g68/g87/g76/g82/g81/g3/g79/g82/g70/g68/g87/g72/g71/g3/g68/g87 /g75/g87/g87/g83/g29/g18/g18/g90/g90/g90/g17/g80/g76/g70/g85/g82/g70/g75/g76/g83/g17/g70/g82/g80/g18/g83/g68/g70/g78/g68/g74/g76/g81/g74 /g49/g82/g87/g72/g29 /g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g55/g72/g70/g75/g81/g82/g79/g82/g74/g92/g3/g39/g85/g68/g90/g76/g81/g74/g3/g38/g19/g23/g16/g21/g24/g22/g22/g16/g26/g24/g59/g3/g53/g72/g89/g3/g37 /g38/g82/g81/g87/g68/g70/g87/g3/g51/g76/g87/g70/g75 /g19/g17/g24/g21/g3/g37/g54/g38 /g40/g20 /g40/g21 /g40/g20 /g40/g20 /g40/g20 /g40/g20 /g40/g20 /g40/g21 /g40/g21 /g40/g20 /g38/g20 /g38/g21 /g19/g17/g22/g19 /g19/g17/g28/g19 /g20/g17/g24/g19 /g21/g17/g20/g19 /g19/g17/g22/g19 /g19/g17/g28/g19 /g20/g17/g24/g19 /g21/g17/g20/g19 /g20/g17/g27/g19 /g20/g17/g21/g19 /g19/g17/g25/g19 /g19/g17/g19/g19 /g19/g17/g25/g19 /g19/g17/g25/g27 /g20/g17/g21/g19 /g20/g17/g26/g21 /g21/g17/g21/g23 /g19/g17/g19/g19 /g54/g44/g47/g46/g3/g54/g38/g53/g40/g40/g49 /g23/g21/g16/g37/g68/g79/g79/g3/g38/g75/g76/g83/g3/g54/g70/g68/g79/g72/g3/g51/g68/g70/g78/g68/g74/g72/g3/g11/g26/g24/g59/g12/g3/g16/g3/g24/g17/g21/g28/g91/g24/g17/g22/g19/g91/g20/g17/g19/g21/g3/g80/g80/g3/g37/g82/g71/g92/g3/g62/g38/g54/g51/g64 /g59 /g20

DS20005498C-page 18  2017-2022 Microchip Technology Inc. and its subsidiaries C SEATING PLANE TOP VIEW SIDE VIEW 0.08 C Microchip Technology Drawing C04-300-Y8X Rev D Sheet 1 of 2 48X For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 48-Lead Plastic Thin Quad Flatpack (Y8X) - 7x7x1.0 mm Body [TQFP] D D E E BA e e A A2 A1 48X b

0.08 C A-B D

D

0.20 C A-B D

0.20 C A-B D 4X

N NOTE 1

 2017-2022 Microchip Technology Inc. and its subsidiaries DS20005498C-page 19 HV2605/HV2705 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Dimensioning and tolerancing per ASME Y14.5M Microchip Technology Drawing C04-300-Y8X Rev D Sheet 2 of 2 48-Lead Plastic Thin Quad Flatpack (Y8X) - 7x7x1.0 mm Body [TQFP] Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Molded Package Width Molded Package Thickness Pitch Standoff Units Dimension Limits A b e L E N

0.50 BSC

1.00 0.45 0.17 0.05 0.22 0.60 MILLIMETERS MIN NOM 0.75 0.27 1.20 0.15 MAX L1 1.00 REFFootprint Overall Length Molded Package Length D

9.00 BSC

7.00 BSC

Terminal Thickness c 0.09 - 0.16 -0.08 -Lead Bend Radius -0.08 0.20Lead Bend Radius 3.5°0° 7°Foot Angle -0° -Lead Angle ࣄ2 12°11° 13°Mold Draft Angle 0.95 1.05 H SECTION A-A c (L1) L

DS20005498C-page 20  2017-2022 Microchip Technology Inc. and its subsidiaries RECOMMENDED LAND PATTERN Dimension Limits Units C2Contact Pad Spacing Contact Pitch MILLIMETERS E MAX 8.40 Contact Pad Length (X48) Contact Pad Width (X48) 1.50 0.30 Microchip Technology Drawing C04-2300-Y8X Rev D NOM E G C1Contact Pad Spacing 8.40 Distance Between Pads G 0.20 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: SILK SCREEN 48-Lead Plastic Thin Quad Flatpack (Y8X) - 7x7x1.0 mm Body [TQFP]

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DS20005498C-page 24  2017-2022 Microchip Technology Inc. and its subsidiaries NOTES:

 2017-2022 Microchip Technology Inc. and its subsidiaries DS20005498C-page 25 HV2605/HV2705 APPENDIX A: REVISION HISTORY Revision C (May 2022)

• Minor layout changes.
• Added 48-Lead LQFP package notice to Package Types† and Packaging Information†. Revision B (August 2021)
• Added 48-Lead TQFP Package
• Updated table Recommended Operating Conditions
• Updated Section 1.0 “Electrical Characteris- tics”
• Updated Section 4.0 “Packaging Information†” Revision A (November 2017)
• Converted Supertex Doc # DSFP-HV2605 and Doc # DSFP-HV2705-HV2706 to Microchip DS20005498C
• Removed HV2706 from the document. HV2706 is EOL.
• Combined HV2605 and HV2705 into one document
• Changed the package marking format
• Added information for 42-Ball Bumped Die package
• Removed the “HVCMOS technology for high performance” in the Features section
• Made minor text changes throughout the document

DS20005498C-page 26  2017-2022 Microchip Technology Inc. and its subsidiaries NOTES:

DS20005498C-page 27  2017-2022 Microchip Technology Inc. and its subsidiaries PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Note: HV2605BD and HV2705BD are RoHS-compliant products. Devices: HV2605 = 16-Channel Low Harmonic Distortion High-Voltage Analog Switch HV2705 = 16-Channel Low Harmonic Distortion High-Voltage Analog Switch with Bleed Resistors Packages: BD = 42-Ball Bumped Die FG = 48-lead LQFP TQ = 48-lead TQFP Environmental: G = Lead (Pb)-free/RoHS-compliant package (not used for BD packages) Media Types: (blank) = 250/Tray for FG package (blank) = 250/Tray for TQ package M931 = 1000/Reel for FG package M931 = 1600/Reel for TQ package M936 = 2500/Reel for BD package Examples: a) HV2605FG-G: 16-Channel Low Harmonic Distortion High-Voltage Analog Switch, 48-lead LQFP Package, 250/Tray b) HV2605BD-M936: 16-Channel Low Harmonic Distortion High-Voltage Analog Switch, 42-ball Bumped Die, 2500/Reel c) HV2705TQ-G: 16-Channel Low Harmonic Distortion High-Voltage Analog Switch with Bleed Resistors, 48-lead TQFP Package, 250 Tray d) HV2705FG-G-M931: 16-Channel Low Harmonic Distortion High-Voltage Analog Switch with Bleed Resistors, 48-lead LQFP Package, 1000/Reel PART NO. -XXXX Device Environmental XX Package Media Type

 2017-2022 Microchip Technology Inc. and its subsidiaries DS20005498C-page 28 HV2605/HV2705 NOTES:

 2017-2022 Microchip Technology Inc. and its subsidiaries DS20005498C-page 29 This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this informa- tion in any other manner violates these terms. Information regarding device applications is provided only for your conve- nience and may be superseded by updates. It is your responsi- bility to ensure t hat your applicatio n meets with your specifications. Contact your lo cal Microchip sales office for additional support or, obtai n additional support at https:// www.microchip.com/en-us/support/design-help/client-support- services. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WAR- RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON- INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI- RECT, SPECIAL, PUNITIVE , INCIDENTAL, OR CONSE- QUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applica- tions is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses ar e conveyed, implicitly or otherwise, under any Microchip intellectual pr operty rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, NVM Express, NVMe, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, Symmcom, and Trusted Time are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2017-2022, Microchip Technology Incorporated and its subsidiar- ies. All Rights Reserved. ISBN: 978-1-6683-0324-5 Note the following details of the code protection feature on Microchip products:

• Microchip products meet the specifications c ontained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is secure w hen used in the intended manner, within operating specifications, and under normal conditions.
• Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
• Neither Microchip nor any other semic onductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

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