HV232Q

SN65HVD230Q-Q1_07 TI | Alldatasheet

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SGLS117C – JUNE 2001 – REVISED JUNE 2002 3.3-V CAN TRANSCEIVERS 1www.ti.com

FEATURES

/C0068Qualification in Accordance With AEC-Q100† /C0068Qualified for Automotive Applications /C0068Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval /C0068ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) /C0068Operates With a 3.3-V Supply /C0068Low Power Replacement for the PCA82C250 Footprint /C0068Bus/Pin ESD Protection Exceeds 15-kV HBM /C0068Controlled Driver Output Transition Times for Improved Signal Quality on the SN65HVD230Q and SN65HVD231Q /C0068Unpowered Node Does Not Disturb the Bus /C0068Compatible With the Requirements of the ISO 11898 Standard /C0068Low-Current SN65HVD230Q Standby Mode 370 µA Typical † Contact factory for details. Q100 qualification data available on request. /C0068Low-Current SN65HVD231Q Sleep Mode 0.1 µA Typical /C0068Designed for Signaling Rates‡ Up To

1 Megabit/Second (Mbps)

/C0068Thermal Shutdown Protection /C0068Open-Circuit Fail-Safe Design logic diagram (positive logic) CANL CANH R D 1 SN65HVD230Q, SN65HVD231Q Logic Diagram (Positive Logic) R S 8 Vref 53VCC CANL CANH R D 1 SN65HVD232Q Logic Diagram (Positive Logic) ‡ The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). D GND VCC R R S CANH CANL Vref SN65HVD230QD SN65HVD231QD (TOP VIEW) D GND VCC R NC CANH CANL NC SN65HVD232QD (TOP VIEW) NC – No internal connection PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2002, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SGLS117C – JUNE 2001 – REVISED JUNE 2002 2 www.ti.com

DESCRIPTION

The SN65HVD230Q, SN65HVD231Q, and SN65HVD232Q controller area network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers, or with equivalent devices. They are intended for use in applications employing the CAN serial communication physical layer in accordance with the ISO 11898 standard. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. Designed for operation in especially-harsh environments, these devices feature cross-wire protection, loss-of-ground and overvoltage protection, overtemperature protection, as well as wide common-mode range. The transceiver interfaces the single-ended CAN controller with the differential CAN bus found in industrial, building automation, and automotive applications. It operates over a –2-V to 7-V common-mode range on the bus, and it can withstand common-mode transients of ± 25 V. On the SN65HVD230Q and SN65HVD231Q, R S (pin 8) provides three different modes of operation: high-speed, slope control, and low-power modes. The high-speed mode of operation is selected by connecting pin 8 to ground, allowing the transmitter output transistors to switch on and off as fast as possible with no limitation on the rise and fall slopes. The rise and fall slopes can be adjusted by connecting a resistor to ground at pin 8, since the slope is proportional to the pin’s output current. This slope control is implemented with external resistor values of 10 kΩ, to achieve a 15-V/µs slew rate, to 100 kΩ, to achieve a 2-V/µs slew rate. The circuit of the SN65HVD230Q enters a low-current standby mode during which the driver is switched off and the receiver remains active if a high logic level is applied to R S (pin 8). The DSP controller reverses this low-current standby mode when a dominant state (bus differential voltage > 900 mV typical) occurs on the bus. The unique difference between the SN65HVD230Q and the SN65HVD231Q is that both the driver and the receiver are switched off in the SN65HVD231Q when a high logic level is applied to RS (pin 8) and remain in this sleep mode until the circuit is reactivated by a low logic level on RS. The Vref (pin 5 on the SN65HVD230Q and SN65HVD231Q) is available as a VCC /2 voltage reference. The SN65HVD232Q is a basic CAN transceiver with no added options; pins 5 and 8 are NC, no connection. AVAILABLE OPTIONS FUNCTION NUMBER LOW POWER MODE INTEGRATED SLOPE CONTROL Vref PIN ’230 370-µA standby mode Yes Yes ’231 10-µA sleep mode Yes Yes ’232 No standby or sleep mode No No PART NUMBER Q100 TA MARKED AS: SN65HVD230QD No 40°Ct HV230Q SN65HVD231QD No –40°C to 125°C HV231Q SN65HVD232QD No 125°C HV232Q SN65HVD230QDQ1 Yes 40°Ct 230Q1 SN65HVD231QDQ1 Yes –40°C to 125°C 231Q1 SN65HVD232QDQ1 Yes 125°C 232Q1 The D package is available taped and reeled. Add the suffix R to device type (e.g., SN65HVD230QDRQ1).

SGLS117C – JUNE 2001 – REVISED JUNE 2002 3www.ti.com Function Tables DRIVER (SN65HVD230Q, SN65HVD231Q) INPUT D R OUTPUTS BUS STATEINPUT D R S CANH CANL BUS STATE L V1 2 V H L Dominant H V(Rs) < 1.2 V Z Z Recessive Open X Z Z Recessive X V(Rs) > 0.75 VCC Z Z Recessive H = high level; L = low level; X = irrelevant; ? = indeterminate DRIVER (SN65HVD232Q) INPUT D OUTPUTS BUS STATEINPUT D CANH CANL BUS STATE L H L Dominant H Z Z Recessive Open Z Z Recessive H = high level; L = low level RECEIVER (SN65HVD230Q) DIFFERENTIAL INPUTS R S OUTPUT R VID ≥ 0.9 V X L 0.5 V < VID < 0.9 V X ? VID ≤ 0.5 V X H Open X H H = high level; L = low level; X = irrelevant; ? = indeterminate RECEIVER (SN65HVD231Q) DIFFERENTIAL INPUTS R S OUTPUT R VID ≥ 0.9 V L 0.5 V < VID < 0.9 V V(Rs) < 1.2 V ? VID ≤ 0.5 V V(Rs) < 1.2 V H X V(Rs) > 0.75 VCC H X 1.2 V < V(Rs) < 0.75 VCC ? Open X H H = high level; L = low level; X = irrelevant; ? = indeterminate RECEIVER (SN65HVD232Q) DIFFERENTIAL INPUTS OUTPUT R VID ≥ 0.9 V L 0.5 V < VID < 0.9 V ? VID ≤ 0.5 V H Open H H = high level; L = low level; X = irrelevant; ? = indeterminate

SGLS117C – JUNE 2001 – REVISED JUNE 2002 4 www.ti.com Function Tables (Continued) TRANSCEIVER MODES (SN65HVD230Q, SN65HVD231Q) V(Rs) OPERATING MODE V(RS) > 0.75 VCC Standby 10 kΩ to 100 kΩ to ground Slope control V(RS) < 1 V High speed (no slope control) Terminal Functions SN65HVD230Q, SN65HVD231Q TERMINAL DESCRIPTIONNAME NO. DESCRIPTION CANL 6 Low bus output CANH 7 High bus output D 1 Driver input GND 2 Ground R 4 Receiver output R S 8 Standby/slope control VCC 3 Supply voltage Vref 5 Reference output SN65HVD232Q TERMINAL DESCRIPTIONNAME NO. DESCRIPTION CANL 6 Low bus output CANH 7 High bus output D 1 Driver input GND 2 Ground NC 5, 8 No connection R 4 Receiver output VCC 3 Supply voltage

SGLS117C – JUNE 2001 – REVISED JUNE 2002 5www.ti.com equivalent input and output schematic diagrams VCC D Input 1 kΩ 9 V Input 100 kΩ VCC Output 16 V CANH and CANL Outputs 20 V VCC 5 Ω 9 V Output R Output VCC Input 16 V CANH and CANL Inputs 20 V 110 kΩ 45 kΩ 9 kΩ 9 kΩ

SGLS117C – JUNE 2001 – REVISED JUNE 2002 6 www.ti.com absolute maximum ratings over operating free-air temperature (see Note 1) (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. 2. Tested in accordance with JEDEC Standard 22, Test Method A114-A. 3. Tested in accordance with JEDEC Standard 22, Test Method C101. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ‡ ABOVE T A = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING D 725 mW 5.8 mW/°C 464 mW 377 mW 145 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. recommended operating conditions PARAMETER MIN NOM MAX UNIT Supply voltage, VCC 3 3.6 V Voltage at any bus terminal (common mode) VIC –2§ 7 V Voltage at any bus terminal (separately) VI –2.5 7.5 V High-level input voltage, VIH D, R 2 V Low-level input voltage, VIL D, R 0.8 V Differential input voltage, VID (see Figure 5) –6 6 V V(RS) 0 VCC V V(RS) for standby or sleep 0.75 VCC VCC V Rs wave-shaping resistance 0 100 kΩ High level output current I Driver –40 mAHigh-level output current, IOH Receiver –8 mA Low level output current I Driver 48 mALow-level output current, IOL Receiver 8 mA Operating free-air temperature, TA –40 125 °C § The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.

SGLS117C – JUNE 2001 – REVISED JUNE 2002 7www.ti.com driver electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT V Dominant VI = 0 V, CANH 2.45 VCCVOH Bus output Dominant VI = 0 V, See Figure 1 and Figure 3CANL 0.5 1.25 V V Bus out ut voltage Recessive VI = 3 V, CANH 2.3 V VOL Recessive VI = 3 V, See Figure 1 and Figure 3CANL 2.3 V Dominant VI = 0 V, See Figure 1 1.5 2 3 VVOD(D) Differential output Dominant VI = 0 V, See Figure 2 1.2 2 3 V V Differential out ut voltage Recessive VI = 3 V, See Figure 1 –120 0 12 mV VOD(R) Recessive VI = 3 V, No load –0.5 –0.2 0.05 V IIH High-level input current VI = 2 V –30 µA IIL Low-level input current VI = 0.8 V –30 µA I Short circuit output current VCANH = –2 V –250 250 mAIOS Short-circuit output current VCANL = 7 V –250 250 mA C o Output capacitance See receiver Standby SN65HVD230Q VV 370 600 A ICC Supply current Sleep SN65HVD231Q V(RS) = VCC 0.1 µA ICC Supply current All devices Dominant VI = 0 V, No load Dominant 10 17 mAAll devices Recessive VI = VCC , No load Recessive 10 17 mA † All typical values are at 25°C and with a 3.3-V supply. driver switching characteristics at TA = 25°C (unless otherwise noted) SN65HVD230Q and SN65HVD231Q PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(RS) = 0 V 35 85 tPLH Propagation delay time, low-to-high-level outputR S with 10 kΩ to ground 70 125 nstPLH Pro agation delay time, low to high level out ut R S with 100 kΩ to ground 500 870 ns V(RS) = 0 V 70 120 tPHL Propagation delay time, high-to-low-level outputR S with 10 kΩ to ground 130 180 nstPHL Pro agation delay time, high to low level out ut R S with 100 kΩ to ground 870 1200 ns V(RS) = 0 V 35 tsk(p) Pulse skew (|tP(HL ) – tP(LH )|) R S with 10 kΩ to ground C L = 50 pF, See Figure 4 60 nstsk( ) Pulse skew (|tP(HL) tP(LH)|) R S with 100 kΩ to ground See Figure 4 370 ns tr Differential output signal rise time V0 V 25 50 100 ns tf Differential output signal fall time V(RS) = 0 V 40 55 80 ns tr Differential output signal rise time R with 10 kΩ to ground 80 120 160 ns tf Differential output signal fall time R S with 10 kΩ to ground 80 125 150 ns tr Differential output signal rise time R with 100 kΩ to ground 600 800 1200 ns tf Differential output signal fall time R S with 100 kΩ to ground 600 825 1000 ns

SGLS117C – JUNE 2001 – REVISED JUNE 2002 8 www.ti.com driver switching characteristics at TA = 25°C (unless otherwise noted) SN65HVD232Q PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high-level output 35 85 ns tPHL Propagation delay time, high-to-low-level output 70 120 ns tsk(p) Pulse skew (|tP(HL) – tP(LH)|) C L = 50 pF, See Figure 4 35 ns tr Differential output signal rise time C L 50 F, See Figure 4 25 50 100 ns tf Differential output signal fall time 40 55 80 ns receiver electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIT+ Positive-going input threshold voltage See Table 1 750 900 mV VIT– Negative-going input threshold voltageSee Table 1 500 650 mVVhys Hysteresis voltage (VIT+ – VIT–) 100 mV VOH High-level output voltage –6 V ≤ VID ≤ 500 mV, IO = –8 mA, See Figure 5 2.4 V VOL Low-level output voltage 900 mV ≤ VID ≤ 6 V, IO = 8 mA, See Figure 5 0.4 V VIH = 7 V 100 250 A I VIH = 7 V, VCC = 0 V Other input at 0 V,100 350 µA II Bus input current VIH = –2 V Other in ut at 0 V, D = 3 V –200 –30 AVIH = –2 V, VCC = 0 V –100 –20 µA C i CANH, CANL input capacitance Pin-to-ground, VI = 0.4 sin(4E6πt) + 0.5 V V(D) = 3 V, 32 pF C diff Differential input capacitance Pin-to-pin, VI = 0.4 sin(4E6πt) + 0.5 V V(D) = 3 V, 16 pF R diff Differential input resistance Pin-to-pin, V(D) = 3 V 40 70 100 kΩ R T CANH, CANL input resistance 20 35 50 kΩ ICC Supply current See driver † All typical values are at 25°C and with a 3.3-V supply. receiver switching characteristics at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high-level output 35 50 ns tPHL Propagation delay time, high-to-low-level output See Figure 6 35 50 ns tsk(p) Pulse skew (|tP(HL) – tP(LH)|) See Figure 6 10 ns tr Output signal rise time See Figure 6 1.5 ns tf Output signal fall time See Figure 6 1.5 ns t(loop) Total loop delay, driver input to receiver outputV(RS) = 0 V 70 135 t(loop) Total loop delay, driver input to receiver outputR S with 10 kΩ to ground 105 175 ns t(loop) Total loop delay, driver input to receiver outputR S with 100 kΩ to ground 535 920

† All typical values are at 25°C and with a 3.3 V supply.

0 V or 3 V

Figure 1. Driver Voltage and Current Definitions Figure 2. Driver VOD Figure 3. Driver Output Voltage Definitions

Table 1. Receiver Characteristics Over Common Mode With V(RS) at 1.2 V

4 V 6 V 7 V 1 V L

1 V –6 V –2 V 4 V H VOH

4 V –6 V 1 V 7 V H

Figure 8. t(WAKE) Test Circuit and Voltage Waveforms

SGLS117C – JUNE 2001 – REVISED JUNE 2002 17www.ti.com TYPICAL CHARACTERISTICS Figure 25 0.5 1.5 2.5 –50 –555 0 VCC = 3 V REFERENCE VOLTAGE vs REFERENCE CURRENT V ref– Reference Voltage – V Iref – Reference Current – µA VCC = 3.6 V

APPLICATION INFORMATION

This application provides information concerning the implementation of the physical medium attachment layer in a CAN network according to the ISO 11898 standard. It presents a typical application circuit and test results, as well as discussions on slope control, total loop delay, and interoperability in 5-V systems. introduction ISO 11898 is the international standard for high-speed serial communication using the controller area network (CAN) bus protocol. It supports multimaster operation, real-time control, programmable data rates up to 1 Mbps, and powerful redundant error checking procedures that provide reliable data transmission. It is suited for networking intelligent devices as well as sensors and actuators within the rugged electrical environment of a machine chassis or factory floor. The SN65HVD230Q family of 3.3-V CAN transceivers implement the lowest layers of the ISO/OSI reference model. This is the interface with the physical signaling output of the CAN controller of the Texas Instruments TMS320Lx240x 3.3-V DSPs, as illustrated in Figure 26.

SGLS117C – JUNE 2001 – REVISED JUNE 2002 20 www.ti.com features of the SN65HVD230Q, SN65HVD231Q, and SN65HVD232Q (continued) The bus pins are also maintained in a high-impedance state during low VCC conditions to ensure glitch-free power-up and power-down bus protection for hot-plugging applications. This high-impedance condition also means that an unpowered node will not disturb the bus. Transceivers without this feature usually have a very low output impedance. This results in a high current demand when the transceiver is unpowered, a condition that could affect the entire bus. operating modes R S (pin 8) of the SN65HVD230Q and SN65HVD231Q provides for three different modes of operation: high-speed mode, slope-control mode, and low-power standby mode. high-speed mode The high-speed mode can be selected by applying a logic low to Rs (pin 8). The high-speed mode of operation is commonly employed in industrial applications. High-speed allows the output to switch as fast as possible with no internal limitation on the output rise and fall slopes. The only limitations of the high-speed operation are cable length and radiated emission concerns, each of which is addressed by the slope control mode of operation. If the low-power standby mode is to be employed in the circuit, direct connection to a DSP output pin can be used to switch between a logic-low level (< 1 V) for high speed mode operation, and the logic-high level (> 0.75 V CC ) for standby mode operation. Figure 29 shows a typical DSP connection, and Figure 30 shows the SN65HVD230Q driver output signal in high-speed mode on the CAN bus. TMS320LF2406 or TMS320LF2407 IOPF61 D GND VCC R CANH CANL Vref R S SN65HVD230Q Figure 29. RS (Pin 8) Connection to a TMS320LF2406/07 for High-Speed or Standby Mode Operation

SGLS117C – JUNE 2001 – REVISED JUNE 2002 21www.ti.com high-speed mode (continued)

1 Mbps

Figure 30. Typical SN65HVD230Q High-Speed Mode Output Waveform Into a 60-Ω Load Figure 32. Typical driver output waveforms from a pulse input signal with and without slope control are displayed in Figure 33. A pulse input is used rather than NRZ data to clearly display the actual slew rate. Figure 31. Slope-Control or Standby Mode Connection to a DSP

SGLS117C – JUNE 2001 – REVISED JUNE 2002 23www.ti.com standby mode (listen only mode) of the SN65HVD230Q If a logic high (> 0.75 VCC ) is applied to RS (pin 8) in Figures 29 and 31, the circuit of the SN65HVD230Q enters a low-current, listen only standby mode during which the driver is switched off and the receiver remains active. In this listen only state, the transceiver is completely passive to the bus. It makes no difference if a slope control resistor is in place as shown in Figure 31. The DSP can reverse this low-power standby mode when the rising edge of a dominant state (bus differential voltage > 900 mV typical) occurs on the bus. The DSP, sensing bus activity, reactivates the driver circuit by placing a logic low (< 1.2 V) on R S (pin 8). the babbling idiot protection of the SN65HVD231Q Occasionally, a runaway CAN controller unintentionally sends messages that completely tie up the bus (what is referred to in CAN jargon as a babbling idiot). When this occurs, the DSP can engage the listen-only standby mode to disengage the driver and release the bus, even when access to the CAN controller has been lost. When the driver circuit is deactivated, its outputs default to a high-impedance state. sleep mode of the SN65HVD231Q The unique difference between the SN65HVD230Q and the SN65HVD231Q is that both driver and receiver are switched off in the SN65HVD231Q when a logic high is applied to R S (pin 8). The device remains in a very low power-sleep mode until the circuit is reactivated with a logic low applied to RS (pin 8). While in this sleep mode, the bus pins are in a high-impedance state, while the D and R pins default to a logic high. loop propagation delay Transceiver loop delay is a measure of the overall device propagation delay, consisting of the delay from the driver input to the differential outputs, plus the delay from the receiver inputs to its output. The loop delay of the transceiver displayed in Figure 34 increases accordingly when slope control is being used. This increased loop delay means that the total bus length must be reduced to meet the CAN bit-timing requirements of the overall system. The loop delay becomes ≈100 ns when employing slope control with a 10-kΩ resistor, and ≈500 ns with a 100-kΩ resistor. Therefore, considering that the rule-of-thumb propagation delay of typical bus cable is 5 ns/m, slope control with the 100-kΩ resistor decreases the allowable bus length by the difference between the 500-ns max loop delay and the loop delay with no slope control, 70.7 ns. This equates to (500–70.7 ns)/5 ns, or approximately 86 m less bus length. This slew-rate/bus length trade-off to reduce electromagnetic interference to adjoining circuits from the bus can also be solved with a high-quality shielded bus cable.

SGLS117C – JUNE 2001 – REVISED JUNE 2002 24 www.ti.com Figure 34. 70.7-ns Loop Delay Through the SN65HVD230Q With RS = 0

SGLS117C – JUNE 2001 – REVISED JUNE 2002 25www.ti.com interoperability with 5-V CAN systems It is essential that the 3.3-V SN65HVD230Q family performs seamlessly with 5-V transceivers because of the large number of 5-V devices installed. Figure 35 displays a test bus of a 3.3-V node with the SN65HVD230Q, and three 5-V nodes: one for each of TI’s SN65LBC031 and UC5350 transceivers, and one using a competitor X250 transceiver. SN65HVD230Q Tektronix HFS –9003 Pattern Generator Tektronix 784D OscilloscopeTrigger Input One Meter Belden Cable #82841 Competitor X250SN65LBC031 UC5350 HP E3516A 3.3-V Power Supply HP E3516A 5-V Power Supply Tektronix P6243 Single-Ended Probes 120 Ω120 Ω Figure 35. 3.3-V/5-V CAN Transceiver Test Bed

SGLS117C – JUNE 2001 – REVISED JUNE 2002 27www.ti.com MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0.228 (5,80) 0.244 (6,20) 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.014 (0,35) 0.020 (0,51) A 0.157 (4,00) 0.150 (3,81) 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) PINS ** 0.008 (0,20) NOM A MIN A MAX DIM Gage Plane 0.189 (4,80) (5,00) 0.197 (8,55) (8,75) 0.337 0.344 (9,80) 0.394 (10,00) 0.386 0.004 (0,10) M0.010 (0,25) 0.050 (1,27) 0°–/C02578° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Falls within JEDEC MS-012

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SN65HVD230QD NRND SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM SN65HVD230QDR NRND SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM SN65HVD230QDRQ1 OBSOLETE SOIC D 8 TBD Call TI Call TI SN65HVD231QD NRND SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM SN65HVD231QDR NRND SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM SN65HVD231QDRQ1 ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM SN65HVD232QD NRND SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM SN65HVD232QDR NRND SOIC D 8 2500 TBD Call TI Call TI SN65HVD232QDRQ1 ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 29-May-2007 Addendum-Page 1

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