SN74HSTL16919 TI | Alldatasheet
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9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH WITH INPUT PULLUP RESISTORS SCES348 – MARCH 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Member of Texas Instruments’ Widebus Family /C0068 Inputs Meet JEDEC HSTL Std JESD 8-6, and Outputs Meet Level III Specifications /C0068 10-kΩ Pullup Resistor on Data and LE Inputs /C0068 Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II /C0068 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)
description
This 9-bit to 18-bit D-type latch is designed for 3.15-V to 3.45-V V CC operation. The D inputs accept HSTL levels and the Q outputs provide LVTTL levels. The SN74HSTL16919 is particularly suitable for driving an address bus to two banks of memory. Each bank of nine outputs is controlled with its own latch-enable (LE ) input. Each of the nine D inputs is tied to the inputs of two D-type latches that provide true data (Q) at the outputs. While LE is low, the Q outputs of the corresponding nine latches follow the D inputs. When LE is taken high, the Q outputs are latched at the levels set up at the D inputs. To ensure low ICC during power up or power down, 10-kΩ pullup resistors are included on the D and LE inputs to ensure a differential voltage relative to VREF . VREF must be applied prior to or at the same time as VCC , or VREF must be pulled down to ground.
ORDERING INFORMATION
TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING 0°C to 70°C TSSOP – DGG Tape and reel SN74HSTL16919DGGR HSTL16919 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2001, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. DGG PACKAGE (TOP VIEW) 2Q1 1Q1 GND V CC GND 1LE GND VREF GND 2LE GND V CC GND 2Q9 1Q9 V CC VCC 1Q2 2Q2 GND 1Q3 2Q3 V CC 1Q4 2Q4 GND 1Q5 2Q5 GND 1Q6 2Q6 V CC 1Q7 2Q7 GND 1Q8 2Q8 V CC VCC PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH WITH INPUT PULLUP RESISTORS SCES348 – MARCH 2001
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
H X Q 0† † Output level before the indicated steady-state input conditions were established logic diagram (positive logic) 1Q1 2Q1 1LE 2LE To Eight Other Channels VREF absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH WITH INPUT PULLUP RESISTORS SCES348 – MARCH 2001 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 3) MIN NOM MAX UNIT VCC Supply voltage 3.15 3.45 V VREF Reference voltage 0.68 0.75 0.9 V VI Input voltage 0 1.5 V VIH AC high-level input voltage All inputs VREF +200 mV V VIL AC low-level input voltage All inputs VREF –200 mV V VIH DC high-level input voltage All inputs VREF +100 mV V VIL DC low-level input voltage All inputs VREF –100 mV V IOH High-level output current –24 mA IOL Low-level output current 24 mA TA Operating free-air temperature 0 70 °C NOTE 3: All unused inputs of the device must maintain a minimum differential voltage of 100 mV between data inputs and VREF to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK VCC = 3.15 V, II = –18 mA –1.2 V VOH VCC = 3.15 V, IOH = –24 mA 2.4 V VOL VCC = 3.15 V, IOL = 24 mA 0.5 V Control inputs VI = 0 or 1.5 V –500 II Data inputs VCC = 3.45 V VI = 0 or 1.5 V –500 µA VREF VREF = 0.68 V or 0.9 V 90 ICC VCC = 3.45 V, VI = 0 or 1.5 V 50 100 mA C i Control inputs VCC = 0 or 3.3 V, VI = 0 or 3.3 V 2.5 pFC i Data inputs VCC = 0 or 3.3 V, VI = 0 or 3.3 V 2.5 pF C o Outputs VCC = 0, VO = 0 2.5 pF † All typical values are at VCC = 3.3 V, TA = 25°C. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 3.3 V ± 0.15 V UNIT MIN MAX tw Pulse duration, LE low 3 ns tsu Setup time, D before LE↑ 2 ns th Hold time D after LE↑ 1 ns tldr‡ Data race condition time D after LE↓ 0 ns ‡ This is the maximum time after LE switches low that the data input can return to the latched state from the opposite state without producing a glitch on the output.
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH WITH INPUT PULLUP RESISTORS SCES348 – MARCH 2001
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, VREF = 0.75 V PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.15 V UNIT(INPUT) (OUTPUT) MIN MAX t d D Q 1.9 3.5 nstpd LE Q 1.9 4.3 ns simultaneous switching characteristics over recommended operating free-air temperature range, VREF = 0.75 V† PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.15 V UNIT(INPUT) (OUTPUT) MIN MAX t d D Q 1.9 4.5 nstpd LE Q 1.9 5.3 ns † All outputs switching.
NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 1 ns, tf ≤ 1 ns. C. The outputs are measured one at a time with one transition per measurement. D. tPHL and tPLH are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SN74HSTL16919DGGR ACTIVE TSSOP DGG 48 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 25-Feb-2005 Addendum-Page 1
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97
48 PINS SHOWN
0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153
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