HSP9501 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • DC to 32MHz Operating Frequency
  • Programmable Buffer Length from 2 to 1281 Words
  • Supports Data Words to 10-Bits
  • Clock Select Logic for Positive or Negative Edge System Clocks
  • Data Recirculate or Delay Modes of Operation
  • Expandable Data Word Width or Buffer Length
  • Three-State Outputs
  • TTL Compatible Inputs/Outputs
  • Low Power CMOS

Applications

  • Sample Rate Conversion
  • Data Time Compression/Expansion
  • Software Controlled Data Alignment
  • Programmable Serial Data Shifting
  • Audio/Speech Data Processing Video/Image Processing Video/Image Processing
  • 1-H Delay Line of 910 NTSC, 1135 PAL or 1280 Samples: - High Resolution Monitor Delay Line - Comb Filter Designs - Progressive Scanning Display - TV Standards Conversion - Image Processing

Ordering Information

TEMP. RANGE ( oC) PACKAGE PKG. NO. HSP9501JC-25 0 to 70 44 Ld PLCC N44.65 HSP9501JC-32 0 to 70 44 Ld PLCC N44.65 HSP9501JC-2596 0 to 70 44 Ld PLCC Tape and Reel N44.65 Data Sheet January 1999 File Number 2786.4

44 LEAD PLCC

18 19 20 21 22 23 24 25 26 27 28 8 38 DO0 DO1 DO2 DO3 DO4 GND DO5 DO6 DO7 DO8 VCC DI0 DI1 DI2 DI3 DI4 GND DI5 DI6 DI7 DI8 V CC MODSEL MUX CLOCK GENERATOR CLKSEL CLK CLKEN REGISTER REGISTER EN LC0 -10 OE DO0-9 DI 0 -9 10LCEN REGISTER PROGRAMMABLE DELAY RAM 0-1279 DELAYS REGISTER HSP9501

NAME PIN NUMBER TYPE DESCRIPTION VCC 12, 34 The +5V power supply pin. A 0.1 µF capacitor between the VCC and GND pin is recommended. GND 13, 33 The device ground. CLK 1 I Input Clock. This clock signal is used to control the data movement through the programmable buff- er. It is also the signal which latches the input data, length control word and mode select. Input setup and hold times with respect to the clock must be met for proper operation. DIO-9 27, 29-32, 35-39 I Data Inputs. This 10-bit input port is used to provide the input data. When MODSEL is low, data on the DI0-9 inputs is latched on the clock edge selected by CLKSEL. DO0-9 7-11, 14-18 O Data Outputs. This 10-bit port provides the output data from the Internal Delay Registers. Data latched into the DI0-9 inputs will appear at the DO0 9 outputs on the Nth clock cycle, where N is the total delay programmed. LC0-10 20-26, 41-44 I Length Control Inputs. These inputs are used to specify the number of clock cycles of delay be- tween the DI0-9 inputs and the DO0-9 outputs. An integer value between 0 and 1279 is placed on the LC0-10 inputs, and the total delay length (N) programmed is the LC0-10 value plus 2. In order to properly load an active length control word, the value must be presented to the LC0-10 inputs and LCEN must be asserted during an active clock edge selected by CLKSEL. LCEN 6 I Length Control Enable. LCEN is used in conjunction with LC0-10 and CLK to load a new length control word. An 11-bit value is loaded on the LC0-10 inputs,LCEN is asserted, and the next se- lected clock edge will load the new count value. Since this operation is synchronous,LCEN must meet the specified setup/hold times with respect to CLK for proper operation. OE 19 I Output Enable. This input controls the state of the DO0-9 output port. A low on this control line en- ables the port for output. WhenOE is high, the output drivers are in the high impedance state. In- ternal latching or transfer of data is not affected by this input. MODSEL 40 I Mode Select. This input is used to control the mode of operation of the HSP9501. A low on MOD- SEL causes the device to latch new data at the DI0-9 inputs on every clock cycle, and operate as a programmable pipeline register. When MODSEL is high, the HSP9501 is in the recirculate mode, and will operate as a programmable length circular buffer. This control signal may be used in a syn- chronous fashion during device operation, however, care must be taken to ensure the required set- up/hold times with respect to CLK are met. CLKSEL 5 I Clock Select Control. This input is used to determine which edge of the CLK signal is used for con- trolling all internal events. A low on CLKSEL selects the negative going edge, therefore, all setup, hold, and output delay times are with respect to the negative edge of CLK. When CLKSEL is high, the positive going edge is selected and all synchronous timing is with respect to the positive edge of the CLK signal. CLKEN 2 I Clock Enable. This control signal can be used to enable or disable the CLK input. When low, the CLK input is enabled and will operate in a normal fashion. A high onCLKEN will disable the CLK input and will “hold'' all internal operations and data. This control signal may also be used in a syn- chronous fashion, however, setup and hold requirements with respect to CLK must be met for prop- er device operation. This signal takes effect on the clock following the one that latches it in. HSP9501

delays in single delay increments. of the mode select (MODSEL) control input. selects the positive going edge of CLK. input and Output Buffer Registers only.

  1. The programmed delay is established by the 11-bit integer

the delay will be 65 + 2 or 67 delays. operation with larger values is not guaranteed. to the selected CLK edge for proper device operation. TABLE 1. LENGTH CONTROL PROGRAMMING EXAMPLES

Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 1) θJA (oC/W) (PLCC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Logical One Input Voltage V IH VCC = 5.25V 2.0 - V Logical Zero Input Voltage V IL VCC = 4.75V - 0.8 V Output HIGH Voltage V OH IOH = -4mA VCC = 4.75V 2.4 - V Output LOW Voltage V OL IOL = +4.0mA VCC = 4.75V - 0.4 V Input Leakage Current I I VIN = GND or VCC VCC = 5.25V -10 10 µA Output Leakage Current I O VOUT = GND or VCC = 5.25V -10 10 µA Standby Current I CCSB VIN = VCC or GND, VCC = 5.25V, Note 3 - 500 µA Operating Power Supply Current I CCOP f = 25MHz, VIN = VCC or GND VCC = 5.25V, Notes 2, 3 - 125 mA Input Capacitance C IN FREQ = 1MHz, VCC = Open, All measurements are referenced to device GND -1 0 p F Output Capacitance C O -1 0 p F PARAMETER SYMBOL -32 -25 UNITS NOTESMIN MAX MIN MAX Clock Period t CP 31 - 40 - ns - Clock Pulse Width High t PWH 12 - 15 - ns - Clock Pulse Width Low t PWL 12 - - 15 ns - Data Input Setup Time t DS 10 - 12 - ns - Data Input Hold Time t DH 2-2- n s - Output Enable Time t ENA - 20 - 25 ns - Output Disable Time t DIS - 24 - 25 ns Note 4 CLKEN to Clock Setup t ES 10 - 12 - ns - CLKEN to Clock Hold t EH 2-2- n s - LC0-10 Setup Time t LS 10 - 13 - ns - LC0-10 Hold Time t LH 2-2- n s - LCEN to Clock Setup t LES 10 - 13 - ns - LCEN to Clock Hold t LEH 2-2- n s - HSP9501

NOTE: Includes stray and jig capacitance. MODSEL Setup Time t MS 10 - 13 - ns - MODSEL Hold Time t MH 2-2- n s - Clock to Data Out T OUT - 16 - 22 ns - Output Hold from Clock T OH 4-4- n s - Rise, Fall Time T RF -6-6 n s Note 4 NOTES: 2. Power supply current is proportional to operating frequency. Typical rating for ICCOP is 5mA/MHz. 3. Output load per test load circuit with switch open and CL = 40pF. 4. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 5. AC Testing is performed as follows: Input levels: 0V and 3.0V, timing reference levels = 1.5V, input rise and fall times driven at 1ns/V, output load CL = 40pF. PARAMETER SYMBOL -32 -25 UNITS NOTESMIN MAX MIN MAX EQUIVALENT CIRCUIT C L (NOTE) IOH 1.5V I OL DUT SWITCH S1 OPEN FOR I CCSB AND ICCOP HSP9501