HSP50415VIZ

HSP50415_07 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

• 32-Bit Programmable Carrier NCO
• X/SIN(X) Rolloff Compensation
• Programmable I and Q Shaping FIR Filters: - Up to 24 Symbol Span
• Fixed or NCO Controlled Interpolation: - Digital PLL to Lock to Input Symbol Clock
• Digital Signal Processing Capable of >70dB SFDR
• Dual 12-bit D/A Processing Capable of >50dB SFDR
• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Wide-Band Digital Modulation
• Base Station Modulators
• HSP50415EVAL1 Evaluation Board Available

Ordering Information

PART NUMBER PART MARKING TEMP RANGE (°C) PACKAGE PKG. DWG # HSP50415VI HSP50415VI -40 to +85 100 Ld MQFP Q100.14x20 HSP50415VIZ (Note) HSP50415VIZ -40 to +85 100 Ld MQFP (Pb-free) Q100.14x20 HSP50415EVAL1 Evaluation Board NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Data Sheet April 23, 2007 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 FN4559.6 April 23, 2007 Pinout HSP50415 (100 LD MQFP) TOP VIEW 99 98 97 96 95 94 93 91 89 87 85 84 83 818286889092100 32 33 34 35 36 37 38 40 42 44 46 47 48 50494543413931 2XSYMCLK CE ADDR0 ADDR1 ADDR2 REFCLK INTREQ GND DIN5 GND VDD DIN13 DIN14 IOUT1 IOUT0 GND RESV IOUT3 RESV RESV FSADJ AGND ICOMP2 AVDD ICOMP1 IOUT11 IOUT10 IOUT8 IOUT7 IOUT6 VDD IOUT5 IOUT4 GND IOUT12 REFIO IOUTB AGND REFLO QCOMP1 AVDD DVDD DGND QOUTB QOUTA AGND LOCKDET FOVRFL GND SYSCLK/2 IOUT13 VDD FEMPTY DIN15 VDD CDATA3 CDATA4 CDATA5 GND CDATA6 CDATA7 CDATA0 IOUTA DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 VDD DIN4 GND DIN3 DIN2 DIN1 DIN0 DATACLK HSP50415 CDATA1 CDATA2 RD NC ISTRB TXEN FFULL IOUT9 IOUT2 VDD RESV VDD RESET CLK GND DVDD DGND PLLRC PGND PVDD WR QCOMP2 Block Diagram COS SIN I OUTX SIN(X) X SIN(X) CARRIER COMPLEX MIXER CONST MAP DATA FIFO INTERFACE/ I Q INTERFACE DATA DATACLK W/R CONTROL SYMBOL NCO/ REFCLK 2XSYMCLK CLK MULTIPLIER CLKANALOG PLLDIGITAL PLL DIGITAL OUT Q OUT μP 12-BIT DAC 12-BIT DAC NCO SHAPING/ INTERPOLATION FILTERS SHAPING/ INTERPOLATION FILTERS HSP50415

3 FN4559.6 April 23, 2007 Functional Block Diagram COS SIN IOUTAX SIN(X) CARRIER NCO COMPLEX I Q REFCLK CLK IOUT<13:0> 12-BIT DAC WR CE RD ADDR<2:0> RESET CDATA<7:0> ISTRB DATACLK TXEN FEMPT DIN<15:0> FOVRFL DATA FFULL FIR x2, 4, 8, 16 I GAIN HALFBAND x2 x2 TO > 8192 BYPASS BYPASS BYPASS I GAIN BYPASS I OFFSET X SIN(X) 12-BIT DAC FIR BYPASS Q GAIN HALFBAND BYPASS BYPASS BYPASS Q GAIN BYPASS Q OFFSET SYMBOL NCO VOLTAGE REFREFIO LOCKDET PLLRC INTREQ REFLO FSADJ LOOP FILTER ÷ 2SYSCLK/2 ICOMP2 QCOMP1 QCOMP2 ICOMP1 PHASE FREQ. LOCK DETECTOR 2XSYMCLK X 2 CHARGE PUMP VOLTAGECLK MULTIPLIER CLK DIVIDER 1, 2, 4, 8÷ PHASE FREQUENCY DETECTOR APLL BYPASS SYSCLK SYSCLK IOUTB QOUTA QOUTB μP INTERFACE INTERFACE/ FIFO CONST. MAP INTERPOLATION FILTER MIXER INTERPOLATION INTERPO LATION INTERPOLATION INTERPOLATION FILTER SELECTOR X 1, 2, 4, 8, 16, 32 (VCO DIVIDER) CONTROLLED OSCILLATOR ERROR DETECT HSP50415

4 FN4559.6 April 23, 2007 Pin Descriptions NAME TYPE DESCRIPTION VDD - Digital power. GND - Digital ground. DVDD - DAC digital power. DGND - DAC digital ground. AVDD - DAC analog power. AGND - DAC analog ground. PVDD - PLL analog power. PGND - PLL analog ground. PLLRC I PLL loop filter provides for the addition of less expens ive RC components in place of a crystal oscillator. The recommended values for this pin are detailed in the ‘System CLK Generation’ section. CLK I System and DAC clock input when APLL not in use, otherwise it is the reference to the APLL. SYSCLK/2 O Sample Clock Divided by Two. All digital output data and stat us pins are output from this clock. The polarity of SYSCLK/2 may be programmed via Register 2 bit-3. 2XSYMCLK O Tri-statable Symbol NCO Clock Output Multiplied by Two. The polarity of 2XSYMCLK may be programmed via register 2 bit-15. REFCLK I External digital PLL reference clock input. DIN<15:0> I Data Bus. The DIN<15:0> bus loads the input data. DATACLK I Asynchronous data clock for DIN<15:0>. TXEN I DIN<15:0> may be optionally gated with the TXEN pin (burst mode) or input free-running as defined by register 2 bits 18-17. The polarity of TXEN may be programmed via register 2 bit-5. ISTRB I Data samples are input as I then Q serially with the ISTRB pin active with the I sample. The polarity of ISTRB may be programmed via Register 2 bit-4. CDATA<7:0> I/O μP Bidirectional Data Bus. The CDATA<7:0> data bus is used for loading the configuration data and sample vectors for modulation. CDATA7 is the MSB. RD I μP Read control input. WR I μP Write strobe input. CE I Chip enable input. ADDR<2:0> I μP Address Bus. The ADDR<2:0> bus is used for addressing the proper registers for loading the configuration data and sample vectors for modulation. ADDR2 is the MSB. INTREQ O Tri-statable Active High Interrupt Request Output. The INTR EQ output is enabled via regi ster 2 bit-8. Register 9 bits 6-0 enable individual events for INTREQ. RESET While the RESET input is asserted (driven low), all processing halts and the WPM is reset. A software reset is also available via register 10H. IOUT<13:0> O Tri-statable In-Phase Output Samples. IOUT<13:0> outputs are enabled via register 2 bit-7. QOUT<13:0> O Tri-statable Quadrature Output Samples. QOUT<13:0> outputs are enabled via register 2 bit-6. The QOUT<13:0> outputs are not available on the MQFP package. FEMPT, FOVRFL, FFULL O Tri-statable Status Flags for FIFO Level Monitoring. These outputs are enabled via register 2 bits 13-11. FIFO status thresholds and control are configured via register 2 bits 23-16. LOCKDET O Tri-statable Status Flag of the Digital PLL. This may be used to generate an interrupt request via INTREQ. The LOCKDET output is enabled via register 2 bit-10. IOUTA, QOUTA O Current Outputs of the Device. Full scale output current is achieved when all input bits are set to binary 1. IOUTB, QOUTB O Complementary Current Outputs of the Device. Full scale output current is achieved on the complementary outputs when all input bits are set to binary 0. HSP50415

5 FN4559.6 April 23, 2007 Functional Description The HSP50415 is a wideband programmable modulator that accepts an input quadrature data stream at programmable symbol rates of up to 25MSPS (QPSK) and outputs a modulated quadrature data stream at the final sample rate up to 100MHz. The allowable symbol rates depend on the modulation type selected (QPSK, 16QAM, etc.). The input data format is parallel with respect to the bits, but serial with respect to the I and Q samples and may be input at a constant symbol rate or burst in at a different rate. The HSP50415 can symbol map the input data stream per a user programmable look up table thus allowing any standard to be supported. The mapped symbols are then interpolated to the final sample rate and low-pass filtered in order to limit the spectral occupancy of the signal. The first stage filter coefficients are user programmable, with subsequent filter stages having fixed coefficients. The HSP50415 then modulates the symbol data at the final sample rate onto a carrier signal that is tunable from 0.023Hz - 50MHz (for a final sample rate of 100MHz) producing a quadrature signal. The signal may then be optionally X/SIN(X) filtered to compensate for the SIN(X)/X roll-off of the DACs. To correct for system (or DAC induced) gain imbalances between the In phase and Quadrature signals there is a final gain correction stage prior to the output. The final Intermediate Frequency (IF) digital output can be converted to differential analog signals via the onboard 12-bit DACs or may be optionally brought out as 14-bit digital data. The 100-pin MQFP package provides a real digital output at 1/2 the final sample rate. System CLK Generation The HSP50415 receives I and Q input data serially at twice the input symbol rate. The data is converted to a parallel quadrature data stream at the symbol rate by the Front End Data Input Block. This data stream is upsampled to the final output sample rate of the device (FSout). This output sample rate (maximum rate of 100MHz) is used to clock the last stage of the digital logic and the dual 12-bit DACs and may be provided externally on the CLK pin or may be generated by an internal analog PLL (APLL). When enabled, the APLL uses the CLK pin as a reference and provides a selectable CLK multiplier of x2, x4, x8, x16 or x32 or CLK divider of /2, /4 or /8. An external loop filter is required to be supplied at PLLRC. The recommend configuration is shown in Figure 1, with suggested component values calculated as: User Input Terms: APLLclkdivider=APLL CLK divider programmed input APLLvcodivider=APLL VCO divider programmed input Fclk=CLK frequency input Fscale=loop bandwidth divisor input Pm=loop phase margin input (degrees) Component calculation formulas: C1=(Fvcogain*Icp)/(wo*wo*sqrt(kk)) C2=kk*C1 R1=1/sqrt(Fvcogain*Icp*C1*sqrt(C2/C1)) Where: Fvcogain=231000000/APLLvcodivider Icp=0.000353 kk=(1+(sin(Pm*pi/180)))/(1-(sin(Pm*pi/180))) wo=2*pi*((Fclk/APLLclkdivider)/Fscale) ICOMP1, QCOMP1 I Compensation Pin for use in Reducing Bandwidth/Noise. Each pin should be individually decoupled to AVDD with a 0.1μF capacitor. To minimize crosstalk, the part was designed so that these pins must be connected externally, ideally directly under the device packaging. The voltage on these pins is used to dr ive the gates of the PMOS devices that make up the current ce lls. Only the ICOMP1 pin is driven and therefore QCOMP1 needs to be connected to ICOMP1, but de-coupled separately to minimize crosstalk. ICOMP2, QCOMP2 I Compensation Pin for Internal Bias Generation. Each pin should be individually decoupled to AGND with a 0.1μF capacitor. The voltage generated at these pins represents the voltage used to supply 2.0V nominal power to the switch drivers. This arrangement helps to minimize cl ock feedthrough to the current cell transistors for reduced glitch energy and improved spectral performance. REFLO I Reference Low Select. When the internal reference is enabled, this pin serves as the precision ground reference point for the internal voltage reference circuitry and therefore needs to have a good connection to analog ground to enable internal 1.2V reference. To disable the internal reference circuitry this pin should be connected to AVDD. REFIO I Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is enabled. Use 0.1μF cap to ground when internal reference is enabled. FSADJ I Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current = 32 x VFSADJ/RSET. Where VFSADJ is the voltage at this pin. VFSADJ tracks the voltage on the REFIO pin; which is typically 1.2V if the internal reference is used. RESV - Reserved. These pins must be floating (not connected) for proper operation. NC - No Connection. Pins may be connected to GND, AGND, DGND or left floating. Pin Descriptions (Continued) NAME TYPE DESCRIPTION HSP50415

dependent on the interpolation rate through the stage. (non-burst) mode is required. the system clock (SYSCLK/2). FIGURE 1. SAMPLE RATE CLK GENERATION 20 TO 100MHz: C1=130PF, C2=2NF, R1=620ΩInternal IC signal names are shown in lowercase. TABLE 1. HSP50415 FILTER CONFIGURATIONS AND RESULTING SYMBOL NCO RATES

1 Not applicable 0 Symbol Rate x 2 PhincLL x 2

1 Not applicable 1 Symbol Rate x 1 PhincLL x 1

NOTE: An optional decimate by two mode allows the device to achieve interpolation by a factor of two in the Shaping FIR.

7 FN4559.6 April 23, 2007 The SYMBOL NCO 32-bit Phinc value is adjusted automatically such that the SYMBOL NCO runs at the input rate of the interpolating filter, since this is the fastest rate prior to the FSout rate. Table 1 lists possible filter configurations of the HSP50415 and the resulting interpolating filter rate. This resulting rate is affected by rate adjustments (interpolation) in the previous filter blocks. Digital Phase Lock Loop The HSP50415 contains a Digital Phase Lock Loop (DPLL) that performs symbol tracking to an external symbol clock (REFCLK). The DPLL consists of a programmable phase/frequency error detector followed by a loop filter and lock detector stage. The phase/frequency error detector block diagram is shown in Figure The DPLL uses two (integer) counters to give added frequency programming flexibility. The programmed symbol rates are functions of the both the REFCLK divider and the NCO divider (N = NCO divider + 1, see Figure 2), each of which can be changed separately. As an example, these two counters can be set to generate a non-integer output (NCO Symbol rate) frequency (16/3) of the input reference frequency (REFCLK). In this case NCO divider = 16, and REFCLK divider =3. If REFCLK is the desired symbol rate, then the REFCLK divider will be the same value as the NCO divider. If REFCLK is for example 2x the desired symbol rate, then the refClk divider will be 2x the NCO divider. REFCLK is divided down by the REFCLK divider. The internal symbol clk is divided down by the NCO divider. When the carry-out of the REFCLK divider is generated, the symbol NCO is sampled. The phase and frequency (dphi/dt) should be zero if the two rates are phase and frequency locked. If not, the sampled phase value is the phaseError. This value is subtracted from the previous phaseError to generate the frequency error. Both of these error terms are input to the loop filter which scales and integrates these error terms and produces a final symbol nco error term. This final error term gets added to the SYMBOL NCO to adjust the symbol rate to try to track to the divided down external REFCLK input. The loop filter error term must be enabled in the software for this error term to be added to the symbol NCO. Otherwise the Digital PLL has no effect on the symbol rate. The minimum value the REFCLK divider and NCO divider values may be programmed to is the larger of 32/clkDivisor or 0x04, where clkDivisor is FSout/REFCLKrate. This is due to the minimum number of system clock (SYSCLK/2) cycles the loop filter requires to process the new error terms. The maximum rate of this clock is FSout/4 or 25MHz for FSout of 100MHz. The phaseError and freqError terms are input to the loop filter block which is a standard lead/lag type second order loop filter as shown in Figure 3. The loop filter requires 32 clock cycles to process a new error term. The phaseError is weighted by the lag gain and added to the freqError weighted by the frequency gain and this sum is accumulated to give the integral response. The lag accumulator is compared to upper and lower limits and forced to the limit value if either limit is exceeded. This keeps the SYMBOL NCO frequency within the expected symbol rate uncertainty and limits the pull in range. This accumulator output is then added to the phaseError weighted by the lead gain to get a proportional response. This lead term should be zeroed during initial tracking. The gain values are user programmable with a mantissa and exponent of the following format Gain = 01.MMMM * 2^(EEEEE-17) where MMMM denotes the 4-bit gain value and EEEEE is the 5-bit shift value. The phaseError and freqError signals may be monitored on the digital outputs for test or the lock detect pin may be used to monitor the symbol tracking phase error. The lock detect pin indicates whether the DPLL has phase locked to the external symbol clock. The lock detect status may also be used to generate an interrupt event. The lock detect block diagram is shown in Figure HSP50415

FIGURE 7. CONSTELLATION MAPPING pertain to a single channel. characteristics for the various interpolation rates. TABLE 3. FIR FILTER CHARACTERISTICS be loaded with all zeros for power conservation.

FIGURE 8. HALF-BAND FREQUENCY RESPONSE so the subsequent discussion will refer to a single channel. should be no greater than -2dB fullscale to prevent overflow. response for varying interpolation ratios.

FIGURE 18. X/SIN(X) FILTER RESPONSE result of the scale operation. values. The output is rounded to either 14-bits or 12-bits. TABLE 4. IQ GAIN CORRECTION STAGE ROUNDING OPTIONS

00 No rounding performed, data is truncated

01 Round to 14-bits

10 Round to 12-bits

11 Round in both positions

If saturation does occur, the output is symmetrically limited. DACs segmented current source architecture. 2mA is possible, with performance degradation. reference is used, VFSADJ will equal the external reference. IOUT(Full Scale) = (VFSADJ/RSET) X 32. then the input coding to output current is shown in Table 5. TABLE 5. INPUT CODING vs OUTPUT CURRENT is produced in conjunction with the output full scale current. load resistor should be chosen to match this impedance.

a 1:1 transformer on the output of the DAC (see Figure 19). FIGURE 19. DAC OUTPUTS values along the transfer curve. temperature to the value measured at either TMIN or TMAX . deviation of the output current from a value of 0mA. measurement is done by switching quarter scale. the specified error band without overdriving the oscilloscope. 0.707 (-3dB) of its original value.

FIGURE 20. CONTROL REGISTER LOADING SEQUENCE TABLE 6. SEQUENCE OF WRITES TO LOAD CNTLWORD12 TABLE 7. READBACK OF CNTLWORD12 TABLE 8. CONTROL WORD 0 - MEMORY CONTROL BITS

1 Auto-Increment Memory Address Mode Active

1 Memory R/W select: Read from Selected Memory

001 I channel 64x72-bit coefficient RAM selected

010 Q channel 64x72-bit coefficient RAM selected

011 I and Q channel 64x72-bit coefficient RAMs

110 Not Used

111 Not Used

Word 0 would reset the internal auto-increment address to 0. TABLE 9. EXAMPLE SEQUENCE OF WRITES TO LOAD I/Q COEFFICIENT RAM TABLE 10. EXAMPLE SEQUENCE OF WRITES TO LOAD CONSTELLATION MAP RAM

data at memory address 0x12. fewer bytes per address are read back. TABLE 11. EXAMPLE SEQUENCE OF WRITES TO READ I COEFFICIENT RAM TABLE 12. MICROPROCESSOR INTERFACE ADDRESS SPACE DEFINITIONS

TABLE 13. HSP50415 REGISTER SUMMARY TABLE 14. MEMORY WRITE/READ CONTROL

7 Reserved 0

6 Auto Increment Memory Address 0

5 Memory R/W (Used in conjunction with bits 4:2)

TABLE 15. DEVICE CONFIGURATION CONTROL

15 Symbol NCO Counter Mode Enable 0B

14 Fast DAC delay 1B

13 Bypass Final Interpolation Filter 1B

4 Half Band Filter Enable

3 Shaping Filter Bypass

2 Decimate by 2 at output of Shaping Filter

1 Constellation Map Bypass

0 FIFO Bypass

TABLE 15. DEVICE CONFIGURATION CONTROL (Continued) TABLE 16. FIFO AND I/O CONTROL

23 FIFO Full Stop Writing 0

22 FIFO Empty, Force 0 data 0

18 FIFO TXEN Enable Gated Write

17 FIFO TXEN Gated Read

16 FIFO Underflow/Empty Pin Function

13 FFULL, FIFO Full Output Enable 0

12 FOVRFL, FIFO Overflow Output Enable 0

11 FEMPT, FIFO Under/Empty Output Enable 0

10 LOCKDET Output Enable 0

9 SYSCLK/2 Output Enable 0

8 INTREQ Pin Output Enable 0

7 IOUT<13:0> Output Enable 0

6 QOUT<13:0> Output Enable 0

5 TXEN Polarity

2 FIFO Gated Read No Address Reset 0

1 IDAC Power Enable 0

0 QDAC Power Enable 0

TABLE 17. I CHANNEL CALIBRATION

3 I Negate Scale Factor 0

2 I Subtract DC Offset 0

TABLE 16. FIFO AND I/O CONTROL (Continued)

TABLE 18. Q CHANNEL CALIBRATION

3 Q Negate Scale Factor 0

2 Q Subtract DC Offset 0

TABLE 19. GAIN AND PHASE ERROR CONTROL TABLE 20. DIGITAL LOOP FILTER CONTROL

31 Reserved 0

30 Invert Phase Error 1

29 Invert Frequency Error 0

28 Disable Offset Frequency 1

0 Zero Loop Filter Accumulator 0

TABLE 21. LOCK DETECT CONTROL

31 Use Analog PLL lock status bit for Lock Detection 0

25 Enable Analog PLL 0

24 Use Analog PLLCLK for CLK 0

0 Greater than Threshold Decrement

TABLE 22. INTERRUPT STATUS

7 Not Used 0

6 FIFO Full 0

5 FIFO Empty 0

4 FIFO Overflow 0

3 FIFO Underflow 0

2 Digital PLL Lock Detect 0

1 Analog PLL Lock Detect 0

0 Reset Done 0

TABLE 23. INTERRUPT ENABLE TABLE 24. CARRIER FREQUENCY TABLE 25. SYMBOL FREQUENCY TABLE 26. DIGITAL LOOP FILTER UPPER LIMIT TABLE 27. DIGITAL LOOP FILTER LOWER LIMIT TABLE 28. FIFO RESET STROBE TABLE 29. MEMORY BUFFER UPDATE STROBE appropriate MasterReg byte to the memory Buffer.

Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 2) θJA (°C/W) Vapor Phase Soldering, 1 Minute CAUTION: Stresses above those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. 26 FN4559.6 April 23, 2007 Electrical Specifications VDD = +3.3V ±5%, TA = -40°C to +85°C, Unless Otherwise Specified PARAMETER TEST CONDITION MIN TYP MAX UNITS POWER SUPPLY CHARACTERISTICS Power Supply Voltage, AVDD, DVDD 3.15 3.3 3.45 V Supply Current (IVDD) IOUTFS = 20mA - 420 500 mA Power Dissipation IOUTFS = 20mA - - 1.75 W Supply Current (IVDD) Sleep Mode DAC in sleep mode CLK stopped - 4 6 mA Power Supply Rejection Single Supply -0.2 - +0.2 %FSR/V DC CHARACTERISTICS: DIGITAL I/O Input Logic Low Voltage, VIL - - 0.8 V Input Logic High Voltage, VIH 2.0 - - V Input Logic Low Current, IIL VIN = 0.0V -10 - 10 μA Input Logic High Current, IIH VIN = DVDD -10 - 10 μA Output Tristate Low Current, IXL -10 - 10 μA Output Tristate High Current, IXH -10 - 10 μA Input Capacitance, CIN (Note 1) - 6 - pF Output Logic Low Voltage, VOL IOL = 2mA - - 0.4 V Output Logic High Voltage, VOH IOH = -2mA 2.6 - - V Output Capacitance, COUT (Note 1) - 6 - pF AC CHARACTERISTICS: DIGITAL CONTROL AND PROCESSOR INTERFACE CLK Frequency, fCLK - - 100 MHz CLK High, tCH (Note 1) 4 - - ns CLK Low, tCL (Note 1) 4 - - ns RESET Setup Time, tRTS To CLK, (Note 1) 3 - - ns RESET Hold Time, tRTH From CLK, (Note 1) 1 - - ns RESET Pulsewidth, tRPW CLK Cycles, (Note 1) 10 - - Cycles WR Frequency - - CLK/4 MHz Setup Time, tS CDATA<7:0>, ADDR<2:0> and CE to WR, (Note 1) 15 - - ns Hold Time, tH CDATA<7:0>, ADDR<2:0> and CE from WR, (Note 1) 0 - - ns CDATA<7:0> Output Delay, tDA CDATA<7:0> from ADDR<2:0>, (Note 1) - - 20 ns CDATA<7:0> Output Delay, tDW CDATA<7:0> from WR, (Note 1) - - 20 ns AC CHARACTERISTICS: DIGITAL I/Q DATA INPUT DATACLK Frequency, FDCLK - - CLK / 2 MHz DATACLK High, TDCH 5 - - ns HSP50415

27 FN4559.6 April 23, 2007 DATACLK Low, tDCL 5 - - ns Setup Time, tDS DIN<15:0>, TXEN, ISTRB to DATACLK, (Note 1) 8 - - ns Hold Time, tDH DIN<15:0>, TXEN, ISTRB from DATACLK, (Note 0 - - ns AC CHARACTERISTICS: DIGITAL STATUS / DATA REFCLK Frequency, fRCK - - CLK / 4 MHz REFCLK High, tRCH 5 - - ns REFCLK Low, tRCL 5 - - ns Digital Status and Output Data Delay, tDO From SYSCLK/2 Includes IOUT<13:0>, FIFO status pins, LOCKDET and INTREQ., (Note 1) - - 5 ns ANALOG OUTPUT PERFORMANCE: Resolution 12 - - Bits Integral Linearity Error, INL “Best Fit” Straight Line (Note 4) - ±1 - LSB Differential Linearity Error, DNL (Note 4) - ±0.5 - LSB Offset Error, IOS (Note 4) -0.025 +0.025 % FSR Offset Drift Coefficient (Note 4) - 0.1 - ppm FSR/oC Full Scale Gain Error, FSE With External Reference (Notes 3, 4) -10 ±2 +10 % FSR With Internal Reference (Notes 3, 4) -10 ±1 +10 % FSR Full Scale Gain Drift With External Reference (Note 4) - ±50 - ppm FSR/oC With Internal Reference (Note 4) - ±100 - ppm FSR/oC Full Scale Output Current, IFS 2 - 20 mA Output Capacitance (Note 1) - 30 - pF Output Voltage Compliance Range (Note 1, 4) -1.0 - 1.25 V Gain Matching Between Channels -8 - +8 % FSR Offset Matching Between Channels - ±0.05 - % FSR Phase Matching Between Channels (Note 1) - ±0.5 - Degrees VOLTAGE REFERENCE: Internal Reference Voltage, VREF - 1.23 - V Internal Reference Voltage Drift (Note 1) - ±40 - ppm/oC Internal Reference Output Current Sink/Source Capability (Note 1) - ±0.1 - μA Reference Input Impedance (Note 1) - 1 - MΩ Reference Input Multiplying Bandwidth (Notes 1, 4) - 1.4 - MHz NOTES: 1. Parameter guaranteed by design or characterization and not production tested. 2. θJA is measured with the component mounted on an evaluation PC board in free air. 3. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625μA). Ideally the ratio should be 32. 4. See ‘Definition of DAC Specifications’ section. Electrical Specifications VDD = +3.3V ±5%, TA = -40°C to +85°C, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITION MIN TYP MAX UNITS HSP50415

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN4559.6 April 23, 2007 HSP50415 Metric Plastic Quad Flatpack Packages (MQFP) D E E1 -A- PIN 1 A2 A1 A 12o-16o 12o-16o 0o-7o 0.40

0.016 MIN

L 0o MIN PLANE b 0.005/0.009 0.13/0.23WITH PLATING BASE METAL SEATING 0.005/0.007 0.13/0.17 -B- e 0.008

0.20 A-B SD SCM

0.076 0.003 -C- -D- -H- Q100.14x20 (JEDEC MS-022GC-1 ISSUE B)

100 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE

A- 0.134 - 3.40 - A1 0.010 - 0.25 -- A2 0.101 0.113 2.57 2.87 - b 0.009 0.015 0.22 0.38 6 b1 0.009 0.013 0.22 0.33 - D 0.908 0.918 23.08 23.32 3 D1 0.782 0.792 19.88 20.12 4, 5 E 0.673 0.681 17.10 17.30 3 E1 0.547 0.555 13.90 14.10 4, 5 L 0.029 0.040 0.73 1.03 - N 100 100 7 e 0.026 BSC 0.65 BSC - ND 30 30 - NE 20 20 - Rev. 1 4/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and toler ances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane . 4. Dimensions D1 and E1 to be determined at datum plane 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. “N” is the number of terminal positions. -C- -H-