HSP50306 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 8
Technical content
Features
- 25.6MHz or 26.97MHz Clock Rates
- Single Chip QPSK Demodulator with 10kHz Tracking Loop
- Square Root of Raised Cosine ( = 0.4) Matched Filtering
- 2.048 MBPS Reconstructed Output Data Stream
- Bit Synchronization with 3kHz Loop Bandwidth
- Internal Equalization for Multipath Distortion
- 6-Bit Real Input: Digitized 10.7MHz or 2.1MHz IF
- Level Detection for External IF AGC Loop
- 0.1s Acquisition Time
- 1 0 -9 BER
- <116mA on +5.0V Supply
Applications
- Cable Data Link Receivers
- Cable Control Channel Receivers
Description
The HSP50306 is a 6-bit QPSK demodulator chip designed for use in high signal to noise environments which have some multipath distortion. The part recovers 2.048 MBPS data from samples of a QPSK modulated 10.7MHz or 2.1MHz carrier. The chip coherently demodulates the waveform, recovers symbol timing, adaptively equalizes the signal to remove multipath distortion, differentially decodes and multiplexes the data decisions. 8-A lock signal is provided to indicate when the tracking loops are locked and the data decisions are valid. To optimize performance, a gain error feedback signal is provided which can be filtered and used to close an I.F. AGC loop around the A/D converter. The QPSK demodulator derives a ll timing from CLKIN. The chip divides this clock by 2 to provide the sample clock for the external A/D converter. The -27 version operates at a clock input of 26.97MHz and demodulates a 10.7MHz QPSK signal to recover the 2048 KSPS data. The -25 version operates at a clock input of 25.6MHz and demodulates a 2.1MHz QPSK signal to recover the 2048 KSPS data. Variation from these CLKIN frequencies will progressively degrade the receive data rate, the receive IF, acquisition sweep rate, acquisition sweep range and loop bandwidths as the deviation increases from normal CLKIN. Details on the maximum allowable devia- tion are found in the Input Characteristics section. The HSP50306 processes 6-bit offset binary data. 4-bit data pro- vides adequate performance for many applications. Block Diagram
Ordering Information
TEMP. RANGE (°C) PACKAGE PKG. DWG. # HSP50306SC-27 0 to 70 16 Ld SOIC M16.3 NCO SINCOS
4 TAP
DIFF. DECODE/ MUX CARRIER LOOP FILTER LOCK DETECT 6DIN0-5 AGCOUT ADCLK CLKIN CLKOUT DATAOUT LOCK I Q EQUALIZER LEVEL DETECT GENERATOR I Q RESET TEST
FN4162 Rev 3.00 Page 2 of 8 Jul 2004 Pinout
16 LEAD SOIC
NAME SOIC PIN TYPE DESCRIPTION VCC 16 - +5V Power Supply GND 8 - Ground CLKIN 7 I Clock input. This is the pr ocessing clock for the part. All timing is derived from this clock. DIN (5:0) 9-14 I I.F. input samples from the A/D converter. These bits interpreted as offset binary format. DIN5 is the MSB. If fewer than 6 bits are used, the bits from the A/D shoul d be connected to the MSBs of the input and the unused LSBs grounded. ADCLK 15 O This output clock is t he clock for the A/D converter. AGCOUT 1 O This output indicates whether the magnitude of the inpu t samples are above or below the expected level. This output is provided as an error detector for an exte rnal AGC loop. The output is low when the input is greater than nominal, and high when the input is lower than nominal. DATAOUT 3 O This is the recovered data. CLKOUT 2 O This is the recovered clock. LOCK 4 O This signal indicates that the carrier tracking loop is locked and data on the DOUT pin should be valid. RESET 5 I This input is provided to for initialization and test. Active low. TEST 6 I This input is provided for te st. Pull high for normal operation. AGCOUT CLKOUT DATAOUT TEST CLKIN GND VCC DIN0 DIN1 DIN2 DIN3 DIN5 ADCLK DIN4 RESET LOCK
cuitry generates the AGC error signal by rectifying the I.F. threshold, high if the magnitude is below the lower limit. Figure 1 shows the circuit of a typical demodulator application.
2.048 MBPS
FIGURE 1. APPLICATIONS CIRCUIT EXAMPLE NOTE: Simulation performed using alpha = 0.4 Root Raised Cosine Transmit Filtering, Multipath -10dBc at 72° at 1.6s. FIGURE 2. TYPICAL BIT ERROR RATE PERFORMANCE
TABLE 1. PERFORMANCE SPECIFICATIONS Acquisition Time Acqui sition within 0.1s from applying an input signal with the specified characteristics. Throughput Delay Less than 6 output bit times. TABLE 2. INPUT SIGNAL CHARACTERISTICS (NOTE 1) Filtering Square root of raised cosine matched filtering ( = 0.4). Input RMS Signal Level Set input p -p signal to full scale on the A/D converter. Input Data Format 6 bits, offset binary. SINAD >25.5dB SNR (thermal (A WGN)), >28dB (adjacent channel interference). may exceed the above specification until the equalizer has readjusted.
- All frequencies are relative to the input clock frequency. For example, the bit rate is actually ~0.075936 * fCLK. The frequencies provided
in this document are only valid for a 26.97MHz or 25.6MHz clock.
- Each pair of input bits is encoded into a phase change relative to the previous symbol. In the HSP50306, the symbol to symbol phase
change is decoded into the transmitted bit pair which is multiplexed into the output data stream.
- While the device is static CMOS and can be clocked down to close to DC, the specified range indicates the accuracy needed to maintain
the data rate inside the bit sync tracking loop bandwidth assuming 50ppm tx and 100ppm rx crystal accuracies.
FN4162 Rev 3.00 Page 6 of 8 Jul 2004 Absolute Maximum Ratings TA = 25°C Thermal Information Operating Conditions Thermal Resistance (Typical, Note 4) JA (°C/W) (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 4. JA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Power Supply Current I CCOP VCC = Max, CLK = 28.6MHz (Notes 5, 6) - 114 mA Standby Power Supply Current I CCSB VCC = Max, Outputs Not Loaded - 500 A Input Leakage Current I I VCC = Max, Input = 0V or VCC -10 10 A CMOS Output High (ADCLK, AGCOUT) V OHC VCC = Min, IOH = -400A3 . 7 - V CMOS Output Low (ADCLK, AGCOUT) V OLC VCC = Min, IOL = 2mA - 0.4 V Logical One Input Voltage V IH VCC = Max 2.0 - V Logical Zero Input Voltage V IL VCC = Min - 0.8 V Logical One Output Voltage V OH IOH = -400A, VCC = Min 2.4 - V Logical Zero Output Voltage V OL IOL = 2mA, VCC = Min - 0.4 V Input Capacitance C IN CLK = 1MHz All measurements referenced to GND. T A = 25°C, (Note 7) -1 0 p F Output Capacitance C OUT -1 0 p F NOTES: 5. Power supply current is proportional to frequency. Typical rating is 4mA/MHz. 6. Output load per test circuit and CL = 40pF. 7. Not tested, but characterized at initial design and at major process/design changes.
FN4162 Rev 3.00 Page 7 of 8 Jul 2004 AC Test Load Circuit PARAMETER SYMBOL NOTES MIN MAX UNITS CLK Period t CP 36 - ns CLK High t CH 12 - ns CLK Low t CL 12 - ns Setup RESET to CLK t RS 15 - ns Hold Time RESET to CLK t RH 1- n s Setup Time DIN0-5 to ADCLK t DS 91 5- n s Hold Time DIN0-5 to ADCLK t DH 92- n s CLK to DATAOUT, LOCK, AGCOUT t PD -2 5 n s Output Rise, Fall Time t RF 10 - 8 ns Output Rise, Fall Time (CMOS Outputs) t TC 10 - 12 ns NOTES: transition measured at VOH_1.5V and VOL_1.5V. 9. The set up and hold times for DIN (5:0) are with respect to the rising edge of ADCLKOUT. These parameters are guaranteed by design and characterization but not tested. An A/D converter with a clock to data out specification of 55ns and a data hold from clock specification of 2ns will meet these requirements at an oscillator clock frequency of 26.97MHz. Intersil recommends the CA3304 or CA3306 A/D con- verters for use with the HSP50306. 10. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes. SWITCH S1 OPEN FOR ICCSB AND ICCOP EQUIVALENT CIRCUIT CL IOH 2.5V I OL DUT S1 (NOTE) NOTE: Test head capacitance