HSP50216KIZ

HSP50216_06 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 58

Technical content

Features

• Up to 70MSPS Input
• Four Independently Programmable Downconverter Channels in a single package
• Four Parallel 16-Bit Inputs - Fixed or Floating Point Format
• 32-Bit Programmable Carrier NCO with > 115dB SFDR
• 110dB FIR Out of Band Attenuation
• Decimation from 8 to >65536
• 24-bit Intern al Data Path
• Digital AGC with up to 96dB of Gain Range
• Filter Functions - 1 to 5 Stage CIC Filter - Halfband Decimation and Interpolation FIR Filter - Programmable FIR Filter - Resampling FIR Filter
• Cascadable Filtering for Additional Bandwidth
• Four Independent Serial Outputs
• 3.3V Operation
• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Narrow-Band TDMA through IS-95 CDMA Digital Software Radio and Basestation Receivers
• Wide-Band Applications: W-CDMA and UMTS Digital Software Radio and Basestation Receivers

Ordering Information

(°C) PACKAGE PKG. NO HSP50216KI HSP50216KI -40 to 85 196 Ld BGA V196.12x12 HSP50216KIZ (Note) HSP50216KIZ -40 to 85 196 Ld BGA (Pb-free) V196.12x12 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Data Sheet July 31, 2006

μP INTERFACE A(15:0) CLK LEVEL NCO / MIXER / CIC INPUT SELECT, FORMAT, DEMUX DETECTOR μP TEST REGISTER μP MODE B(15:0) C(15:0) D(15:0) RESET SYNCI SYNCO CHANNEL 0 P(15:0) ADD(2:0) WR CE SCLK RD or DSTRB or RD / WR INTRPT SYNCA SDIA SD2A OUTPUT SELECT, FORMAT, SERIALIZE INPUT SELECT, FORMAT, DEMUX BUS I Q NCO / MIXER / CIC CHANNEL 1 INPUT SELECT, FORMAT, DEMUX I Q NCO / MIXER / CIC CHANNEL 2 INPUT SELECT, FORMAT, DEMUX I Q NCO / MIXER / CIC CHANNEL 3 INPUT SELECT, FORMAT, DEMUX I Q ROUTING SYNCB SDIB SD2B SYNCC SDIC SD2C SYNCD SDID SD2D ENIA ENIB ENIC ENID FIR FILTERS, AGC, CARTESIAN-TO-POLAR COORDINATE CONVERTER FIR FILTERS, AGC, CARTESIAN-TO-POLAR COORDINATE CONVERTER FIR FILTERS, AGC, CARTESIAN-TO-POLAR COORDINATE CONVERTER FIR FILTERS, AGC, CARTESIAN-TO-POLAR COORDINATE CONVERTER HSP50216

196 LEAD BGA

K J H G F E D C B A 123456789 1 1 10 L M N VCC D9GNDVCC 13 14 C14 C10 C8 GND VCC GND D11 ENIDD13B1 D 1 5 D 3D 1D 0B0 C 1 2 C 6C 4C 2C 0 B3 WRB2 B5 GND P0VCC B7 P2GND CLK GND P4VCC B9 VCC P6GND B11 GND P8VCC B13 P10GND B15 P12 SD2C SD2DSD2BSD1B INTRPT P15ENIA A12 A14 SD2A SD1CGNDVCCGND ADD0A8 A10 GNDVCC SCLK SYNCCSYNCBSYNCA SYNCD SYNCI SYNCOA7 A9 A11 A13 A15 SD1A P D12 D10D14C13 ENIC D8 D6 D4C 1 1 C 9C 7C 5C 3C 1 POWER PIN GROUND PIN SIGNAL PIN THERMAL BALL NC (NO CONNECTION) B12 B14 B10 GND B6 VCCP3 A6A3 VCC SD1D ADD1 A4A2A1 P14 A0 P13RESET VCCP11 B4 P1 ENIB RDCE C15 D5 D2 ADD2 μP MODE HSP50216

VCC - Positive Power Supply Voltage, 3.3V ±0.15 GND - Ground, 0V. INPUTS A(15:0) I Parallel Data Input bus A. Samp led on the rising edge of clock when ENIA is active (low). B(15:0) I Parallel Data Input bus B. Samp led on the rising edge of clock when ENIB is active (low). C(15:0) I Parallel Data Input bus C. Samp led on the rising edge of clock when ENIC is active (low). D15 I Parallel Data Input D15 or tuner channel A COF. D14 I Parallel Data Input D14 or tuner channel A COFSync. D13 I Parallel Data Input D13 or tuner channel A SOF. D12 I Parallel Data Input D12 or tuner channel A SOFSync. D11 I Parallel Data Input D11 or tuner channel B COF. D10 I Parallel Data Input D10 or tuner channel B COFSync. D9 I Parallel Data Input D9 or tuner channel B SOF. D8 I Parallel Data Input D8 or tuner channel B SOFSync. D7 I Parallel Data Input D7 or tuner channel C COF. D6 I Parallel Data Input D6 or tuner channel C COFSync. D5 I Parallel Data Input D5 or tuner channel C SOF. D4 I Parallel Data Input D4 or tuner channel C SOFSync. D3 I Parallel Data Input D3 or tuner channel D COF. D2 I Parallel Data Input D2 or tuner channel D COFSync. D1 I Parallel Data Input D1 or tuner channel D SOF. D0 I Parallel Data Input D0 or tuner channel D SOFSync. ENIA I Input enable for Parallel Data Input bus A. Active low. This pin enables the input to the part in one of two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENI is asserted. ENIB I Input enable for Parallel Data Input bus B. Active low. This pin enables the input to the part in one of two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENI is asserted. ENIC I Input enable for Parallel Data Input bus C. Active low. This pin enables the input to the part in one of two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENI is asserted. ENID I Input enable for Parallel Data Input bus D. Active low. This pin enables the input to the part in one of two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENI is asserted. CONTROL CLK I Input clock. All processing in t he HSP50216 occurs on the rising edge of CLK. SYNCI I Synchronization Input Signal. Used to align the proc essing with an external event or with other HSP50216 devices. SYNCI can update the carrier NCO, reset decimation counters, restart the filter compute engine, and restart the output section among other functions. For most of the functional blocks, the response to SYNCI is programmable and can be enabled or disabled. SYNCO O Synchronization Output Signal . The processing of multiple H SP50216 devices can be synchronized by tying the SYNCO from one HSP50216 device (the master) to the SYNCI of all the HSP50216 devices (the master and slaves). RESET I Reset Signal. Active low. Asserting reset will halt all processing and set certain registers to default values. HSP50216

SD1A O Serial Data Output 1A. A serial data stream output which can be programmed to consist of I1, Q1, I2, Q2, magnitude, phase, frequency (dφ/dt), AGC gain, and/or zeros. In addition, data outputs from Channels 0, 1, 2 and 3 can be multiplexed into a common serial output data stream. Information can be sequenced in a programmable order. See Serial Data Output Formatter Section. SD2A O Serial Data Output 2A. This output is provided as an auxiliary output for Serial Data Output 1A to route data to a second destination or to output two words at a time for higher sample rates. SD2A has the same programmability as SD1A except that fl oating point format is not available. See Serial Data Output Formatter Section and Microprocessor Interface section. SD1B O Serial Data Output 1B. See description for SD1A. SD2B O Serial Data Output 2B. See description for SD2A. SD1C O Serial Data Output 1C. See description for SD1A. SD2C O Serial Data Output 2C. See description for SD2A. SD1D O Serial Data Output 1D. See description for SD1A. SD2D O Serial Data Output 2D. See description for SD2A. SCLK O Serial Output Clock. Can be programmed to be at 1, 1/2, 1/4, 1/8, or 1/16 times the clock frequency. The polarity of SCLK is programmable. SYNCA O Serial Data Output 1A sync signal. This signal is us ed to indicate the start of a data word and/or frame of data. The polarity and position of SYNCA is programmable. SYNCB O Serial Data Output 1B sync signal. This signal is us ed to indicate the start of a data word and/or frame of data. The polarity and position of SYNCB is programmable. SYNCC O Serial Data Output 1C sync signal. This signal is used to indicate the start of a data word and/or frame of data. The polarity and position of SYNCC is programmable. SYNCD O Serial Data Output 1D sync signal. This signal is used to indicate the start of a data word and/or frame of data. The polarity and position of SYNCD is programmable. MICROPROCESSOR INTERFACE P(15:0) I/O Microprocessor Interface Data bus. See “Microprocessor Interface” on page 29. P15 is the MSB. ADD(2:0) I Microprocessor Interface Address bus. ADD2 is the MSB. See “Microprocessor Interface” on page 29. Note: ADD2 is not used but designated for future expansion. WR or DSTRB I Microprocessor Interface Write or Data Strobe Signal. When the Microprocessor Interface Mode Control, μP MODE, is a low data transfers (from either P(15:0) to the internal write holding register or from the internal write holding register to the target register specified) occur on the low to high transition of WR when CE is asserted (low). When the μP MODE control is high this input fu nctions as a data read/write strobe. In this mode with RD/WR low data transfers (from either P(15:0) to the internal write holding register or from the internal write holding register to the target register specified) occur on the low to high transition of Data Strobe. With RD/WR high the data from the address specified is placed on P(15:0) when Data Strobe is low. See “Microprocessor Interface” on page 29. RD or RD/WR I Microprocessor Interface Read or Read/Write Signal. When the Microprocessor Interface Mode Control, μP MODE, is a low the data from the address specified is placed on P(15:0) when RD is asserted (low) and CE is asserted (low). When the μP MODE control is high this input functions as a Read/Write control input. Data is read from P(15:0) when high or written to the appropriate register when low. See “Microprocessor Interface” on page 29. μP MODE I Microprocessor Interface Mode Control. This pin is used to select the Read/Write mode for the Microprocessor Interface. Internally pulled down. See “Microprocessor Interface” on page 29. CE I Microprocessor Interface Chip Select. Active low. This pin has the same timing as the address pins. INTRPT O Microprocessor Interrupt Signal. Asserted for a prog rammable number of clock cycles when new data is available on the selected Channel. Pin Descriptions (Continued) NAME TYPE DESCRIPTION HSP50216

The HSP50216 is a four channel digital receiver integrated circuit offering exceptional dynamic range and flexibility. Each of the four channels consists of a front-end NCO, digital mixer, and CIC-filter block and a back-end FIR, AGC and Cartesian to polar coordinate-conversion block. The parameters for the four channels are independently programmable. Four parallel data input busses (A(15:0), B(15:0), C(15:0) and D(15:0)) and four pairs of serial data outputs (SDxA, SDxB, SDxC, and SDxD; x = 1 or 2) are provided. Each input can be connected to any or all of the internal signal processing channels, Channels 0, 1, 2 and 3. The output of each channel can be routed to any of the serial outputs. Outputs from more than one channel can be multiplexed through a common output if the channels are synchronized. The four channels share a common input clock and a common serial output clock, but the output sample rates can be synchronous or asynchronous. Bus multiplexers between the front end and back end sections provide flexible routing between channels for cascading back-end filters or for routing one front end to multiple back ends for polyphase filtering or systolic arrays (to provide wider bandwidth filtering). A level detector is provided to monitor the signal level on any of the parallel data input busses, facilitating microprocessor control of gain blocks prior to an A/D converter. Each front end NCO/digital mixer/CIC filter section includes a quadrature numerically controlled oscillator (NCO), digital mixer, barrel shifter and a cascaded-integrator-comb filter (CIC). The NCO has a 32-bit frequency control word for 16.3mHz tuning resolution at an input sample rate of 70MSPS. The SFDR of the NCO is >115dB. The barrel shifter provides a gain of between 2 -45 and 2-14 to prevent overflow in the CIC. The CIC filter order is programmable between 1 and 5 and the CIC decimation factor can be programmed from 4 to 512 for 5 th order, 2048 for 4th order, 32768 for 3rd order, or 65536 for 1st or 2nd order filters. Each channel back end section includes an FIR processing block, an AGC and a cartesian-to-polar coordinate converter. The FIR processing block is a flexible filter compute engine that can compute a single FIR or a set of cascaded decimating filters. A single filter in a chain can have up to 256 taps and the total number of taps in a set of filters can be up to 384 provided that the decimation is sufficient. The HSP50216 calculates 2 taps per clock (on each channel) for symmetric filters, generally making decimation the limiting factor for the number of taps available. The filter compute engine supports a variety of filter types including decimation, interpolation and resampling filters. The coefficients for the programmable digital filters are 22 bits wide. Coefficients are provided in ROM for several halfband filter responses and for a resampler. The AGC section can provide up to 96dB of either fixed or automatic gain control. For automatic gain control, two settling modes and two sets of loop gains are provided. Separate attack and decay slew rates are provided for each loop gain. Programmable limits allow the user to select a gain range less than 96dB. The outputs of the cartesian-to-polar coordinate conversion block, used by the AGC loop, are also provided as outputs to the user for AM and FM demodulation. The HSP50216 supports both fixed and floating point parallel data input modes. The floating point modes support gain ranging A/D converters. Gated, interpolated and multiplexed data input modes are supported. The serial data output word width for each data type can be programmed to one of ten output bit widths from 4-bit fixed point through 32- bit IEEE 754 floating point. The HSP50216 is programmed through a 16-bit microprocessor interface. The output data can also be read via the microprocessor interface for all channels that are synchronized. The HSP50216 is specified to operate to a maximum clock rate of 70MSPS over the industrial temperature range (-40 oC to 85oC). The power supply voltage range is 3.3V ± 0.15V. The I/Os are not 5V tolerant. HSP50216

Each front end block and the level detector block contains an input select/format block. A functional block diagram is provided in the above figure. The input source can be any of the four parallel input busses (See Microprocessor Interface section, Table 3, “CHANNEL INPUT SELECT/FORMAT REGISTER (IWA = *000h),” on page 32 or a test register loaded via the processor bus (see Microprocessor Interface section, Table 42, “mP/TEST INPUT BUS REGISTER (GWA = F807h),” on page 45). The input to the part can operate in a gated or interpolated mode. Each input channel has an input enable (ENIx,x=A , B, C or D). In the gated mode, one input sample is processed per clock that the ENIx signal is asserted (low). Processing is disabled when ENIx is high. The ENIx signal is pipelined through the part to minimize delay (latency). In the interpolated mode, the input is zeroed when the ENIx signal is high, but processing inside the part continues. This mode inserts zeros between the data samples, interpolating the input data stream up to the clock rate. On reset, the part is set to gated mode and the input enables are disabled. The inputs are enabled by the first SYNCI signal. The input section can select one channel from a multiplexed data stream of up to 8 channels. The input enable is delayed by 0 to 7 clock cycles to enable a selection register. The register following the selection register is enabled by the non-delayed input enable to realign the processing of the channels. The one-clock-wide input enable must align with the data for the first channel. The desired channel is then selected by programming the delay. A delay of zero selects the first channel, a delay of 1 selects the second, etc. A(15:0) ENIA B(15:0) ENIB C(15:0) ENIC D(15:0) ENID NOTE: ENI* SIGNALS ARE ACTIVE HIGH (INVERTED AT THE I/O PAD) TESTENBIT TESTENSTRB MUX MUX EXTERNAL DATA INPUT SELECT (IWA *000 - 14:13 or GWA F804 - 14:13) MUX μP TEST REGISTER (GWA F807 - 15:0) (IWA *000 - 11 (GWA F808) or GWA F804 - 11) TEST ENI SELECT (IWA *000 - 12 EXTERNAL/TEST SELECT (IWA *000 - 15 or GWA F804 - 15)or GWA F804 - 12) 15:0 15:0 TESTEN ENI 15:0 EN OFFSET BINARY OR TWO’s COMPLEMENT (IWA *000 - 10 or GWA F804 - 10) FORMAT FLOATING POINT TO FIXED POINT MUX 11/3, 12/3, 13/3, 14/2 (IWA *000 - 8:7 or GWA F804 - 8:7) R E G PROGRAMMABLE DELAY DE-MULTIPLEX CONTROL (0-7) (IWA *000 - 6:4 or GWA F8O4 - 6:4) 15:0 FIXED POINT OR FLOATING POINT (IWA *000 - 9 or GWA F804 - 9) DATA TO NCO / MIXER INTERPOLATED/GATED MODE (IWA *000 - 3 or GWA F804 - 3) INPUT ENABLE HOLD OFF (ENABLED BY SYNCI) (GWA F802 - 30) DATA SAMPLE ENABLE CARRIER OFFSET FREQUENCY (COF) COF SYNC ENABLE COF RESAMPLER OFFSET FREQUENCY (SOF) SOF SYNC ENABLE SOF ENABLE PN (IWA *000 - 0) PN COF TO CARRIER NCO/MIXER COF SYNC TO CARRIER NCO/MIXER SOF TO RESAMPLER NCO SOF SYNC TO RESAMPLER NCO PN TO CARRIER NCO/MIXER OR LEVEL DETECTOR HSP50216

The parallel input busses are 16 bits wide. The input format may be twos complement or offset binary format. A floating point mode is also supported. The floating point modes and the mapping of the parallel 16-bit input format is discussed below. Floating Point Input Mode Bit Mapping The input bit weighting for fixed point inputs on busses A, B, C, and D is: bit 15 (MSB): 2 For floating point modes, the least significant 2 or 3 bits are used as exponent bits (See Floating Point Input Mode Bit Mapping Tables). The difference between the four floating point modes with three exponent bits is where the exponent saturates. Floating Point Input Mode Bit Mapping Tables 1 5 1 41 3 1 2 1 1 1 0 9876 5 4 3 2 1 0 11-BIT MODE: 11 to 13-BIT MANTISSA , 3-BIT EXPONENT, 30dB EXPONENT RANGE EXPONENT GAIN (dB) PIN BIT WEIG HTING TO 16-BIT INPUT MAPPING 000 0 X15 X15 X15 X15 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 001 6 X15 X15 X15 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 0 1 0 1 2 X 1 5 X 1 5 X 1 5 X 1 5 X 1 4 X 1 3 X 1 2 X 1 1 X 1 0 X 9X 8X 7X 6X 5X 4X 3 011 18 X15 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 1 0 0 2 4 X 1 5 X 1 5 X 1 4 X 1 3 X 1 2 X 1 1 X 1 0 X 9X 8X 7X 6X 5X 4X 3 0 0 101 (Note 1) 30 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 0 0 NOTES: 1. Or 110 or 111, the exponent input saturates at 10. 2. “Xnn” = input A, B, C, or D bit nn. 12-BIT MODE: 12 to 13-BIT MANTISSA , 3-BIT EXPONENT, 24dB EXPONENT RANGE EXPONENT GAIN (dB) PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING 000 0 X15 X15 X15 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 001 6 X15 X15 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 010 12 X15 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 011 18 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 0 100 (Note 3) 24 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 0 0 NOTE: 3. Or 101, 110, or 111, the exponent input saturates at 100. 13-BIT MODE: 13-BIT MANTISSA, 3- BIT EXPONENT, 18dB EXPONENT RANGE EXPONENT GAIN (dB) PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING 000 0 X15 X15 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 001 6 X15 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 010 12 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 0 011 (Note 4) 18 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 0 0 NOTE: 4. Or 100, 101, 110, or 111, the exponent input saturates at 011. HSP50216

An input level detector is provided to monitor the signal level on any of the input busses. Which input bus, the input format, and the level detection type are programmable (see Microprocessor Interface section, Table 39, “INPUT LEVEL DETECTOR SOURCE SELECT/FORMAT REGISTER (GWA = F804h),” on page 44, Table 40, “INPUT LEVEL DETECTOR CONFIGURATION REGISTER (GWA = F805h),” on page 45 and Table 41, “INPUT LEVEL DETECTOR START STROBE REGISTER (GWA = F806h),” on page 45). This signal level represents the wideband signal from the A/D and is useful for controlling gain / attenuation blocks ahead of the converter. The supported monitoring modes are: integrated magnitude (like the HSP50214 without the threshold), leaky integration n =X n xA+Y n-1 x (1-A)) where A = 1, 2-8, 2-12, or 2-16 (see GWA = F805h), and peak detection. The measurement interval can be programmed from 2 to 65537 samples (or continuous for the leaky integrator and peak detect cases). The output is 32 bits and is read via the μP interface. NCO/Mixer After the input select/format section, the samples are multiplied by quadrature sine wave samples from the carrier NCO. The NCO has a 32-bit frequency control, providing sub-hertz resolution at the maximum clock rate. The quadrature sinusoids have exceptional purity. The purity of the NCO should not be the determining factor for the receiver dynamic range performance. The phase quantization to the sine/cosine generator is 24 bits and the amplitude quantization is 19 bits. The carrier NCO center frequency is loaded via the μP bus. The center frequency control is double buffered - the input is loaded into a center frequency holding register via the μP interface. The data is then transferred from the holding register to the active register by a write to a address IWA *006h or by a SYNCI signal, if loading via SYNCI is enabled. To synchronize multiple channels, the carrier NCO phase accumulator feedback can be zeroed on loading to restart all of the NCOs at the same phase. A serial offset frequency input is also available for each channel through the D(15:0) parallel data input bus (if that bus is not needed for data input). This is legacy support for HSP50210 type tracking signals. See IWA=*000 and *004 for carrier offset frequency parameters. After the mixers, a PN (pseudonoise) signal can be added to the data. This feature is provided for test and to digitally reduce the input sensitivity and adjust the receiver range (sensitivity). The effect is the same as increasing the noise figure of the receiver, reducing its sensitivity and overall dynamic range. For testing, the PN generator provides a wideband signal which may be used to verify the frequency response of a filter. The one bit PN data is scaled by a 16-bit programmable scale factor. The overall range for the PN is 0 to 1/4 full scale (see IWA = *001h). A gain of 0 disables the PN input. The PN value is formed as where S is the PN generator output bit (treated as a sign bit) and the 16 X’s refer to the PN Gain Register IWA = *001h. The minimum, non-zero, PN value is 2 -18 of full scale (-108dBFS) on each axis (-105dBFS total). For an input noise level of -75dBFS, this allows the SNR to be decreased in steps of 1/8dB or less. The I and Q PN codes are offset in time to decorrelate them. The PN code is selected and enabled in the test control register (F800h). The PN is added to the signal after the mix with the three sign bits aligned with the most significant three bits of the signal, so the maximum level is - 12dBFS and the minimum, non-zero level is -108dBFS. The PN code can be 2 15-1, 223-1 or 215-1 * 223-1. 14-BIT MODE: 14-BIT MANTISSA, 2- BIT EXPONENT, 12dB EXPONENT RANGE EXPONENT GAIN (dB) PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING 0 0 0 X 1 5 X 1 5 X 1 5 X 1 4 X 1 3 X 1 2 X 1 1 X 1 0 X 9X 8X 7X 6X 5X 4X 3X 2 01 6 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 0 10 (Note 5) 12 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 0 0 NOTE: 5. Or 11, the exponent input saturates at 10. PN Value SSS X X XXXXXXXXXXXX X X HSP50216

Next, the signal is filtered by a cascaded integrator/comb (CIC) filter. A CIC filter is an efficient architecture for decimation filtering. The power or magnitude squared frequency response of the CIC filter is given by: where M = Number of delays (1 for the HSP50216) N = Number of stages and R = Decimation factor. The passband frequency response for 1 st (N=1) though 5th (N=5) order CIC filters is plotted in Figure 8. The frequency axis is normalized to fS/R, making fS/R = 1 the CIC output sample rate. Figure 10 shows the frequency response for a th order filter but extends the frequency axis to fS/R = 3 (3 times the CIC output sample rate) to show alias rejection for the out of band signals. Figure 9 uses information from Figure 10 to provide the amplitude of the first (strongest) alias as a function of the signal frequency or bandwidth from DC. For example, with a 5 th order CIC and fS/R = 0.125 (signal frequency is 1/8 the CIC output rate) Figure 9 shows a first alias level of about -87 dB. Figure 9 is also listed in table form in Table 47. The CIC filter order is programmable from 0 to 5. The minimum decimation is 4. If the order is set to 0, there must be at least 4 clocks between samples or the decimation counter must be set to 4 to chose every 4th sample. The integrator bit widths are 69, 62, 53, 44, and 34 for the 1 st through 5th stages, respectively, while the comb bit widths are all 32. The integrators are sized for decimation factors of up to 512 with 5 stages, 2048 with 4 stages, 32768 with 3 stages, and 65536 with 1 or 2 stages. Higher decimations in the CIC should be avoided as they will cause integrator overflow. In the HSP50216, the integrators are slightly oversized to reduce the quantization noise at each stage. Pf() πMf()sin πf R-----⎝⎠ ⎛⎞sin HSP50216

A CIC filter has a gain of RN, where R is the decimation factor and N is the number of stages. Because the CIC filter gain can become very large with decimation, an attenuator is provided ahead of the CIC to prevent overflow. The 24 bits of sample data are placed on the low 24 bits of a 69 bit bus (width of the first CIC integrator) for a gain of 2 -45. A 32 bit barrel shifter then provides a gain of 20 to 231 inclusive before passing the data onto the CIC. The overall gain in the pre-CIC attenuator can therefore be programmed to be any one of 32 values from 2 -45 to 2-14, inclusive (see IWA=*004, bits 18:14). This shift factor is adjusted to keep the total barrel shifter and CIC filter between 0.5 and 1.0. The equation which should be used to compute the necessary shift factor is: Shift Factor = 45 - Ceiling(log 2(RN)). NOTE: With a CIC order of zero, the CIC shifter does not have sufficient range to route more than 10 bits to the back end since the maximum gain is 2-14 (the least significant 14 bits are lost). Back End Section One back-end processing section is provided per channel. Each back end section consists of a filter compute engine, a FIFO/timer for evenly spacing samples (important when implementing interpolation filters and resamplers), an AGC and a cartesian-to-polar coordinate conversion block. A block diagram showing the major functional blocks and data routing is shown above. The data input to the back end section is through the filter compute engine. There are two other inputs to the filter compute engine, they are a data recirculation path for cascading filters and a magnitude and dφ/dt feedback path for AM and FM filtering. There are seven outputs from each back end processing section. These are I and Q directly out of the filter compute engine (I2, Q2), I and Q passed through the FIFO and AGC multipliers (I1, Q1), magnitude (MAG), phase (or dφ/dt), and the AGC gain control value (GAIN). The I2/Q2 outputs are used when cascading back end stages. The routing of signals within the back end processing section is controlled by the filter compute engine. The routing information is embedded in the instruction bit fields used to define the digital filter being implemented in the filter compute engine. MAG: I dphi/dt: QAGC LOOP FILTER FILTER COMPUTE ENGINE MUX FIFO/ TIMER AGC MULT CART TO POLAR SHIFT d/dt M U X x1, x2 x4, x8 M U X FROM CIC PATH 0 PATH 1 PATH 2 (4:0) EXT AGC GAIN GAIN MAG PHASE DESTINATION BIT MAP (BITS 28:18 OF FIR INSTRUCTIONS BIT FIELD) 28 27 25 24 23 22 21 20 19 18 26, 25 22:18 AGC LOOP GAIN SELECT (PATH 01 ONLY) UPDATE AGC LOOP (PATH 01 ONLY) PATH 00 - - IMMEDIATE FILTER PROCESSOR FEEDBACK PATH 01 - - FIFO/AGC PATH 10 - - DIRECT OUT/CASCADE PATH 11 - - BOTH 00 AND 10 PATHS (FOR TEST) STROBE OUTPUT SECTION (START SERIAL OUTPUT WITH THIS SAMPLE) FEED MAG/PHASE BACK TO FILTER PROCESSOR FILTER PROCESSOR SEQUENCE STEP NUMBER HSP50216

The filter compute engine is a dual multiply-accumulator (MAC) data path with a microcoded FIR sequencer. The filter compute engine can implement a single FIR or a set of filters. For example, the filter chain could include two halfband filters, a shaping (matched) filter and a resampling filter, all with different decimations. The following filter types are currently supported by the architecture and microcode:

• Even symmetric with even # of taps decimation filters
• Even symmetric with odd # of taps decimation filters (including HBFs)
• Odd symmetric with even # of taps decimation filters
• Odd symmetric with odd # of taps decimation filters
• Asymmetric decimation filters
• Complex filters
• Interpolation filters (up to interpolate by 4)
• Interpolation halfband filters
• Resampling filters (under resampler NCO control)
• Fixed resampling ratio filter (within the available number of coefficients)
• Quadrature to real filtering (w/ fs/4 up conversion) The input to the filter compute engine comes from one of three sources - a CIC filter output (which can also be another backend section), the output of the filter compute engine (fed back to the input) or the magnitude and dφ/dt fed back from the cartesian-to-polar coordinate converter. The number and size of the filters in the chain is limited by the number of clock cycles available (determined by the decimation) and by the data and coefficient RAM/ROM resources. The data RAM is 384 words (I/Q pairs) deep. The data addressing is modulo in power-of-2 blocks, so the maximum filter size is 256. The block size and the block starting memory address for each filter is programmable so that the available memory can be used efficiently. The coefficient RAM is 192 words deep. It is half the size of the data memory because filter coefficients are typically symmetric. ROMs are provided with halfband filter coefficients, resampling filter coefficients, and constants. The filter compute engine exploits symmetry where possible so that each MAC can compute two filter taps per clock, by doing a pre-add before multiplying. In the case of halfband filters, the zero-valued coefficients are skipped for extra efficiency. There is an overhead of one clock cycle per input sample for each filter in the chain (for writing the data into the data RAM) and (except in special cases) a two clock cycle overhead for the entire chain for program flow control instructions. The output of the filter compute engine is routed through a FIFO in the main output path. The FIFO is provided to more evenly space the FIR outputs when they are produced in bursts (as when computing resampling or interpolation filters). The FIFO is four samples deep. The FIFO is loaded by the output of the filter when that path is selected. It is unloaded by a counter. The spacing of the output samples is specified in clock periods. The spacing can be set from 1 (fall through) to 4096 samples M U X I Q RAM 384 WORDS I Q RAMR/Wb ADDRA (8:0) ADDRB (8:0) S W A P S W A P A L U A L U R/dφ/dt 0..-23 INMUX (1:0) 0..-23 A B 1..-23 1..-25 WITH RND A B RAMAEN RAMBEN IQSWAP IFUNCT QFUNCT COEF S H F T R E G S H F T R E G L I M I T L I M I T R E G R E G R E G M U X M U X∑ENFB, RNDSEL (2:0) SHIFT (1:0) REGEN4 ENLIMIT ENHR1 ENHR2 OUTSEL DOWN SHIFT 0, 1, 2 PLACES 9..-31 0..-23 0..-21 COEF (21:0), SHIFT (1:0) NOTE: PIPELINE DELAYS OMITTED FOR CLARITY IQ HSP50216

(approximately the spacing for a 16KSPS output sample rate when using 65MSPS clock) using IWA = *00Ah bits 11:0. The number and order of the filtering in the filter chain is defined by a FIR control program. The FIR control program is a sequence of up to 32 instruction words. Each instruction word can be a filter or program flow instruction. The filter instruction defines a FIR in the chain, specifying the type of FIR, number of taps, decimation, memory allocation, etc. For program flow, a wait for input sample(s) instruction, a loop counter load, and several jumps (conditional and unconditional) are provided. The HSP50216 evaluation board includes software for automatically generating FIR control programs for most filter requirements. Examples of programs FIR control programs are given below. The simplest filter program computes a single filter. It has three instructions (see Sample Filter #1 Program Instructions below): The parameters of the FIR (including type, number of taps, decimation and memory usage) are specified in the bit fields of the step 1 instruction word. To change the filtering the only other change needed is the number of samples in the wait threshold register (IWA = *00C, bits 9:0). The filter in this example requires 52 clock cycles to compute, allocated as follows: Using a 65MSPS clock, the output sample rate could be as high as 65MSPS / 52 clocks = 1.25MSPS. The input sample rate to the FIR from the CIC filter would be 2.5MSPS. The impulse response length would be 38 μsec (95 taps at 0.4μs/tap). Each additional filter added to the signal processing chain requires one instruction step. As an example of this, a typical filter chain might consist of two decimate-by-2 halfband filters being followed by a shaping filter with the final filter being a resampling filter. The program for this case might be (see Sample Filter Program #2 Program Instructions below): SAMPLE FILTER #1 PROGRAM STEP INSTRUCTION

0 Wait for enough input samples

(equal to the decimation factor) 1F I R Type = even symmetric 95 taps Decimate by 2 Compute one output Decrement wait counter Memory block size 128 Memory block start at 64, Coefficient block start at 64 Step size 1 Output to AGC

2 Jump, Unconditional, to step 0

SAMPLE FILTER #1 CLOCK CYCLES CALCULATION CLOCK CYCLES FUNCTION PERFORMED

48 Clocks for FIR computation (two taps/clock due to

symmetry)

2 Clocks for writing the input data into the data RAMs

(Decimate by 2 requires 2 inputs per output)

2 Clocks for the program flow instructions (wait and

jump)

52 Total

SAMPLE FILTER #2 PROGRAM STEP INSTRUCTION

0 Wait for enough input samples (usually equal to the

total decimation -- 8 in this case) 1F I R Type = even symmetry 15 taps Halfband Decimate by 2 Compute four outputs Memory block size 32 Memory block start at 0 Coefficient block start at 13 Output to step 2 Decrement wait count 2F I R Type = even symmetry 23 taps Halfband Decimate by 2 Compute two outputs Memory block size 32 Memory block start at 32 Coefficient block start at 24 Output to step 3 3F I R Type = even symmetry 95 taps Decimate by 2 Compute one output Memory block size 128 Memory block start at 64 Coefficient block start at 64 Step size 1 Output to step 4 4F I R Type = resampler Increment NCO 6 taps Compute one output Memory block size 8 Memory block starts at 192 Coefficient block start at 512 Step size 32 Output to AGC

5 Jump, Unconditional, to 0

Sample filter #2 requires:

• 32 + 32 + 128 + 8 = 200 data RAM locations
• (95+1)/2=48 coefficient RAM location (resampler and HBF coefficients are in ROM). The number of clock cycles required to compute an output for Sample filter #2 is calculated as follows: Total decimation is 8, so the input sample rate for the FIR chain (CIC output rate) could be up to: fCLK/(ceil(105/8)) = fCLK/14. With a 65MHz clock, this would support a maximum input sample rate to the FIR processor of 4.6MHz and an output sample rate up to 0.580MHz. The shaping filter impulse response length would be: (95 x 2)/580,000 = 82μs. The maximum output sample rate is dependent on the length and number of FIRs and their decimation factors. Illustrating this concept with Filter Example #3, a higher speed filter chain might be comprised of one 19 tap decimate-by-2 halfband filter followed by a 30 tap shaping FIR filter with no decimation. The program for this example could be: The number of clock cycles required to compute an output for Sample filter #3 is calculated as follows: For Filter Example #3 and a 65MSPS input, the maximum FIR input rate would be 65MSPS / ceil(26 / 2) = 5MSPS giving a decimate-by-2 output sample rate of 2.5MSPS. At 70MSPS, the FIR could have up to 34 taps with the same output rate. Channels 0, 1, 2 and 3 can be combined in a polyphase structure for increased bandwidth or improved filtering. Filter Example #4 will be used to demonstrate this capability. Symbol rate of 4.096 MSym. The desired output sample rate is 8.192MSPS. Arrange the four back end sections as four filters operating on the same CIC output at a rate of 65.536MHz/4=16.384MHz, where the factor of 4 is the CIC decimation we have chosen. Each channel computes the same sequence, offset by one output sample from the previous sample (see IWA = *00Bh). Each channel decimates down to 2.048M and then the SAMPLE FILTER #2 CLOCK CYCLES CALCULATION CLOCK CYCLES FUNCTION PERFORMED

20 Halfband 1 compute clocks

(5 per compute x 4 computes)

8 Halfband 1 input sample writes (8 input samples)

14 Halfband 2 compute clocks

(7 per compute x 2 computes)

4 Halfband 2 input sample writes (4 input samples)

48 95 tap symmetric FIR, 2 clocks per tap

2 FIR input sample writes (2 input samples)

6 resampler (6 taps, nonsymmetric)

1 Resampler input sample write (1 input samples)

1 Jump instruction

1 Wait instruction

105 Clock cycles per output

SAMPLE FILTER #3 PROGRAM STEP INSTRUCTION

0 Wait for enough input samples (2 in this case)

Type = even symmetry 19 taps Halfband Decimate by 2 Compute one output Memory block size 32 Memory block start at 0 Coefficient block start at 18 Output to step 2 Reset wait count 2F I R Type = even symmetry 30 taps Decimate by 1 Compute one output Memory block size 64 Memory block start at 32 Coefficient block start at 64 Step size 1 Output to AGC

3 Jump, Unconditional, to 0

SAMPLE FILTER #3 CLOCK CYCLES CALCULATION CLOCK CYCLES FUNCTION PERFORMED 6 19 tap halfband, one output 2 halfband input writes (2 input samples) 15 30 tap symmetric FIR, 2 taps per clock 1 1 FIR input write 11 w a i t 11 j u m p

26 Clock cycles per output

SAMPLE FILTER #3 PROGRAM (Continued) STEP INSTRUCTION HSP50216

channels are multiplexed together in the output formatter to get the desired 8.192MSPS. The input sample rate to the final filter of each channel must meet Nyquist requirements for the final output to assure that no information is lost due to aliasing. The number of FIR taps available for these requirements is calculated as follows: 65536/2048 = 32 clocks minus (8 writes + 1 wait + 1 jump = 10 clocks) = 22 clocks Therefore, the number of taps available is: 22 x 2 = 44 taps. Multiplexing the four outputs gives a final output sample rate of 8.192MSPS. The impulse response is 44 taps at 16.384M or 22 output samples (11 symbols at 4.096M). The AGC loop filter output of channel 4 can be routed to control the forward AGC gain control of all four channels. This assures that the gains of the four back end sections are the same. The gain error, however, is only computed from every fourth output sample. The back end processing sections of two or more HSP50216s can be combined using the same polyphase approach, but the AGC gain from one part cannot be shared with another part (except via the μP interface), so polyphase filter using multiple parts would typically usually use a fixed gain. The filter sequencer is programmed via an instruction RAM and several control registers. These are described below. Instruction RAMs The filter compute engine is controlled by a simple sequencer supporting up to 32 steps. Each step can be a filter or one of four sequence flow instructions - wait, jump (conditional or unconditional), load loop counter, or NOP. There are 128 bits per instruction word with each word consisting of condition code selects, FIR parameters and data routing controls. Not all of the instruction word bits are used for all instruction types. The actual sequencer instruction is only 9 bits. The rest of the bits are used for filter parameters or for the loop counter preload. Each sequence step is loaded in four 32-bit writes. The mapping of the bit fields for the instruction types is shown in the instruction bit field table that follows. These FIR instruction words can be generated using software tools provided with the HSP50216 evaluation board. When the filter is reset, the instruction pointer is set to 31 (the last instruction step). The read and write pointers are initialized on reset, so a reset must be done when the channel is initialized or restarted. A fixed offset can be added to the starting read address of one of the filters in the program. This function is provided to offset the data reads of the filters in a polyphase filter bank -- all filters in the bank will write the same data to the same RAM location. To offset the computations the RAM read address is offset. See IWA = *00Bh for details. The instruction word bits (127:0) are assigned to memory words as follows: 31:0 to destination C C C C 0 0 0 1 0 x x x x x 0 0 63:32 to destination C C C C 0 0 0 1 0 x x x x x 0 1 95:64 to destination C C C C 0 0 0 1 0 x x x x x 1 0 127:96 to destination C C C C 0 0 0 1 0 x x x x x 1 1 where CCCC is the channel number and xxxxx is the instruction sequence step number (0 - 31 decimal). Note the μPHold bit in the filter compute engine control register (IWA = *00Ah) must be set for the microprocessor to read from or write to the instruction or coefficient RAMs. SAMPLE FILTER #4 PROGRAM STEP INSTRUCTION

0 Wait for enough input samples (8 in this case)

type = even symmetry 44 taps decimate by 8 compute one output memory block size 64 memory block start at 0 coefficient block start at 64 step size 1 output to AGC offset memory read pointers by 0, -2, -4, -6

2 Jump, Unconditional, to 0

B INSTRUCTION RAM, SEQUENCER WAIT COUNTER LOOP COUNTER FIR PARAMETER FIR# - WRITE DESTINATION FIR# - COMPUTE ALIAS MASK READ POINTER REG FILE WRITE POINTER REG FILE DATA PATH CONTROL ROM RAM ADDR GEN A COEF ADDR GEN COMPUTE COUNTERS DATA ADDRESS STEP SIZE COMPUTE TO COMPUTE FIR TYPE NUMBER OF OUTPUTS TAPS/OUTPUT READS/TAP INSTR/TAP START ADDRESS RAM ADDR INITIAL OFFSET RAM ADDR OFFSET STEP RAM ADDR BLOCK TO BLOCK STEP COEF ADDR BLOCK START COEF ADDR BLOCK SIZE COEF ADDR SIZE PER TAP ADDR STEP SIZE PER OUTPUT ADDRESS OFFSETRESAMPLER NCO LOOP COUNTER PRELOAD THRESHOLD DECREMENT 1 DECREMENT 2 NEW DATA, FIR # RESET SYNC FIR OUTPUT DESTINATION DATA PATH CONTROL SIGNALS DATA RAM A READ/WRITE ADDRESS DATA RAM B READ ADDRESSENABLE COEFFICIENT OFFSET READ ADDRESS RAM ADDR BLOCK START RAM ADDR BLOCK SIZE RAM ADDR STEP SIZE 1 RAM ADDR STEP SIZE 2 RAM ADDR BLOCK TO BLOCK STEP RAM HSP50216

POSITIONS FUNCTION DESCRIPTION 8:0 Instruction Instruction Field Bit Mapping B i t 876543210 Type W A I T 00XXXXCCC FIR 0 1 Start IncrRS DecrSel DecrEn LdLp DecrLp EnU/C J U M P 1JJJJJC C C (NOPs and loading the loop counter are special cases of the FIR instruction). XXXX = ignored. JJJJJ = jump destination (sequence step number). CCC = condition code. 000 = (waitcount ≥ threshold) -- See IWA = *00Ch, bits 9:0 for threshold details. 001 = waitcount ≥ threshold -- See IWA = *00Ch, bits 9:0 for threshold details. 010 = loop counter ≠ 0. 011 = loop counter = 0. 100 = RSCO Tab (RSCO - resampler NCO carry output). 101 = RSCO. 110 = sync (if enabled) or μP controlled bit. 111 = always. Start = load parameters and start filter computation, set to zero for no-ops, loop counter loads. IncrRS = increment resampler during this filter. Increments on start or at each FIR output depending on μPcontrol bit. DecrSel = selects between two decrement values for the wait counter. DecrEn = decrement wait count on starting this instruction. LdLp = load loop counter with the data in the I(20:9) bit field. The start bit should not be set when this bit is set. DecrLp = decrement loop counter on starting this instruction. EnU/C = enable U/C counter with this FIR. This multiplies the data by 1, j, -1, -j. The multiplication factor changes each time the filter runs. 14:9 FIR Type FIR Parameter Bit Fields 14:9 FIR type. 000000 NOP. 000001 Decimating FIR, Even Symmetric, Even # Taps. 000010 Decimating FIR, Even Symmetric, Odd # Taps. 000011 Decimating FIR, Odd Symmetric, Even # Taps. 000100 Decimating FIR, Odd Symmetric, Odd # Taps. 000101 Decimating FIR, Asymmetric. 001000 Resampling FIR, Asymmetric. 001001 Interpolating HBF. 100000 Decimating FIR, Complex (Asymmetric). NOTES: 1. Regular interpolation FIRs are successive runs of a FIR with no data address increment, but with coefficient start address increments. 2. Decimating HBFs are even symmetric, odd number of taps but with different data step sizes. 3. U/C FIR is a normal FIR with the U/C bit enabled. 4. Other codes may be added in the future. 17:15 Steps per FIR Specifies the number of steps pe r FIR instruction sequence (load with value minus 1) (set to 0 for all FIR types except complex which is set to 1). HSP50216

28:18 Destination Destination Field Bit Mapping 28 27 26 25 24 23 22 21 20 19 18 AGCLFGN AGCLF Path1 Path0 OS FB F4 F3 F2 F1 F0 AGCLFGNAGC loop gain select. Only applies to Path 1. Loop gain 0 or 1 if AGCLF bit is set. Set to 0 (1 is a test mode for future chips). AGCLF AGC loop filter enable. Only applies to Path 1. The AGC loop is updated with the magnitude of this sample (Path(1:0) = 01). Path(1:0) Back End Data Routing Path Selection. 00Route output back to filter compute engine input to another FIR in the filter chain. 01Route output through the FIFO and AGC forward path to the cartesian-to-polar coordinate converter conversion and output (I1, Q1, magnitude, phase, gain) and also to route to a dis- criminator (i.e., dφ/dt FIR). 10Route output directly to the output, bypassing the FIFO and AGC (I2, Q2). This path also routes to next channel FIR input. OS Enable output strobe. Setting this bit generat es a data ready signal when the data reaches the output section and starts the serial output sequence (paths 1, 2, 3). If OS is not set, there will be no output to the outside world from this channel, for that output calculation, but the data will be loaded into its output holding register (OS would not be set when routing the data to another back end when cascading channels). FB Feedback data path. When set, the magnitude and dp hi/dt from the cartesian-to-polar coor- dinate converter block are routed to the filter compute engine input (magnitude goes to the I input and dphi/dt goes to the Q input). Provided for discriminator filtering. F(4:0) Filter select. For data recirculated to the input of the FIR processor by path 0 or from the car- tesian to polar coordinate converter output, these bits tell which filter sequencer step gets it as an input. 31:29 Round Select 31:29 Round Select (Add rounding bit at specified location). 000 2 -24, use this code when downshifting is not used. 001 2 -23 010 2 -22 011 2 -21 100 2 -20 101 2 -19 110 2 -18 111 no rounding. Provided for use with the coefficient down-shift bits. 41:32 Data Memory Block Start Memory block base address, 0-1023, 0-383 are valid for the HSP50216. 44:42 Data Memory Block Size 44:42 Block Size. 0 8 1 16 2 32 36 4 4 128 5 256 6 512 7 1024 (modulo addressing is used). 52:45 Data Memory Block-to-Block Step 0-255, usually equal to the decimation factor for the FIR in this instruction. INSTRUCTION BIT FIELDS (Continued) BIT POSITIONS FUNCTION DESCRIPTION HSP50216

62:53 Coefficient Memory Block Start Memory base address of coefficients, 0-1023, 0-511 are valid on the HSP50216. 63 Reserved Set to 0. 66:64 Coefficient Memory Block Size 66:64 Memory Block Size 11 6 2 32 36 4 4 128 5 256 6 512 71 0 2 4 (Modulo addressing can be used, but is usually not needed. If not needed this bit field can always be set to 7). 75:67 Number of FIR Outputs Number of FIR outputs (range is 1 to 512, load w/ desired value minus 1). This is usually equal to the total decimation that follows the filter. 84:76 Read Address Pointer Step Read address pointer step (for next run). This is usually equal to the filter decimation times the number of outputs from the instruction. 93:85 Initial Address Offset Initial address offset (to ADDRB). This is the offset from the start address to other end of filter. For symmetric filters, usually equal to -1 x (number of taps -1). 95:94 Reserved Set to 0 104:96 Memory Reads Per FIR Output This is based on the number of taps (load with value below minus 1). Type Value Symmetric even number of taps(taps/2) or floor((taps+1)/2). Symmetric odd number of taps (taps+1)/2 or floor((taps+1)/2). Decimating HBF (taps+5)/4. Asymmetric taps. Complex taps. Resampling taps/phase (six taps per phas e for the ROM’d coefficients provided). Interpolating HBF (taps+5)/4-1. 106:105 Clocks Per Memory Read Set to 0 for all but complex FIR, which is set to 1. 115:107 Data Memory Step Size 1 (ADDRA) Step size for all but the last tap computation of the FIR. Set to -2 for HBF, -1 otherwise. 117:116 Data Memory Step Size 2 (ADDRA) Step size for last tap computation. Set to -1. 117:116 Step size 0 0 1 -1 2 -2 3 step size value. 119:118 Data Memory Address Offset Step (ADDRB) Step size for opposite end of symmetric filter. Set to +2 for Decimating HBF, to +1 for others (the B data is not used for asymmetric, resampling, and complex filters). INSTRUCTION BIT FIELDS (Continued) BIT POSITIONS FUNCTION DESCRIPTION HSP50216

Basic Instruction Set Examples 1. Wait for number of input samples > threshold 127:9 = 0 8:0 = 001 0000,0000,0000,0001h 2. Jump unconditional 127:9 = 0 8:0 = 1JJJJJ111b example: jump to step 0= 0000,0000,0000,0107h 3. Jump RSCO (jump on resampler NCO carry output) 127:9 = 0 8:0 = 1JJJJJ101b example: jump RSCO, step 0= 0000,0000,0000,0105h 4. Jump RSCO (jump on no resampler NCO carry output) 127:9 = 0 8:0 = 1JJJJJ100b example: jump RSCO , step 0 = 0000,0000,0000,0104h 5. NOP single clock 127:9 = 0 8:0 = 010000000b NOP1 = 0000,0000,0000,0080h 6. Load Loop Counter 127:21 = 0 20:9 = Loop counter preload (tested against 0) 8:0 = 010000100b example: LdLpCntr 14 = 0000,0000,0000,1C84h 122:120 Coefficient Memory Step Size (ADDRC) Usually set to 1. 122:120 Step size 1 1 2 2 4 8 5 16 6 32 76 4 125:123 Coefficient Memory Block-to-Block Step (ADDRC) Usually set to 0. 125:123 Step size 0 0 1 1 2 2 3 4 4 8 5 16 6 32 7 64 127:126 Reserved Set to 0 INSTRUCTION BIT FIELDS (Continued) BIT POSITIONS FUNCTION DESCRIPTION HSP50216

This is the basic program for a single FIR. This program applies to decimation filters (including DECx1) that are symmetric or asymmetric (but not complex). The FIR output is routed through path A with the AGC enabled. Wait Preload Register This register (IWA register *00Ch) holds the wait counter threshold and two wait counter decrement values. Each is 10 bits. The wait counter counts filter input samples until the count is greater than or equal to the threshold. The wait counter then asserts a flag to the filter compute engine. The wait counter threshold is typically set to the total number of input samples needed to generate a filter output. A “WAIT” instruction in the filter compute engine waits for the wait counter flag signal before proceeding. The filter compute engine would then compute all the filters needed to produce an output and then would jump back to the “WAIT” instruction. The wait counter is implemented with an accumulator. This allows the count to go beyond the threshold without losing the sample count. Two bits in the FIR instruction decrement the wait counter (subtract a value) and select the decrement value. The decrement value is typically the number of samples needed for an output (total decimation), though it can be a different value to ignore inputs and shift the timing. (The read pointer increment must be adjusted as well.) The filter compute engine sequencer does not count each input sample or track whether each filter is ready to run. Instead, the wait counter is used to determine whether there are enough input samples to compute all the filters in the chain and get an output sample from the entire filter chain. This adds some additional delay since intermediate results are not precalculated, but it simplifies the filter control. The number of samples needed is equal to the total decimation of the filter chain. For example, with two decimate-by-2 halfband filters and a decimate-by-2 shaping FIR, the total decimation would be 8 so 8 samples are needed to compute an output. HBF1 would compute four times to generate four inputs to HBF2. HBF2 would compute twice to generate the two samples that the shaping FIR needs to compute an output. 0 - WAIT FOR ENOUGH SAMPLES 0000 0000 0000 0000 0000 0000 0000 0000 127:96 00000000h 0000 0000 0000 0000 0000 0000 0000 0000 95:64 00000000h 0000 0000 0000 0000 0000 0000 0000 0000 64:32 00000000h 0000 0000 0000 0000 0000 0000 0000 0001 31:0 00000001h 1 - FIR 0000 0001 0101 1111 1111 100R RRRR RRRR 127:96 015FF---h 00TT TTTT TTTD DDDD DDDD 0000 0000 0111 95:64 -----007h 0000 1000 0000 0000 0000 1010 0000 0000 63:32 08000A00h 0000 1011 0000 0000 0FFF FFF0 1100 1000 31:0 0B00--C8h 2 - JUMP TO STEP 0 0000 0000 0000 0000 0000 0000 0000 0000 127:96 00000000h 0000 0000 0000 0000 0000 0000 0000 0000 95:64 00000000h 0000 0000 0000 0000 0000 0000 0000 0000 64:32 00000000h 0000 0000 0000 0000 0000 0001 0000 0111 31:0 00000107h Four bit fields must be filled in: F - filter type (this example applies to types 1-5) D - decimation (also loaded into wait threshold) T - number of taps minus 1 R - clocks/calculation (=floor((taps +1)/2) for symmetric, = taps for asymmetric) The rest of the instruction RAM would typically be filled with NOP instructions: 0000 0000 0000 0000 0000 0000 0000 0000 127:96 00000000h 0000 0000 0000 0000 0000 0000 0000 0000 95:64 00000000h 0000 0000 0000 0000 0000 0000 0000 0000 64:32 00000000h 0000 0000 0000 0000 0000 0000 1000 0000 31:0 00000080h HSP50216

spurious caused by the AGC resolution. I and Q signal levels into the Cartesian to polar converter. to 1.64676 times the desired magnitude of the I1/Q1 output. Detector output has the identical range. † Controlled via microprocessor interface. FIGURE 1. AGC FUNCTIONAL BLOCK DIAGRAM

4 EXPONENT)

The loop gain register values adjust the response / settling time of the AGC loop. The loop gain is set in the AGC Error Scaling circuitry, using four values in two sets of programmable mantissa and exponent pairs (see IWA register *010h). Each set has both an attack and a decay gain. This allows asymmetric adjustment for applications such as VOX systems where the signal turns on and off. In these applications, the gains would be set for fast attack and slow decay so that the part decreases the gain quickly when the signal turns on, but increases the gain slowly when the signal turns off (in anticipation of it turning back on shortly). For fixed gains, either set the upper and lower AGC limits to the same value, or set the limits to minimum and maximum gains and set the AGC attack and decay loop gains to zero. The mantissa, M, is a 4-bit value which weights the loop filter input from 0.0 to 15 / 2 4 = 0.9375. The exponent, E, defines a shift factor that provides additional weighting from 2 0 to 2-15. Together the mantissa and exponent define the loop gain as given by, AGC Loop Gain = MLG 2-4 2-(15-ELG) where M LG is a 4-bit binary mantissa value ranging from 0 to 15, and E LG is a 4-bit binary exponent value ranging from 0 to 15. The composite (shifter and multiplier) AGC scaling Gain range is from 0.0000 to 2.329(0.9375)2 0 = 0.0000 to 2.18344. The scaled gain error can range (depending on threshold) from 0 to 2.18344, which maps to a “gain change per sample” range of 0 to 3.275dB / sample. The AGC attack and decay gain mantissa and exponent values for loop gains 0 and 1 are programmed into IWA register *010h. The PDC provides for the storing of two values of AGC attack and decay scaling gains to allow for quick adjustment of the loop gain by simply setting IWA register *013h bits 9 and 10 accordingly. Possible applications include acquisition / tracking, no burst present / burst present, strong signal / weak signal, track / hold, or fast / slow AGC values. The AGC loop filter consists of an accumulator with a built in limiting function. The maximum and minimum AGC gain limits are provided to keep the gain within a specified range and are programmed by 16-bit upper and lower limits using the following the equation: AGC Gain Limit = (1 + m AGC 2-12) 2e (AGC Gain Limit)dB = (6.02)(eeee) + 20 log(1.0+0.mmmm mmmm mmmm) where m is a 12-bit mantissa value between 0 and 4095, and e is the 4-bit exponent ranging from 0 to 15. IWA register *011h Bits 31:16 are used for programming the upper limit, while bits 15:0 are used to program the lower limit. The format for these limit values are: (31:16) or (15:0): E E E E M M M M M M M M M M M M for a gain of 0 1. M M M M M M M M M M M M * 2 E E E E and the possible range of AGC limits from the previous equations is 0 to 96.328dB. The bit weightings for the AGC Loop Feedback elements are detailed in Table 51. Using AGC loop gain, the AGC range, and expected error detector output, the gain adjustments per output sample for the loop filter section of the digital AGC can be given by AGC Slew Rate = (1.5 dB) (THRESHOLD - (MAG * 1.64676)) x (M The loop gain determines the growth rate of the sum in the loop accumulator which, in turn, determines how quickly the AGC gain scales the output to the threshold value. Since the log of the gain response is roughly linear, the loop response can be approximated by multiplying the maximum AGC gain error by the loop gain. The expected range for the AGC rate is ~ 0.000106 to 3.275dB / output sample time for a threshold of 1/2 scale. For a full scale error, the minimum non-zero AGC slew rate would be approximately 0.0002dB / output or 20dB / sec at 100ksps. The maximum gain would be 6dB / output. This much gain, however, would probably result in significant AM on the output. The maximum AGC Response is given by: AGC Response Max = (Input)(Cart/Polar Gain)(Error Det. Gain)(AGC Loop Gain)(AGC Output Weighting) Since the AGC error is scaled to adjust the gain, the loop settles asymptotically to its final value. The loop settles to the mean of the signal. For example, if MLG = 0101 and ELG = 1100, the AGC Loop Gain = 0.3125 * 2 -7. The loop gain mantissas and exponents are set in IWA register *010h, with IWA register *013h selecting loop gain 0 or 1 and the settling mode. In the HSP50216, a SYNCI signal will clear the AGC loop filter accumulator if GWA register F802h bit 27 is set. The settling mode of the AGC forces either the mean or the median of the signal magnitude error to zero, as selected by IWA register *013h bit 8. For mean mode, the gain error is scaled and used to adjust the gain up or down. This proportional scaling mode causes the AGC to settle to the final gain value asymptotically. This AGC settling mode is preferred in many applications because the loop gain adjustments get smaller and smaller as the loop settles, reducing any AM distortion caused by the AGC. With this AGC settling mode, the proportional gain error causes the loop to settle more slowly if the threshold is small. This is because the maximum value of the threshold minus the magnitude is smaller. Also, the settling can be asymmetric, where the loop may settle faster for “over range” signals than for “under range” signals (or vice versa). In some applications, such as burst signals or TDMA signals, a very fast settling time and/or a more predictable settling time is desired. The AGC may be turned off or slowed down after an initial AGC settling period. HSP50216

settling time independent of the signal level. adjustments during tracking. programmable AGC loop gain register IWA *010h. may be disabled by setting both limits to the same value. selected by setting bit 8 to 1. and phase of the I/Q vector. The I and Q inputs are 24 bits. unsigned (0.0 to approximately 1.0), as shown in Figure 2. stage, either the output formatter or frequency discriminator. always be worse than the Cartesian to Polar conversion. TABLE 1. MAG/PHASE BIT WEIGHTING FIGURE 2. PHASE BIT MAPPING OF COORDINATE

the AGC) plus the compute delay of the resampler block. TABLE 2. MAG/PHASE ACCURACY vs CLOCK CYCLES

Serial Data Output Formatter Section Serial Data Output Control Register The serial data output control register contains sync position and polarity (SYNCA, B, C or D), channel multiplexing, and scaling controls for the SD1x and SD2x (x = A, B, C or D) serial outputs (see Microprocessor Interface section, Table 23, “SERIAL DATA OUTPUT CONTROL REGISTER (IWA = *014h),” on page 37). Channel Routing Mask The multiplexing mask bits for each channel (see Microprocessor Interface section, Table 23, IWA *014h bits 19:16 for SD1x or bits 15:12 for SD2x) can be used to enable that channel’s output to any of the four serial outputs. These bits control the AND gates that mask off the channels, so a zero disables the channel’s connection to that output. To configure more than one channel's output onto a serial data output, the SD1 serial outputs and syncs from each channel (0,1, 2 and 3) are brought to each of the SD1 serial output sections and the SD2 serial outputs are brought to each of the SD2 serial output sections (the syncs are only associated with the SD1 serial outputs). There, the four outputs are AND-ed with the multiplexing mask programmed in the serial data output control registers of channels 0 through 3 and OR-ed together. By gating off the channels that are not wanted and delaying the data from each desired channel appropriately, the channels can be multiplexed into a common serial output stream. It should be noted that in order to multiplex multiple channels onto a single serial data stream the channels to be multiplexed must be synchronous. M U X M U X O R FIXED TO FLOAT DELAY SYNC GEN PARALLEL TO SERIAL PARALLEL TO SERIAL SEQUENCER SD2x SEQUENCER ROUND ROUND M U XM U X R E G TO μP INTERFACE SYNCx SD1x OUTPUT SECTION ZERO MAG PHASE GAIN STROBE ZERO NOTE: Each serial output has 7 time slots. Each slot can contain I1, Q1, I2, Q2, Mag, phase or dφ/dt. AGC gain, or zeros. Each slot can be 4, 6, 8, 10, 12, 16, 20, 24, or 32 (24 + 8 zeros) bits or disabled. Output 1 can also be 32-bit floating point. Slots can be disabled. A disabled slot will be one clock wide if there are other active slots following. A sync can be asserted with any or all slots following. A sync can be asserted with any or all slots in output 1. The serial output can be delayed from 0 to 4095 serial clock periods from the input strobe. The serial outputs are always MSB first. The sync position applies to all time slots and can be one clock prior to the first data bit, aligned with the first data bit, or one clock after the last data bit. O R O R HSP50216

Serial Data Output Time Slot Content/Format Registers These four registers are used to program the content and format of the serial data output sequence time slots (see Microprocessor Interface section: Table 24, “SERIAL DATA OUTPUT 1 CONTENT/FORMAT REGISTER 1 (IWA = *015h),” on page 39 through Table 27, “SERIAL DATA OUTPUT 2 CONTENT/FORMAT REGISTER 2 (IWA = *018h),” on page 40). There are seven data time slots that make up a serial data output stream. The number of data bits and data format of each slot is programmable as well as whether there will be a sync generated with the time slot (the syncs are only associated with the SD1 serial outputs). Any of seven types of data or zeros can be chosen for each time slot. Eight bits are used to specify the content and format of each slot. As an example, suppose we wanted to output 32-bit I and Q values from channels 0 and 1 into the SD1A serial data output stream, we would program the following settings in the channel’s serial data output control and content/format registers: Channel 0: delay = 0 (IWA = 0014h, bits 11:0 = 0); first data time slot = I, 32-bit, sync pulse generated (IWA = 0015h, bits 7:0 = 0xC9); second data time slot = Q, 32-bit, no sync pulse (IWA = 0015h, bits 15:8 = 0x4A); third through seventh data time slot = zero and no sync, (IWA = 0015h, bits 31:16 = 0 and IWA = 0016h, bits 31:0 = 0); enable the SD1A serial output for this channel in the serial routing mask (IWA = 0014h, bit 16 = 1). Channel 1: delay = 64 (IWA = 1014h, bits 11:0 = 0x40); first data time slot = I, 32-bit, sync pulse generated (IWA = 1015h, bits 7:0 = 0xC9); second data time slot = Q, 32-bit, no sync pulse (IWA = 1015h, bits 15:8 = 0x4A); third through seventh data time slot = zero and no sync, (IWA = 1015h, bits 31:16 = 0 and IWA = 1016h, bits 31:0 = 0); enable the SD1A serial output for this channel in the serial routing mask (IWA = 1014h, bit 16 = 1). The resulting order is CH0 I first, then CH0 Q, CH1 I, and CH1 Q with sync pulses generated in the I data slots. The position of the sync pulses relative to the data slot may be programmed with IWA register *014h bits 25:24. Setting delay = 64 offsets channel 1’s 32 bit I and Q data by 64 clocks so that it immediately follows the 64 bits of data from channel 0. In this way channel 1’s first and second time slots follow channel 0’s second time slot. Instead of using the delay to offset channel 1’s data, channel 0 could have been configured to output 32 bits of I in the fist slot, 32 bits of Q in the second slot, 32 bits of zeros in the third slot and 32 bits of zeros in the fourth slot. Channel 1 could then be configured to output 32 bits of zeros in the first and second slots, 32 bits of I in the third slot and 32 bits of Q in the fourth slot. As the channel outputs are OR’d together, the zero slots do not interfere with data slots. The HSP50216 Microprocessor (μP) interface consists of a 16-bit bidirectional data bus, P(15:0), three address pins, ADD(2:0), a write strobe (WR ), a read strobe (RD) and a chip enable (CE). Indirect addressing is used for control and configuration of the HSP50216. The control and configuration data to be loaded is first written to a 32-bit holding register at direct (external) addresses ADD(2:0) = 0 and 1, 16 bits at a time. The data is then transferred to the target register, synchronous to the clock, by writing the indirect (internal) address of the target register to direct (external) address 2, ADD(2:0) = 2. The interface generates a synchronous one clock cycle wide strobe to transfer the data contained in the holding register to the target register. The synchronization and write process requires 4 clock periods. New data should not be written to the holding register until after the synchronization period is over. HSP50216

Data reads can be direct, indirect or FIFO-like depending on the data that is being read. The status register is read directly at direct (external) address 3, ADD(2:0) = 3. Readback of internal registers and memories is indirect. The 16-bit indirect (internal) address of the desired read source is first written to direct (external) address 3, ADD(2:0) = 3, to select the data. The data can then be read at direct (external) addresses ADD(2:0) = 0 and 1 (bits 15:0 at address 0 and 31:16 at address 1). The data types available via the indirect read are listed in the Tables of Indirect Read Address (IRA) Registers. (Note that the μPHold bit contained in the target register at Indirect Write Address (IWA) = *00Ah must be set to suspend the filter compute engine before the coefficient RAM and instruction bit fields can be written to or read from.) The HSP50216 output data from the four channels is available through the microprocessor interface as well as from the serial data outputs. A FIFO-like interface is used to read the output data through the microprocessor interface. When new output data is available, it is loaded into a FIFO in a user programmed order (for details on the programming order, see Tables of Global Write Address (GWA) Registers (GWA) = F820h - F83Fh). It can then be read, 16 bits at a time, at direct address 2, ADD(2:0) = 2. At the end of each read, the FIFO counter is advanced to the next location. This allows a DMA controller to read all of the data with successive reads to a single direct address. No writes or other interaction is required. The FIFO counter is reset and reloaded by each interrupt signal, see GWA F802h. New data in the FIFO is also indicated in the status register located at direct address ADD(2:0) = 3 if a polled mode is preferred. The eight data types available, for each of the four channels, via this interface are: I(23:8), I(7:0)+8 Zeroes, Q(23:8), Q(7:0)+8 Zeroes, Mag(23:8), Mag(7:0)+8 Zeroes, Phase (15:0), and AGC (15:0). The upper bits of I, i.e., I(23:8), and Q, i.e., Q(23:8), are not rounded to 16 bits. This interface can read the data from all the channels that are synchronized. However, because a common FIFO is used and the FIFO is reset and reloaded by each interrupt, it cannot be used for asynchronous channels. MUX 3 2 1 0 R E R E F F F F R E AND M U X E S D E C O D E RD P(15:0) WR A(2:0) CLK = 0 = 1 = 2 or 3 = 2 en en en 15:0 31:0 31:16 15:0 31:16 31:0 INTERNAL READ DATA BUS INTERNAL READ SIGNAL SYNC’d WR TO TARGET REGISTERS INTERNAL ADDRESS BUS INTERNAL WRITE DATA BUS SPECIAL LOW METASTABILITY CELL RST CE (GATING NOT SHOWN) L A T C H FROM OUTPUT FIFO STATUS G A T I N G HSP50216

The direct address map for the microprocessor interface is shown in the TABLE OF MICROPROCESSOR DIRECT READ/WRITE ADDRESSES and the procedures for reading and writing to this interface are provided below. The bit field details for each indirect read and write address are provided in the Table of Indirect Read Address (IRA) Registers, Tables of Indirect Write Address (IWA) Registers (Tables 3 - 34) and Tables of Global Write Address (GWA) Registers (GWA) Registers (Tables 35 - 45). μP Read/Write Procedures To Write to the Internal Registers: 1. Load the indirect write holding registers at direct address ADD(2:0) = 0 and 1 with the data for the internal register (16 or 32 bits depending on the internal register being addressed). 2. Write the Indirect Write Address of the internal register being addressed to direct address ADD(2:0) = 2 (Note: A write strobe to transfer the contents of the Indirect Write Holding Register into the Target Register specified by the Indirect Address will be generated internally). 3. Wait 4 clock cycles before performing the next write to the indirect write holding registers. To Write to the Internal Instruction/Coefficient RAMs: 1. Put the filter compute engine of the desired channel into the hold mode by setting bit 31 of the Filter Compute Engine / Resampler Control register located at IWA = *00Ah (Note: The * is equal to 0, 1, 2 or 3 depending on the channel being addressed). By setting bit 31 all FIR processing for the channel addressed will be stopped. 2. Load the indirect write holding registers at direct address ADD(2:0) = 0 and 1 with the data for the internal RAM location. 3. Write the Indirect Write Address of the internal RAM location being addressed to direct address ADD(2:0) = 2 (Note: A write strobe to transfer the contents of the Indirect Write Holding Register into the RAM location specified by the Indirect Address will be generated internally). 4. Wait 4 clock cycles before performing the next write to the indirect write holding registers. 5. After all data has been loaded, set the μPHold bit back low. To Read Internal Registers: 1. Write the Indirect Read Address of the internal register being addressed to direct address ADD(2:0) = 3. 2. Perform a read of the Indirect Read Holding Registers at direct address ADD(2:0) = 0 and 1. To Read Data Outputs: 1. Set up the μP FIFO Read Order Control Register (located at Global Write Address (GWA) = F820h - F83Fh). 2. Wait for interrupt or check flag. 3. Data can then be read, 16 bits at a time, at direct address 2, ADD(2:0) = 2. 4. Repeat step 3 for desired number of words. 5. Go to step 2. To Read Instruction/Coefficient Values: 1. Put the filter compute engine of the desired channel into the hold mode by setting bit 31 of the Filter Compute Engine / Resampler Control register located at IWA = *00Ah (Note: The * is equal to 0, 1, 2 or 3 depending on the channel being addressed). 2. Write the Indirect Read Address (IRA) of the internal RAM/ROM location being addressed to direct address ADD(2:0) = 3. 3. Wait 4 clock cycles. 4. Read the data at direct address ADD(2:0) = 0 and 1. 5. After all the data has been read, set the μPHold bit back low. Recommended HSP50216 configuration procedure following a hardware reset (i.e. RESETb is pulsed low): 1. Load Global Write Address registers GWA F800 - GWA F808 and GWA F820 - GWA F83F. 2. For each signal processing channel (0-3): a. Set mPHold bit located at Indirect Write Address register IWA *00A - 31. b. Load Filter Compute Engine Instruction RAMS. c. Load Filter Compute Engine Coefficient RAMS. d. Load IWA registers *000 - *019. (Clear the mPHold bit in register IWA *00A - 31). e. Wait 32 clocks (CLK) for the reset to complete in the Filter Compute Engine. 3. Generate a SYNCI to enable the input data or to synchronize the processing to external events or generate a SYNCO by writing to GWA F809. NOTE: For the latter method, the SYNCO pin must be connected to the SYNCI pin. Recommended HSP50216 Channel Reconfiguration Procedure: 1. Disable the serial output for the desired channel in register GWA F801 - 3, 2, 1 or 0. 2. Disable the interrupts from the channel in register GWA F802 - 31, 23, 15, or 7. 3. Set the mPHold bit in register IWA *00A - 31 to give the processor access to the Filter Compute Engine Instruction RAMS and Coefficient RAMS. 4. Load the new filter configuration. 5. Load any other channel registers. HSP50216

1. Clear the mPHold bit in register IWA *00A - 31. 7. Do a software channel reset by writing to IWA *019. 8. Enable the serial outputs (GWA F801) and interrupts (GWA F802). 9. Generate a SYNCI to enable the input data or to synchronize the processing to external events or generate a SYNCO by writing to GWA F809. NOTE: For the latter method, the SYNCO pin must be connected to the SYNCI pin. TABLE OF MICROPROCESSOR DIRECT READ/WRITE ADDRESSES ADD(2:0) PINS REGISTER DESCRIPTION 0 WR Indirect Write Holding Register, Bits 15:0. 1 WR Indirect Write Holding Register, Bits 31:16. 2 WR Indirect Write Address Register for Internal Target Regi ster (Generates a write strobe to transfer contents of the Write Holding Register into the Target Register specified by the Indirect Address, see also Table of Indirect Read Address (IRA) Registers). 3 WR Indirect Read Address Register (Used to select the Read source of data - uses the same register as Direct Address 2 but generates a read strobe (for RAMs and AGC) as needed instead of a write strobe). 0 RD Indirect Read, Bits 15:0. 1 RD Indirect Read, Bits 31:0f. 2 RD Read Register (FIFO) - Reads FIFO data from output section (This location reads output data in the order loaded in Global Control Indirect Address Registers F820-F83F. The FIFO is automatically incremented to the next data location at the end of each read).

3 RD Status Register

P(15:0) BIT DESCRIPTION 15:12 Unused. 11:6 Read non-bus input pins (ENIx , RESET, SYNCI). 11 RESET (Note: This bit is inverted with respect to the RESET input pin). 10 ENIA. 9E N I B. 8E N I C. 7 ENID . 6 SYNCI. 5:2 Mask revision number. 1 Level detector integration done. Active high. 0 New FIFO output data available (used for polling mode vs interrupt mode) Active low. HSP50216

special case which writes the data to the same location in each of the four channels simultaneously. **TABLE 3. CHANNEL INPUT SELECT/FORMAT REGISTER (IWA = *000h)**

000 A(15:0)

001 B(15:0)

010 C(15:0)

011 D(15:0)

Global Write Address register for the μP Test input register is F807h. 1 Bit 11 of this register is used as the input enable. 0 A one clock wide pulse generated on each write to lGWA F808h is used as the input enable. Select 0 to write test data into the part. Select 1 to input a constant or to disable the input for minimum power dissipation when an NCO/mixer/CIC section is unused.

0 Enabled

10 Parallel Data Input Format:

9 Fixed/Floating point:

00 11/3: bits 15:5 are mantissa, 2:0 are exponent. 01 12/3: bits 15:4 are mantissa, 2:0 are exponent. 10 13/3: bits 15:3 are mantissa, 2:0 are exponent. 11 14/2: bits 15:2 are mantissa, 1:0 are exponent. See the exponent tables contained in the Input Select/Format Block section. NCO/Mixer/CIC stage at the next ENIx.

000 Zero delay

111 7 clock periods of delay. All values from 0 through 7 are valid.

3 Interpolated/Gated Mode Select:

0 Gated. The carrier NCO and CIC are updated once per clock when ENIx is asserted. input is zeroed when ENIx is high.

0 Enable PN. When set, A PN code, weighted by the gain in location *001, is added to the input samples at the output of the mixe r. **TABLE 3. CHANNEL INPUT SELECT/FORMAT REGI STER (IWA = *000h) (Continued)** **TABLE 4. PN GAIN REGISTER (IWA = *001h)** 31:16 Reserved, set to all 0’s. **TABLE 5. CIC DECIMATION FACTOR REGISTER (IWA = *002h)** 15:0 Load with the desired CIC decimation factor minus 1. **TABLE 6. CIC DESTINATION FIR AND OUTPUT ENABLE/DISABLE REGISTER (IWA = *003h)** 5:1 CIC output destination (FIR # in FIR processor). Usually set to 00001. 0 CIC output enable. Active high. When low, the data writes from the CIC to the filter compute engine are inhibited. **TABLE 7. CARRIER NCO/CIC CONTROL REGISTER (IWA = *004h)** 31:19 Reserved, set to zero. 18:14 CIC barrel shift control. Shift Factor = 45 - Ceiling(log2(RN)). enabled starting with stage 1 for maximum decimation range. 8:6 Carrier phase shift. Phase shifts of N*( π/4), N = 0 to 7. 5 Clear feedback (test signal or for mixer bypass). 4 NCO clear feedback on load.

**TABLE 7. CARRIER NCO/CIC CONTROL REGISTER (IWA = *004h) (Continued)** **TABLE 8. CARRIER NCO CENTER FREQUENCY REGISTER (IWA = *005h)** frequency is: CCF*fCLK/(232). mode and the clock rate for interpolated mode. **TABLE 9. CARRIER NCO CENTER FREQUENCY UPDATE STROBE REGISTER (IWA = *006h)** register can also be done using the SYNCI pin to synchronize the transfer in multiple parts or to synchronize to an external event. 00 and 01 after writing to this address and before writing a new address to either A(1:0) = 10 or 11. **TABLE 10. TIMING NCO FREQUENCY CONTROL REGISTER, MSW (IWA = *007h)** 31:0 These are the upper 32 bits of the 56-bit ti ming (resampler) NCO center frequency control. **TABLE 11. TIMING NCO FREQUENCY CONTROL REGISTER, LSW (IWA = *008h)** 31:8 These are the lower 24 bits of the 56-bit timing (resampler) NCO center frequency control. **TABLE 12. TIMING NCO CENTER FREQUENCY LOAD STROBE REGISTER (IWA = *009h)** **TABLE 13. FILTER COMPUTE ENGINE/RESAMPLER CONTROL REGISTER (IWA = *00Ah)** instruction at location 31 is fetched). 30 μPShiftZeroB. This bit, when set to zero, disables the coefficient shift bits (bits 9:8 of the master register when coefficient loading). controlled limiting (ANDed with normal signal).

22 Timing (resampler) NCO ENsync. If this bit is se t, the center frequency is updated on a SYNCI. Set to 1.

19 Beginning/End

1 Once at the beginning of the FIR instruction. 0 At the last tap of each of the instruction’s FIR computations (once per output). 18 RSModeSelect. This bit selects whether the resa mpler is a phase shifter or a frequency shifter. NCO phase accumulator -- effect of the resampler is a constant phase shift. 1 Frequency shift. effect of the resampler is a change in the sample rate. use the resampler for phase instead of frequency shifting. zeroed. To disable the shifting, see IWA register *000h. **TABLE 13. FILTER COMPUTE ENGINE/RESAMPLER CO NTROL REGISTER (IWA = *00Ah) (Continued)** **TABLE 14. FILTER START OFFSET REGISTER (IWA = *00Bh)** 13:9 RAM Instruction number to which the offset is appl ied. 0-31. Aliasing applies. Used for polyphase filters. 100 taps where a single channel would only be capable of around 24 taps at a 4MHz output. EXCEPT IN VERY RARE CIRCUMSTANCES, THIS VALUE SHOULD BE A NEGATIVE NUMBER.

**TABLE 15. WAIT THRESHOLD/DECREMENT VALUE REGISTER (IWA = *00Ch)** or synchronous startup. Active high. 29:20 Decrement value 1. Positive number. 19:10 Decrement value 0. Positive number. Usually set equal to the Threshold (bits 9:0). 9:0 Threshold. Number of samples needed to run a filter set and produce an output. **TABLE 16. RESET WRITE POINTER OF FSET REGISTER (IWA = *00Dh)** filter and two for a multi-filter chain. **TABLE 17. AGC GAIN LOAD REGISTER (IWA = *00Eh)** AGC will hold this value. If not, the AGC will be set to this gain (or to a limit) and then start to settle. format is 4 exponent bits (15:12), and 12 mantissa bits, (11:0). **TABLE 18. AGC GAIN READ STROBE REGISTER (IWA = *00Fh)** this location after waiting the 4 clocks required for read synchronization. **TABLE 19. AGC LOOP ATTACK/DECAY GAIN VALUES REGISTER (IWA = *010h)** 31:24 Loop gain 0, decay gain value (signal decay, incr ease gain) 31:28 = EEEE (exponent), 27:24 = MMMM (mantissa). 23:16 Loop gain 1, decay gain value 23:20 = EEEE (exponent), 19:16 = MMMM (mantissa). 15:8 Loop gain 0, attack gain value (signal arrival, decr ease gain) 15:12 = EEEE (exponent), 11:8 = MMMM (mantissa). 7:0 Loop gain 1, attack gain value 7:4 = EEEE (exponent), 3:0 = MMMM (mantissa). **TABLE 20. AGC GAIN LIMITS REGISTER (IWA = *011h)** 31:16 Upper gain limit. See AGC section. 15:0 Lower gain limit. See AGC section. **TABLE 21. AGC THRESHOLD REGISTER (IWA = *012h)** 16 Enables dphi/dt update for non-fed back data. Discriminator output is not filtered. 15:0 AGC threshold. Equals 1.64676 times th e desired magnitude of the I1/Q1 output.

**TABLE 22. AGC/DISCRIMINATOR CONTROL REGISTER (IWA = *013h)** which loop gain to use with that filter output’s gain error. Setting bit 10 overrides this bit and forces a loop gain 1.

00 Loop Gain 0 ( μP controlled)

10 Loop gain 1 ( μP controlled)

01 Loop Gain controlled by filter compute engine

11 Loop 1 ( μP override of filter compute engine)

but will have more AM after settling.

1 Mean mode

0 Median mode

7 Set this bit to 1 to get a dphi/dt output without having to feedback through the filter compute engine .

5 PhaseOutputSel

0 Phase

180, 90, or 45 degrees to remove PSK modulation. The resulting phase is 18 bits. 2:0 DiscDelay(2:0). Sets the delay, in sample times, for the d φ/dt calculation. **TABLE 23. SERIAL DATA OUTPUT CONTROL REGISTER (IWA = *014h)**

28 Sync polarity

1 Active low (low for one serial clock per word with a sync). 27:26 Reserved, set to zero. 00 Sync is asserted during the serial cl ock period prior to the first data bit of the serial word (early sync). 01 Sync is asserted during the cloc k period following the last data bit of the word (late sync). 1X Sync is asserted during the serial clock period of t he first data bit of the serial word (coincident sync). 23:22 Reserved, set to zero.

The upper limits on codes 00 and 01 are the same, but 01 has no leading zero. 19:16 Serial data output SD1 rout ing mask. 0 disables. 1 enables. 16 Enables the serial output for this channel to pin SD1A. 17 Enables the serial output for this channel to pin SD1B. 18 Enables the serial output for this channel to pin SD1C. 19 Enables the serial output for this channel to pin SD1D. 15:12 Serial data output SD2 rout ing mask. 0 disables. 1 enables. 12 Enables the serial output for this channel to pin SD2A. 13 Enables the serial output for this channel to pin SD2B. 14 Enables the serial output for this channel to pin SD2C. 15 Enables the serial output for this channel to pin SD2D. stream for multiplexing channels. Load with the desired delay (0 = zero, 1 = one, 2 = two, etc.). **TABLE 23. SERIAL DATA OUTPUT CONTROL REGISTER (IWA = *014h) (Continued)**

**TABLE 24. SERIAL DATA OUTPUT 1 CONTENT/FORMAT REGISTER 1 (IWA = *015h)** 31:24 Fourth serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 for functional description of bits 31:24. 23:16 Third serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 for functional description of bits 23:16. 15:8 Second serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 for functional description of bits 15:8. 7:0 First serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. associated with Output 1). Set to zero for Output 2, SD2x. 0000 0-bit, fixed point (actually 1-bit position is used). 1001 32-bit fixed (8 LSBs are zeroed). 1010 32-bit, floating point, IEEE format. All other codes are invalid. Note: Floating point format is only available on the Serial Data Output 1. Code 1010 is invalid on Serial Data Output 2.

000 Zeros

001 I1 (data routed from FIFO and AGC path). 010 Q1 (data routed from FIFO and AGC path). 100 Phase (or d φ/dt) of I1/Q1. 101 I2 (data routed directly fr om the filter processor). 110 Q2 (data routed directly from the filter processor). The filter processor must be programmed appropriately to route the data to I1/Q1 or I2/Q2. programmed to 16-bit, disabled, 16-bit, there would a one clock idle period between the two 16-bit data words. the new data will begin immediately. If a late sync was programmed, it will not occur. **TABLE 25. SERIAL DATA OUTPUT 1 CONTENT/FORMAT REGISTER 2 (IWA = *016h)** 23:16 Seventh serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 23:16. 15:8 Sixth serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 15:8. 7:0 Fifth serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 7:0.

**TABLE 26. SERIAL DATA OUTPUT 2 CONTENT/FORMAT REGISTER 1 (IWA = *017h)** 31:24 Fourth serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 23:16. 23:16 Third serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 23:16. 15:8 Second serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 15:8. 7:0 First serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 7:0. **TABLE 27. SERIAL DATA OUTPUT 2 CONTENT/FORMAT REGISTER 2 (IWA = *018h)** 23:16 Seventh serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 23:16. 15:8 Sixth serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 15:8. 7:0 Fifth serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 7:0. **TABLE 28. SOFTWARE RESET REGISTER (IWA = *019h)** N/A Writing to this location resets the followi ng activities of the functional block indicated. Input Format/Select, NCO, Mixer and CIC. processing in the data path, but does not clear the data path registers). Resets the Read/Write pointers, fetch instruction 31 and start the filter program execution. Resets the compute blocks in both the forward and loop filter blocks (any calculations in progress are lost). Resets the compute blocks (any calculations in progress are lost). Resets counter (clears the FIFO, all data is lost). Clears the slave (active) frequency registers and clears the phase accumulator. Resets the serial output section (clears all registers, counters, and flags but does not clear the configuration registers). Engine, AGC, and Cartesian-to-Polar Coordinate Converter). **TABLE 29. CHANNEL TIMING ADVANCE STROBE REGISTER (IWA = *01Ah)** **TABLE 30. CHANNEL TIMING RETARD STROBE Register (IWA = *01Bh)** N/A Writing to this location deletes one data sample in the CIC to FIR path. Used for shifting the FIR filter compute engine timing.

**TABLE 31. FILTER COMPUTE ENGINE INSTRUCTION RAMS (IWA = *100h THROUGH *17Fh)** and Filter Sequencer sections of the data sheet for more details. **TABLE 32. FILTER COMPUTE ENGINE INSTRUCTION POINTER RAMS (IWA = *180h THROUGH *1FCh)** **TABLE 33. FILTER COMPUTE ENGINE COEFFICIENT RAM1 (IWA = *440h THROUGH *47Fh)** filter coefficient storage locations. See the Filter Compute Engine and Filter Sequencer sections of the data sheet for more details. **TABLE 34. FILTER COMPUTE ENGINE COEFFICIENT RAM2 (IWA = *480h THROUGH *4FFh)** filter coefficient storage locations. See the Filter Compute Engine and Filter Sequencer sections of the data sheet for more details.

bits select this set of registers (F8XXh). TABLE 35. TEST CONTROL REGISTER (GWA = F800h) serial clock control register (GWA = F803h). normal output. 7=CH0 6=CH1 5=CH2 4=CH3. 3 Offset I PN by XORing bit 10 of the PN generator with the output PN.

2 Enable (2

(223 - 1) sequence on the I channel to decorrelate it from the Q channel. Otherwise, the same sequence will be used on both I and Q. 1 Enable (2 15 - 1) PN generator. 0 Test mode. When asserted, this bit puts the chip into internal (self) test mode. TABLE 36. BUS ROUTING CONTROL REGISTER (GWA = F801h) any interrupt pulse in process will finish). 19:17 DataRdy delay (CH1 only). Test. From 1-8. AGC gain input of CH0. 0=CH3, 1=CH1. 15:14 CH3 ext source mux sel. These bits select whether the CH2 s ource mux, CIC2, or FIR2out is routed to the external input of FIR3. 0=CH2srcmux, 1=FIR2, 2=CIC2. 13 CH2 ext source mux sel. This bit selects whether the CH1 exter nal source mux or FIR1out is routed to the external input of FIR2. 11 CH0 backend input sel. 0=CIC0, 1=CIC1 (test). 10 CH1 backend input sel 0=CIC1, 1=CH1 ext src mux. 9 CH2 backend input sel 0=CIC2, 1=CH2 ext src mux. 8 CH3 backend input sel 0=CIC3, 1=CH3 ext source mux.

7 CH0 Ext AGC input enable. 0=CH0 loop filt, 1=external input. 6 CH1 Ext AGC input enable 0=CH1 loop filt, 1=external input. 5 CH2 Ext AGC input enable 0=CH2 loop filt, 1=external input. 4 CH3 Ext AGC input enable Set to 0. 3 CH0 enable serial output 1=FIR0 out enabled to serial outputs. 2 CH1 enable serial output 1=FIR1 out enabled to serial outputs. 1 CH2 enable serial output 1=FIR2 out enabled to serial outputs. 0 CH3 enable serial output 1=FIR3 out enabled to serial outputs. TABLE 36. BUS ROUTING CONTROL REGISTER (GWA = F801h) (Continued) TABLE 37. RESET/SYNC/INTERRUPT SOURCE SELECTION REGISTER (GWA = F802h) synchronous and phase continuous across channels. cycles to initialize the read and write pointers. 27 When this bit is set, the AGC is reset on SYNCI. 25 When this bit is set, the CIC decimation counter is reset on SYNCI. 24 When this bit is set, the serial output block is reset on SY NCI. If bit 4 in location GWA F803h is set, the serial clock divider is also reset. 23:16 Same functions as 31:24 for channel 1. 15:8 Same functions as 31:24 for channel 2. 7:0 Same functions as 31:24 for channel 3. TABLE 38. SERIAL CLOCK CONTROL REGISTER (GWA = F803h) 5 When set to 1, this bit will keep the se rial clock disabled after a hardware reset until receipt of the first SYNCI signal. Reset/Sync register (GWA = F802h, bits 24, 16, 8 or 0) will reset the serial clock divider. 1 Clock low to high transition occurs at the center of the data bit. 0 Clock high to low transition at the center of the data bit.

001 Serial clock rate is Input CLK Rate. 010 Serial clock rate is Input CLK Rate/2. 011 Serial clock rate is Input CLK Rate/4. 100 Serial clock rate is Input CLK Rate/8. 101 Serial clock rate is Input CLK Rate/16. TABLE 38. SERIAL CLOCK CONTROL REGISTER (GWA = F803h) (Continued) TABLE 39. INPUT LEVEL DETECTOR SOURCE SELECT/FORMAT REGISTER (GWA = F804h) Test Input register as shown below. This is provided for testing and to zero the input data bus when a channel is not in use. The Global Write Address register for the μP Test input register is F807h. constant or to disable the input for minimum power dissipation when the input level detector section is unused. 11 μP input enable. When bit 12 is set, this bit is the input enable for the μP register input. Active low. 0=enabled, 1=disabled.

10 Parallel Data Input Format

0 Two’s complement

1 Offset binary

9 Fixed/Floating point

0 Fixed point

select the mantissa/exponent grouping, add an offset to the exponent and set the shift control saturation level. the input of the input level detector at the next ENIx. 111 7 clock periods of delay.

3 Interpolated/Gated Mode Select

1 Interpolated. The input level detector is upda ted every clock. The input is zeroed when ENIx is high.

TABLE 39. INPUT LEVEL DETECTOR SOURCE SELECT/FORMAT REGISTER (GWA = F804h) (Continued) TABLE 40. INPUT LEVEL DETECTOR CONF IGURATION REGISTER (GWA = F805h) 21 1 Ones complement of 16-bit data after formatting. 20 1 Free run (ignore interval counter). 0 Stop when interval counter times out. This bit may also be set low temporarily when free running to stabilize the accumulator data for reading. 19:18 Input Level Detector Leak factor, A. 00 Leaky integrator (Y n = A*Xn + (1-A)*Yn-1, where A is the gain selected in bits 19:18). 10 Integrator (bit 20 should be set to 0). Load with two less than the desired number of input samples. The interval range is 2 to 65537 input samples. TABLE 41. INPUT LEVEL DETECTOR START STROBE REGISTER (GWA = F806h) bit 1 of the status word is set. TABLE 42. μP/TEST INPUT BUS REGISTER (GWA = F807h) input to a constant value to minimize power when the channel is not in use. F808h (selected via bit 12 of the channel register at IWA *000h). TABLE 43. μP/TEST INPUT BUS ENI REGISTER (GWA = F808h) N/A A write to this location, generates and ENI strobe for the μP driven input port (when selected via bit 12 of IWA *000h). TABLE 44. SYNCO STROBE REGISTER (GWA = F809h) inserted in the SYNCO to SYNCI path.

address 3 (ADD(2:0) = 3) to select and/or fetch the data. A strobe is generated, if needed, to fetch or stabilize the data for reading. of the Indirect Address select the target channel register for the data being read. Values of 0 through 3 and F are valid. TABLE 45. μP FIFO READ ORDER CONTROL REGISTER (GWA = F820h THROUGH F83Fh) where CC is the channel number and DDD is the data type. 000 I(23:8) The upper 16 bits of the I data path via the FIFO/AGC. 001 I(7:0),8*zeros The lower 8 bits of the I data path. 010 Q(23:8) The upper 16 bits of the Q data path via the FIFO/AGC. 011 Q(7:0),8*zero The lower 8 bits of the Q data path.

100 Mag(23:8) The upper 16 bits of magnitude (a fter the gain adjust described in channel register)

101 Mag(7:0),8*zero The lower 8 bits of magnitude. 110 Phase(15:0) The upper 16 bits of phase. 111 AGC gain (15:0) The upper 16 bits of the AGC gain. TABLE 46. TABLE OF INDIRECT READ ADDRESS (IRA) REGISTERS *006h Active Carrier NCO Center Frequency. *00Ch Wait Preload, Decr 1&2. *009h Active Timing NCO Center Freq (Most Significant 32 bits). *00Fh AGC gain (must first write to AGC gain read strobe register IWA = *00Fh before reading). *100h - *17Fh Instruction RAMs. *180h - *1FCh Instruction RAMs (pointer DRAM). *400h - *43Fh Coefficient ROM -HBF, const. *440h - *47Fh Coefficient RAM -1. *480h - *4FFh Coefficient RAM -2. *500h - *5FFh Coefficient ROM -Resampler. F806h Input Level Detector Output.

Absolute Maximum Ratings Thermal Information Operating Conditions Temperature Range Thermal Resistance (Typical) θJA (°C/W) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications VCC = 3.3V ± 0.15V, TA = -40°C to 85°C, Industrial PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Logical One Input Voltage V IH VCC = 3.45V 2.0 - V Logical Zero Input Voltage V IL VCC = 3.15V - 0.8 V Output High Voltage V OH IOH = -2mA, VCC = 3.15V 2.6 - V Output Low Voltage V OL IOL = 2mA, VCC = 3.15V - 0.4 V Input Leakage Current I I VIN = VCC or GND, VCC = 3.45V -10 10 μA Output Leakage Current I O VIN = VCC or GND, VCC = 3.45V -10 10 μA Standby Power Supply Current I CCSB VCC = 3.45V, Outputs Not Loaded, No CLK -5 0 0 μA Operating Power Supply Current I CCOP f = 70MHz, VIN = VCC or GND, VCC = 3.45V, Outputs Not Loaded -8 5 0 m A (Note 6) Input Capacitance C IN Freq = 1MHz, VCC open, all measurements are referenced to device ground -7 p F (Note 7) Output Capacitance C OUT -7 p F (Note 7) NOTES: 6. Power Supply current is proportional to frequency of operation and programmed configuration of the part. Typical rating for ICCOP is 11mA/MHz. 7. Capacitance: T A = 25°C, controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes. Electrical Specifications VCC = 3.3V ± 0.15V, TA = -40°C to 85°C Industrial PARAMETER SYMBOL MIN MAX UNITS INPUT AND CONTROL TIMING CLK Frequency f CLK -7 0 M H z CLK High tCH 5- n s CLK Low tCL 5- n s Setup Time - Data Inputs, Input Enables, SYNCI to CLK High t DS 6- n s Hold Time - Data Inputs, Input Enables, SYNCI to CLK High t DH 0- n s CLK to Output Valid - SYNCO, INTRPT tPDC -6 . 5 n s RESET Pulse Width Low tRW 5- n s RESET Setup Time to CLK High (Note 8) t RS 6- n s HSP50216

Output Rise, Fall Time (Note 9) t RF -3 n s MICROPROCESSOR WRITE TIMING P(15:0) Setup Time to Rising Edge of WR tDSW 10 - ns P(15:0) Hold Time from Rising Edge of WR tDHW -2 - ns A(1:0) Setup Time to Rising Edge of WR tASW 10 - ns A(1:0) Hold Time from Rising Edge of WR tAHW -2 - ns CE Setup Time to Rising Edge of WR tCSW 10 - ns CE Hold Time from Rising Edge of WR tCHW -2 - ns WR Low Time tWL 5- n s MICROPROCESSOR READ TIMING A(1:0) Setup Time to FALLING Edge of RD tASR 8- n s A(1:0) Hold Time from RISING Edge of RD tAHR -2 - ns RD Enable Time tRE -1 1 . 5 n s RD Disable Time (Note 9) tRD -8 n s RD to P(15:0) Data Valid Time t DV -1 2 n s CE Setup Time to Falling Edge of RD tCSR 8- n s CE Hold Time from Rising Edge of RD tCHR -2 - ns SERIAL CLOCK OUTPUT TIMING CLK to Serial Data, Sync and SCLK (Divide-by 2 through 16 Modes) t PD -6 . 5 n s CLK Low to SCLK Low (Divide-by 1 Mode, Note 9) t PDL -6 . 5 n s CLK High to SCLK High (Divide-by 1 Mode, Note 9) t PDH -3 n s Time Skew Between SCLK and Serial Data or Serial Sync (Divide-by 2 through 16 Modes, Note 9) tSKEW1 -1 1 ns Time Skew Between SCLK and Serial Data or Serial Sync (Divide-by 1 Mode, Note 9) t SKEW2 0.5 2 ns NOTES: 8. The HSP50216 goes into reset immediately on RESET going low and comes out of reset on the 4th rising edge of CLK after RESET goes high. 9. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes. Electrical Specifications VCC = 3.3V ± 0.15V, TA = -40°C to 85°C Industrial (Continued) PARAMETER SYMBOL MIN MAX UNITS EQUIVALENT CIRCUIT CL (NOTE) IOH 1.5V I OL DUT SWITCH S1 OPEN FOR ICCSB AND ICCOP NOTE - TEST HEAD CAPACITANCE, 40pF (TYP) HSP50216

TABLE 47. CIC PASSBAND AND ALIAS LEVELS

TABLE 48. DECIMATING HALFBAND FIR FILTER COEFFICIENTS

1. Decimating Halfband Filter #4 Coefficients are shown for refere nce only and if it is desired to implement this FIR filter these coefficients would

have to be loaded into the FIR Coefficient RAM (They are not included in the ROMd Fir Filter Coefficient memory).

1. The 22-bit ROMd FIR filter c oefficients are located in the upper 22 bits of the Read register when read back from ROM memory (except for

for the hexadecimal coefficient is calculated by first converting the hexadecimal value to decimal and the dividing by 223 (8388608).

TABLE 49. INTERPOLATING HALFBAND FIR FILTER COEFFICIENTS

1. The 22-bit ROMd FIR filter coefficients are located in the upper 22 bits of the Read

bytes (24 bits) with the two LSBs of the lower byte (bits 9:8 of 31:0) being zero. the hexadecimal value to decimal and the dividing by 223 (8388608).

TABLE 50. RESAMPLER FIR FILTER COEFFICIENTS

1. The 22-bit ROMd FIR filter c oefficients are located in the upper 22 bits of the Read register when read back from ROM memory. These bits

TABLE 51. BIT WEIGHTING FOR AGC LOOP FEEDBACK PATH

All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/o r specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How- ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation 2401 Palm Bay Rd., Mail Stop 53-204 Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369 HSP50216 Plastic Ball Grid Array Packages (BGA) o TOP VIEW DA1 CORNER BOTTOM VIEW P N L M J K G H F E 81314 12 11 10 9 CORNER 765 3 42 C D A B SIDE VIEW SEATING PLANE C A bbb Caaa A1 CORNER I.D. E A B b S ALL ROWS AND COLUMNS S M A BC C 0.15 0.08 M 0.006 0.003 CORNER I.D. e A A C V196.12x12

196 BALL PLASTIC BALL GRID ARRAY PACKAGE

A - 0.059 - 1.50 - A1 0.012 0.016 0.31 0.41 - A2 0.037 0.044 0.93 1.11 - b 0.016 0.020 0.41 0.51 7 D/E 0.468 0.476 11.90 12.10 - D1/E1 0.405 0.413 10.30 10.50 - N 196 196 - e 0.032 BSC 0.80 BSC - MD/ME 14 x 14 14 x 14 3 bbb 0.004 0.10 - aaa 0.005 0.12 - Rev. 2 12/00 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 3. “MD” and “ME” are the maximum ball matrix size for the “D” and “E” dimensions, respectively. 4. “N” is the maximum number of balls for the specific array size. 5. Primary datum C and seating plane are defined by the spher- ical crowns of the contact balls. 6. Dimension “A” includes standoff height “A1”, package body thickness and lid or cap height “A2”. 7. Dimension “b” is measured at the maximum ball diameter, parallel to the primary datum C. 8. Pin “A1” is marked on the top and bottom sides adjacent to A1. 9. “S” is measured with respect to datum’s A and B and defines the position of the solder balls nearest to package center- lines. When there is an even number of balls in the outer row the value is “S” = e/2.