HSP50214BVCZ

HSP50214B_07 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

• Up to 65MSPS Front-End Processing Rates (CLKIN) and 55MHz Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous
• Processing Capable of >100dB SFDR
• Up to 255-Tap Programmable FIR
• Overall Decimation Factor Ranging from 4 to 16384
• Output Samples Rates to ≅ 12.94MSPS with Output Bandwidths to ≅ 982kHz Lowpass
• 32-Bit Programmable NCO for Channel Selection and Carrier Tracking
• Digital Resampling Filter for Symbol Tracking Loops and Incommensurate Sample-to-Output Clock Ratios
• Digital AGC with Programmable Limits and Slew Rate to Optimize Output Signal Resolution; Fixed or Auto Gain Adjust
• Serial, Parallel, and FIFO 16-Bit Output Modes
• Cartesian to Polar Converter and Frequency Discriminator for AFC Loops and Demodulation of AM, FM, FSK, and DPSK
• Input Level Detector for External I.F. AGC Support
• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Single Channel Digital Software Radio Receivers
• Base Station Rx’s: AMPS, NA TDMA, GSM, and CDMA
• Compatible with HSP50210 Digital Costas Loop for PSK Reception
• Evaluation Platform Available

Ordering Information

PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. NO. HSP50214BVC HSP50214BVC 0 to +70 120 Ld MQFP Q120.28x28 HSP50214BVCZ (Note) HSP50214BVCZ 0 to +70 120 Ld MQFP (Pb-free) Q120.28x28 HSP50214BVI HSP50214BVI -40 to +85 120 Ld MQFP Q120.28x28 HSP50214BVIZ (Note) HSP50214BVIZ -40 to +85 120 Ld MQFP (Pb-free) Q120.28x28 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Data Sheet May 1, 2007 FN4450.4

2 FN4450.4 May 1, 2007 Block Diagram HALFBAND POLYPHASE FIR AND FILTERS INPUT SECTION LEVEL DETECT CARRIER 5TH CARTESIAN TO OUTPUT FORMATTER DISCRIMINATOR AGC LOOP FILTER MAG. PHASE RESAMPLING I OUT Q OUT FREQ AGC Δ TIMING ERROR IN(13:0) REFCLK SEROUTA SEROUTB AOUT(15:0) BOUT(15:0) CONTROL C(7:0) MICROPROCESSOR READ/WRITE GAIN (2:0) HALFBAND FILTERSFILTER CIC ORDER HALFBAND FILTERS POLAR COORDINATE CONVERTER HALFBAND POLYPHASE FIR AND FILTERS NCO NCOCOF SOF ADJ CLKIN PROCCLK 255-TAP FIR FILTER 255-TAP FIR FILTER 5TH FILTER CIC ORDER HSP50214B

3 FN4450.4 May 1, 2007 Pinout HSP50214B (120 LD MQFP) TOP VIEW 60 91 100 106 107 108 109 110 111 101 102 103 104 105 117 118 119 120 112 113 114 115 116 NC BOUT3 BOUT2 BOUT1 OEBL BOUT0 BOUT4 GND PROCCLK VCC MSYNCI GND BOUT7 BOUT6 BOUT5 GND MSYNCO GND BOUT15 BOUT14 V CC NC BOUT12 BOUT11 BOUT10 BOUT9 BOUT8 BOUT13 OEBH DATARDY SYNCOUT INTRRP WR RD GND NC V CC NC GND SEL2 SEL1 SEL0 GND SEROUTA SEROUTB SERSYNC SEROE SERCLK VCC SYNCIN2 SYNCIN1 COF GAINADJ0 COFSYNC GND SOF SOFSYNC VCC VCC IN0 IN1 GND IN3 CLKIN GND NC ENI GAINADJ2 IN4 IN8 IN9 IN10 GND IN7 NC IN6 IN5 IN2 OEAL GND AOUT0 AOUT1 AOUT2 AOUT3 AOUT4 NC V CC AOUT5 AOUT6 AOUT7 AOUT8 AOUT9 NC GND AOUT10 AOUT11 AOUT12 IN11 AOUT13 AOUT14 AOUT15 OEAH GND REFCLK V CC AGCGNSEL IN13 IN12 GAINADJ1 HSP50214B

4 FN4450.4 May 1, 2007 Pin Descriptions NAME TYPE DESCRIPTION VCC - Positive Power Supply Voltage. GND - Ground. CLKIN I Input Clock. This clock should be a multiple of the input sample rate. All input section processing occurs on the rising edge of CLKIN. The frequency of CLKIN is designated fCLKIN . IN(13:0) I Input Data. The format of the input data may be set to offset binary or 2’s complement. IN13 is the MSB (see Control Word 0). ENI I Input Enable. Active Low. This pin enables the input to the part in one of two modes, gated or interpolated (see Control Word 0). In gated mode, one sample is taken per CLKIN when ENI is asserted. The input sample rate is designated fS, which can be different from fCLKIN when ENI is used. GAINADJ(2:0) I GAINADJ Input. Adds an offset to the gain via the shifter following the mixer. GAINADJ value is added to the shift code from the microprocessor (μP) interface. The shift code is saturated to a maximum code of F. The gain is offset by (6dB)(GAINADJ); (000 = 0dB gain adjust; 111 = 42dB gain adjust) GAINADJ2 is the MSB. See “Using the Input Gain Adjust Control Signals” Section. PROCCLK I Processing Clock. PROCCLK is the clock for all processing functions following the CIC Section. Processing is performed on PROCCLK’s rising edge. All output timing is derived from this clock. This clock may be asynchronous to CLKIN. AGCGNSEL I AGC Gain Select. This pin selects between two AGC loop gains. This input is setup and held relative to PROCCLK. Gain setting 1 is selected when AGCGNSEL = 1. COF I Carrier Offset Frequency Input. This serial input pin is used to load the carrier offset frequency into the Carrier NCO (see Serial Interface Section). The offset may be 8, 16, 24, or 32-bits. The setup and hold times are relative to CLKIN. This input is compatible with the output of the HSP50210 Costas loop [1]. COFSYNC I Carrier Offset Frequency Sync. This signal is asserted one CLK before the most significant bit (MSB) of the offset frequency word (see Serial Interface Section). The setup and hold times are relative to CLKIN. This input is compatible with the output of the HSP50210 Costas loop [1]. SOF I Re-Sampler Offset Frequency Input. This serial input pin is used to load the offset frequency into the Re-Sampler NCO (see Serial Interface Section). The offset may be 8, 16, 24, or 32-bits. The setup and hold times are relative to PROCCLK. This input is compatible with the output of the HSP50210 Costas loop [1]. SOFSYNC I Re-Sampler Offset Frequency Sync. This signal is asserted one CLK before the MSB of the offset frequency word (see Serial Interface Section). The setup and hold times are relative to PROCCLK. This input is compatible with the output of the HSP50210 Costas loop [1]. AOUT(15:0) O Parallel Output Bus A. Two parallel output modes are available on the HSP50214B. The first is called the Direct Output Port, where the source is selected through Control Word 20 (see the Microprocessor Write Section) and comes directly from the Output MUX Section (see Output Control Section). The most significant byte of AOUT always outputs the most significant byte of the Parallel Direct Output Port whose data type is selected via μP interface. AOUT15 is the MSB. In this mode, the AOUT(15:0) bus is updated as soon as data is available. DATARDY is asserted to indicate new data. For this mode, the output choices are: I, |r|, or f. The format is 2’s complement, except for magnitude, which is unsigned binary with a zero as the MSB. The second mode for parallel data is called the Buffer RAM Output Port. The Buffer RAM Output Port acts like a FIFO for blocks of information called data sets. Within a data set is I, Q, magnitude, phase, and frequency information; a data type is selected using SEL(2:0). Up to 7 data sets are stored in the Buffer RAM Output Port. The LSBytes of the AOUT and BOUT busses form the 16-bits for the buffered output mode and can be used for buffered mode while the MSBytes are outputting data in the direct output mode. For this mode, the output formats are the same as the Direct Output Port mode. BOUT(15:0) O Parallel Output Bus B. Two parallel output modes are available on the HSP50214B. The first is called the Direct Output Port, where the source is selected through Control Word 20 (see the Microprocessor Write Section) and comes directly from the Output MUX Section (see Output Control Section). The most significant byte of BOUT always outputs the most significant byte of the Parallel Direct Output Port whose data type is selected via μP interface. BOUT15 is the MSB. In this mode, the BOUT(15:0) bus is updated as soon as data is available. DATARDY is asserted to indicate new data. For this mode, the output choices are: Q, φ, or |r|. The format is 2’s complement, except for magnitude which is unsigned binary with a zero as the MSB. The second mode for parallel data is called the Buffer RAM Output Port. The Buffer RAM Output Port acts like a FIFO for blocks of information called data sets. Within a data set is I, Q, magnitude, phase, and frequency information; a particular information is selected using SEL(2:0). Up to 7 data sets is stored in the Buffer RAM Output Port. The least significant byte of BOUT can be used to either output the least significant byte of the B Parallel Direct Output Port or the least significant byte of the Buffer RAM Output Port. See Output Section. For this mode the output formats are the same as the Direct Output Port mode. HSP50214B

5 FN4450.4 May 1, 2007 DATARDY O Output Strobe Signal. Active Low. Indicates when new data from the Direct Output Port Section is available. DATARDY is asserted for one PROCCLK cycle during the first clock cycle that data is available on the parallel out busses. See Output Section. OEAH I Output enable for the MSByte of the AOUT bus. Active Low. The AOUT MSByte outputs are three-stated when OEAH is high. OEAL I Output enable for the LSByte of the AOUT bus. Active Low. The AOUT LSByte outputs are three-stated when OEAL is high. OEBH I Output enable for the MSByte of the BOUT bus. Active Low. The BOUT MSByte outputs are three-stated when OEBH is high. OEBL I Output enable for the LSByte of the BOUT bus. Active Low. The BOUT LSByte outputs are three-stated when OEBL is high. SEL(2:0) I Select Address is used to choose which information in a data set from the Buffer RAM Output Port is sent to the least significant bytes of AOUT and BOUT. SEL2 is the MSB. INTRRP O Interrupt Output. Active Low. This output is asserted for 8 PROCCLK cycles when the Buffer RAM Output Port is ready for reading. SEROUTA O Serial Output Bus A Data. I, Q, magnitude, phase, frequency, timing error and AGC information can be sequenced in programmable order. See Output Section and Microprocessor Write Section. SEROUTB O Serial Output Bus B Data. Contents may be related to SEROUTA. I, Q, magnitude, phase, frequency, timing error and AGC information can be sequenced in programmable order. See Output Section and Microprocessor Write Section. SERCLK O Output Clock for Serial Data Out. Derived from PROCCLK as given by Control Word 20 in the Microprocessor Write Section. SERSYNC O Serial Output Sync Signal. Serves as serial data strobes. See Output Section and Microprocessor Write Section. SEROE I Serial Output Enable. When high, the SEROUTA, SEROUTB, SERCLK, and SERSYNC signals are set to a high impedance. C(7:0) I/O Processor Interface Data Bus. See Microprocessor Write Section. C7 is the MSB. A(2:0) I Processor Interface Address Bus. See Microprocessor Write Section. A2 is the MSB. WR I Processor Interface Write Strobe. C(7:0) is written to Control Words selected by A(2:0) in the Programmable Down Converter on the rising edge of this signal. See Microprocessor Write Section. RD I Processor Interface Read Strobe. C(7:0) is read from output or status locations selected by A(2:0) in the Programmable Down Converte r on the falling edge of this sign al. See Microproce ssor Read Section. REFCLK I Reference Clock. Used as an input clock for the timing error detector. The timing error is computed relative to REFCLK. REFCLK frequency must be less than or equal to PROCCLK/2. MSYNCO O Multiple Chip Sync Output. Provided for synchronizing multiple parts when CLKIN and PROCCLK are asynchronous. MSYNCO is the synchronization signal between the input section operating under CLKIN and the back end processing operating under PROCCLK. This output sync signal from one part is connected to the MSYNCI signal of all the HSP50214Bs. MSYNCI I Multiple Chip Sync Input. The MSYNCI pin of all the parts should be tied to the MSYNCO of one part. NOTE: MSYNCI must be connected to an MSYNCO signal for operation. SYNCIN1 I CIC Decimation/Carrier NCO Update Sync. Can be used to synchronize the CIC Section, carrier NCO update, or both. See the Multiple Chip Synchronization Section and Control Word 0 in the Microprocessor Write Section. Active High. SYNCIN2 I FIR/Timing NCO Update/AGC Gain Update Sync. Can be used to synchronize the FIR, Timing NCO update, AGC gain update, or any combination of the above. See the Multiple Chip Synchronization Section and Control Words 7, 8, and 10 in the Microprocessor Write Section. Active High. SYNCOUT O Strobe Output. This synchronization signal is generated by the μP interface for synchronizing multiple parts. Can be generated by PROCLK or CLKIN (see Control Word 0 and Control Word 24 in the Microprocessor Write Section). Active High. Pin Descriptions (Continued) NAME TYPE DESCRIPTION HSP50214B

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF THE HSP50214B PROGRAMMABLE DOWNCONVERTER

DSP microprocessor to pass baseband and status data.

1. The diagram shows the major blocks and

sections are configured through a microprocessor interface. NOTE: All of the clocks may be asynchronous. changes in the analog RF front end receive equipment. TABLE 1. CELLULAR PHONE BASE STATION

same gain value at the arrival of the next user burst. preamble pattern to aid in burst acquisition. demodulation and optimum detection of the GMSK signals. received signals are required, such as base-stations. the received signal. AMPS is an example of an FM application. timing recovery loop filters to complete the receiver design. Loop Filtering is required for this waveform. TABLE 2. CELLULAR BASESTATION APPLICATIONS USING

loading and timing is relative to PROCCLK. NOTE: TD can be 0, and the fastest rate is with 8-bit word width. bit value is pipelined to match the delay of the input samples. the permissible CIC Shift Gain values. the first integrator in the CIC is used to offset this variation. be adjusted in 6dB steps to control the CIC output level. where R is the decimation factor and N is the number of stages. maximum decimation in the CIC to 32 for a full scale input. If R is 32, the gain through all five integrator stages is 325 = 225. TABLE 3. GAIN ADJUST CONTROL AND CIC DECIMATION FIGURE 15. CIC SHIFT GAIN VALUES

16 FN4450.4 May 1, 2007 last 3 it is 215, etc.). The sum of the input bits and the growth bits cannot exceed the accumulator size. This means that for a decimation of 32 and 15 input bits, the first accumulator must be 15 + 25 = 40-bits. Thus, the value of the CIC Shift Gain word can be calculated: NOTE: The number of input bits is IIN. (If the number of bits into the CIC filter is used, the value 40 replaces 39). For 14-bits, Equation 7 becomes: For 12-bits, Equation 7 becomes: For 10-bits, Equation 7 becomes: For 8-bits, Equation 7 becomes: Figure 15 is a plot of Equations 8A through 8D. The 4-bit CIC Shift Gain word has a range from 0 to 15. The 6-bit Decimation Factor counter preload field, (R-1), has a range from 0 to 63, limited by the input resolution as cited above. Using the Input Gain Adjust Control Signals The input gain offset control GAINADJ(2:0)) is provided to offset the signal gain through the part, i.e., to keep the CIC filter output level constant as the analog front end attenuation is changed. The gain adjust offset is 6dB per code, so the gain adjust range is 0 to 42dB. For example, if 12dB of attenuation is switched in at the receiver RF front end, a code of 2 would increase the gain at the input to the CIC filter up 12dB so that the CIC filter output would not drop by 12dB. This fixed gain adjust eliminates the need for the software to continually normalize. One must exercise care when using this function as it can cause overflow in the CIC filter. Each gain adjust in the shifter from the gain adjust control signals is the equivalent of an extra bit of input. The maximum decimation in the CIC is reduced accordingly. With a decimation of 32, all 40-bits of the CIC are needed, so no input offset gain is allowed. As the decimation is reduced, the allowable offset gain increases. Table 3 shows the decimation range versus desired offset gain range. Table 3 assumes that the CIC Shift Gain has been programmed per Equation 7 or 8A. The CIC filter decimation counter can be loaded synchronous with other PDC chips, using the SYNCIN1 signal and the CIC External Sync Enable bit. The CIC external Sync Enable is set via Control Word 0, Bit 19. Halfband Decimating Filters The Programmable Down Converter has five halfband filter stages, as shown in Figure 17. Each stage decimates by 2 and filters out half of the available bandwidth. The first halfband, or HB1, has 7 taps. The remaining halfbands; HB2, HB3, HB4, and HB5; have 11, 15, 19, and 23 taps respectively. The coefficients for these halfbands are given in Table 4. Figure 18 shows the frequency response of each of the halfband filters with respect to normalized frequency, F N. Frequency normalization is with respect to the input sampling frequency of each filter section. Each stage is activated by their respective bit location (15-20) in Control Word 7. Any combination of halfband filters may be used, or all may be bypassed. (EQ. 7)SG = FLOOR 39 - [ IIN() - log2(R)5 for 4<R<32 for R = 4= 15 SG FLOOR 25 log 2 R() 5 ]for 4 R 32<<–[= 15= for R 4= (EQ. 8A) SG FLOOR 27 log 2 R() 5 ]for 5 < R < 40–[= (EQ. 8B) 15= for 4 R 5 ≤≤ SG FLOOR 29 log 2 R() 5 ]for 6 < R < 52–[= (EQ. 8C) for 4 R 6 ≤≤15= SG FLOOR 31 log 2 R() 5 ]for 9 < R < 64–[= (EQ. 8D) 15= for 4 R 9 ≤≤ HSP50214B

number of multiplies for each of the halfband filter stages. then Equation 10 shows the minimum ratio needed. faster than (7x2+5x4+3x8)/8 = 7.25 times faster than fS . TABLE 4. HALFBAND FILTER COEFFICIENTS Processing Rates of the PDC”.

may be available for filter calculation. for an odd number of filter taps, 0 = an even number of taps. Use Equation 12A to calculate the maximum input rate. rate for both real and complex filters.

1. Note that complex filters can also be

coefficients that are used need to be loaded. Asymmetric: A filter with no coefficient symmetry. Even Tap filter: A filter where N is an even number. Odd Tap filter: A filter where N is an odd number. Real Filter: A filter implem ented with real coefficients. Complex Filters: A filter with quadrature coefficients. FIGURE 20. DEMONSTRATION OF DIFFERENT TYPES OF

Error Detector output has the identical range. signal/weak signal, track/hold, or fast/slow AGC values. TABLE 5. AGC THRESHOLD (CONTROL WORD 8) BIT

† Controlled via microprocessor interface. FIGURE 23. AGC BLOCK DIAGRAM

4 EXPONENT)

15 E LG–()–

reducing any AM distortion caused by the AGC. range” signals than for “under range” signals (or vice versa). after an initial AGC settling period. independent of the signal level. adjustments during tracking. works identically to the HSP50214. TABLE 7. AGC LOOP GAIN BINARY MANTISSA TO GAIN TABLE 8. AGC LOOP GAIN BINARY EXPONENT TO GAIN

26 FN4450.4 May 1, 2007 TABLE 9A. BIT WEIGHTING FOR AGC LOOP FEEDBACK PATH AGC ACCUM BIT POSITION GAIN ERROR INPUT GAIN ERROR BIT WEIGHT AGC LOOP FILTER GAIN (MANTISSA) AGC LOOP FILTER GAIN MULTIPLIER (OUTPUT) SHIFT = 0 SHIFT = 4 SHIFT = 8 SHIFT = 15 AGC OUTPUT AND AGC LIMITS BIT WEIGHT AGC GAIN RESOLUTION (dB) 31 2 2 2 2 0 30 2 2 2 2 E 3 48 29 2 2 2 2 E 2 24 28 2 2 2 2 E 1 12 27 12 = 2 2 2 2 2 2 E 0 6 26 11 = 1 1 2 2 2 1 M -1 3 24 9 = 1 x 1 2 2 2 1 M -3 0.75 23 8 = 2 x 2 2 2 2 2 M -4 0.375 22 7 = 3 x 3 2 2 2 3 M -5 0.1875 21 6 = 4 x 4 2 2 2 4 M -6 0.09375 20 5 = 5 5 2 2 2 5 M -7 0.04688 19 4 = 6 6 2 2 1 6 X -8 0.02344 18 3 = 7 7 2 2 0. 7 -9 0.01172 17 2 = 8 8 2 2 1 8 -10 0.00586 16 1 = 9 9 2 2 2 9 -11 0.00293 15 0 = 10 10 2 1 3 10 -12 0.00146 14 11 2 0. 4 11 -13 0.000732 13 12 2 1 5 12 -14 0.000366 12 13 2 2 6 13 -15 0.000183 11 14 1 3 7 14 -16 0.0000916 10 0. 4 8 G -17 0.0000458 9 1 5 9 G -18 0.0000229 8 2 6 10 G -19 0.0000114 7 3 7 11 G -20 0.00000572 6 4 8 12 G -21 0.00000286 5 5 9 13 G 4 6 10 14 G 3 7 11 G G 2 8 12 G G 1 9 13 G G 0 10 14 G G AGC ResponseMax = Input(Cart/PolarGain)(Error Det Gain)(AGC Loop GainMax)(AGC Output Weighting).G = ground = 0. AGC ResponseMax = . AGC ResponseMin = . Thus, the expected range for the AGC rate is ~ 0.000106 to 3.275dB/output sample time. 2() 1.64676() 15 ⎛⎞ 1() 1.5dB() 3.275dB/output sample time∼ 2() 1.64676() 2 15–() 1() 1.5dB() 0.000106dB/output sample time∼ HSP50214B

27 FN4450.4 May 1, 2007 TABLE 9B. PDC BIT WEIGHTING BIT WEIGHT INPUT SIN/COS MIX OUT CIC IN SHIFT = 0 CIC IN SHIFT = 15 CIC BIT WEIGHTS IIIIICCCCC CIC OUT HB DATA IN HB DATA OUT/FIR IN FIR COEF FIR MULTI/ ACC FIR OUT 0 0 0 0 S S xxxxxxxxxx 0 0 0 0 1 1 1 1 1 S S xxxxxxxxxx 1 1 1 1 0 0 2 2 2 2 S S xxxxxxxxxx 2 2 2 2 1 1 3 3 3 3 S S xxxxxxxxxx 3 3 3 3 2 2 4 4 4 4 S S xxxxxxxxxx 4 4 4 4 3 3 5 5 5 5 S S xxxxxxxxxx 5 5 5 5 4 4 6 6 6 6 S S xxxxxxxxxx 6 6 6 6 5 5 7 7 7 7 S S xxxxxxxxxx 7 7 7 7 6 6 8 8 8 8 S S xxxxxxxxxx 8 8 8 8 7 7 9 9 9 9 S S xxxxxxxxxx 9 9 9 9 8 8 10 10 10 10 S 10(S) xxxxxxxxxx 10 10 10 10 9 9 11 11 11 11 S 11 xxxxxxxxxx 11 11 11 11 10 10 12 12 12 12 S 12 xxxxxxxxxx 12 12 12 12 11 11 13 13 13 13 S 13 xxxxxxxxxx 13 13 13 13 12 12 14 14 14 S 14 xxxxxxxxxx 14 14 14 14 13 13 15 15 SRnd S 15 xxxxxxxxxx 15 15 15 15 14 14 16 16 S 16 xxxxxxxxxx 16 16 16 16 15 15 17 17 S 17 xxxxxxxxxx 17 17 17 17 16 16

18 S 18 xxxxxxxxxx 18 18 18 18 17 17

19 S 19 xxxxxxxxxx 19 19 19 19 18 18

20 S 20 xxxxxxxxxx 20 20 20 20 19 19

21 S 21 xxxxxxxxxx 21 21 21 21 20 20

22 S 22 xxxxxxxxxx 22 22 22 21 21

23 S 23 xxxxxxxxxx 23 23 23 22 22

24 S 24 xxxxx Rnd Rnd Rnd 23 23

25 25(S) 25 xxxxx SAT SAT SAT 24 24 26 26 26 xxxxx 25 Rnd 27 27 27 xxxxx 26 SAT 28 28 28 xxxxx 27 29 29 29 xxxxx 28 30 30 30 xxxxx 29 31 31 31 xxxxx 30 32 32 32 xx 31 33 33 33 xx 32 34 34 34 xx (Rnd Out of Mult.) 35 35 35 xx 36 36 36 x 37 37 37 x 38 38 38 x 39 39 39 x NOTES: 1. SRnd = Symmetric Round; Rnd = Round; SAT = Saturation. 2. The NBW out of the CIC filter is 0.5 x fSOUT. If the NBWIN = fS / 4 and NBWOUT = fSOUT/2, then the processing gain for a decimation x 16 CIC should be ~ 8 (9dB or 1.5 bits) versus A/D noise, the processing gain should be 10log(BWIN / BWOUT). HSP50214B

minimizes intersymbol interference. halfband filters are then used to obtain the 8x CDMA output. TABLE 10. POLYPHASE AND INTERPOLATING HALFBAND

1 Halfband

2 Halfband

1. This frequency is set by the Resampler NCO.

FIGURE 25. GENERATING DATA READY PULSES FOR

0 BYPASS

and phase of the I/Q vector. The I and Q inputs are 18 bits.

1. The phase conversion gain is 1/2π.

bits. The MSB is always zero. 16-bits output from the PDC. stage, either the output formatter or frequency discriminator. always be worse than the Cartesian to Polar conversion. contributing factor in the phase and frequency computations. only 4-bits each for I and Q. FIR filter to be routed directly to the coordinate converter. phase, and frequency computations. still routed to the discriminator. TABLE 11. MAG/PHASE BIT WEIGHTING FIGURE 28. PHASE BIT MAPPING OF COORDINATE TABLE 12. MAG/PHASE ACCURACY vs CLOCK CYCLES

the AGC) plus the compute delay of the resampler block. Control Word 27, Bit 13 to a logic zero. by 4, and a multiply of 23 reduces the range by 8. 2) 18-bits of magnitude from the coordinate converter block. added to provide for processing SSB signals. † Controlled via microprocessor interface. FIGURE 29. FREQUENCY DISCRIMINATOR BLOCK DIAGRAM

00 Item (1) described above. 01 Item (2) described above. 1X Item (3) described above. 0 I and Q enabled to the I/Q to R/Theta block. 1 The Q input to the I/Q to R/Theta block is zeroed.

1 The data ready strobe from the coordinate con -

2 The data ready strobe from the coordinate con -

AGC output data ready signal. when the resampler/halfband filters are enabled. the frequency discriminator. processor interface or a 16-bit processor interface. DATARDY is asserted can be different. † Controlled via microprocessor interface. FIGURE 30. PARALLEL OUTPUT BLOCK DIAGRAM

identical number of words in the serial output streams. while the remaining signals are 2’s complement format. desired data words have been linked. sample time until a new value appears at the filter output. output using the Serial Output mode. TABLE 13. LINKING CONTROL WORDS FOR SERIAL OUTPUT

000 I Data

001 Q Data

010 Magnitude (MAG) Data

011 Phase (PHAS) Data

100 Frequency (FREQ) Data

101 Timing Error (TIMER) Data

110 AGC Gain

111 Zeros

FIGURE 34. SERIAL OUTPUT FORMATTER BLOCK DIAGRAM

010 MAG

011 PHASE

100 FREQUENCY

101 TIMING ERROR

110 AGC

Word 19 should be programmed. SEROUTA sequence that follows the duplicate data type. by the Magnitude data word is to be output on SEROUTA. microprocessor to synchronize to the serial data stream. TABLE 14. EXAMPLE 1 SERIAL OUTPUT CONTROL SETTINGS TABLE 15. EXAMPLE 2 SERIAL OUTPUT CONTROL SETTINGS

1. The Buffer RAM controller supports both FIFO

FIGURE 35. EXAMPLE 2 SERIAL OUTPUT DATA STREAM FIGURE 36. VALID SERSYNC CONFIGURATION OPTIONS it must be that way on both serial outputs.

• • • MSB WORD2 1 15 1412215 14 • • • MSB WORD1 LSB WORD2LSB WORD1
• • • 2 01 2 2 3 2 3 SERSYNC PRECEDES MSB SERSYNC FOLLOWS LSB 0 0 0 LSB WORD0

TABLE 16. RAM DATA STORAGE MAP sample time until a new value appears at the filter output.

the LSByte is sent to BOUT(7:0).

1. A DSP microprocessor or the

that the RAM is ready to be read. TABLE 17. BUFFER RAM OUTPUT SELECT DEFINITIONS

010 Magnitude

101 Unused

110 Memory Status

111 Reading this address increments to the next

TABLE 18. STATUS BIT DEFINITIONS the current depth of the FIFO.

4 EMPTY - When in FIFO mode, the FIFO is

3 FULL - When in FIFO mode, the FIFO is full, and

new samples will not be written.

2 READYB - When in FIFO mode, the output

buffer has reached the programmed threshold. of samples have been taken. Active Low. NOTE: In the Status output, BOUT(7:0) are all GND. FIGURE 37. 16-BIT MICROPROCESSOR INTERFACE BUFFER

pointer has already been incremented into a sample. Figure 38 shows INTRRP going low before the FIFO is read. FIFO must be monitored by the user via a status read. buffer has sufficient data to be read. same address (the circuitry will not allow this). are read or the FIFO is reset). Rule #4: You cannot write over what you have not read. is generated when the depth increments past the threshold. FIGURE 38. INTERFACE BETWEEN A 16-BIT

8 CLKS

FIGURE 39. TIMING DIAGRAM FOR PDC IN FIFO MODE WITH

samples and the snapshot interval. FIGURE 41. 8-BIT MICROPROCESSOR INTERFACE BUFFER RAM MODE BLOCK DIAGRAM

000000 R A M I L S B

000001 R A M I M S B

000010 R A M Q L S B

000011 R A M Q M S B

001000 R A M | r | L S B

001001 R A M | r | M S B

001010 R A M φ LSB

001011 R A M φ MSB

010000 R A M ƒ LSB

010001 R A M ƒ MSB

100000 I N P U T I N T E G L S B

100001 I N P U T I N T E G N M S B

100010 I N P U T I N T E G M S B

101000 A G C L S B

101001 A G C M S B

101010 T I M I N G L S B

101011 T I M I N G M S B

FIGURE 42. RAM LOAD SEQUENCE FIGURE 43. SNAP SHOT SAMPLING

Microprocessor Read Section. must be retrieved before time-out to avoid data loss. depending on the Destination Registers. A(2:0) determines the destination for the data on bus, C(7:0). Word to guarantee that the data has been transferred. register - not the Master Register. 20 details the steps to be taken. FIGURE 44. AVOIDING FALSE INTRRP ASSERTIONS TABLE 19. DEFINITION OF ADDRESS MAP Destination Register. Bit 0 is the LSB of the 32-bit register. map is given in the tables in the Control Word Section.

done to location 5 to select the source of data to be read. user could obtain the status bits quickly. details the steps to be taken. TABLE 20. EXAMPLE PROCESSOR WRITE SEQUENCE (23:16) on rising edge of WR. (31:24) on rising edge of WR. Configuration Control Register 0. FIGURE 45. LOADING THE CONTROL REGISTERS WITH TABLE 21. PROCESSOR READ SEQUENCE (INPUT LEVEL TABLE 22. DEFINITION OF ADDRESS MAP

000 Buffer RAM

001 Buffer RAM

010 Buffered

011 Not Used

100 Input Level

FIGURE 46. READING THE CONTROL REGISTERS USING A

44 FN4450.4 May 1, 2007 Composite Filter Response Example For this example consider a total receive band roughly 25MHz wide containing 124 200kHz wide FDM channels as shown in Figure 47. The design goal for the PDC is to tune to and filter out a single 200kHz FDM channel from the FDM band, passing only baseband samples onto the baseband processor at a multiple of the 270.8 KBPS bit rate. RF/IF Considerations The input frequency to the PDC is dependent on the A/D converter selected, the RF/IF frequency, the bandwidth of interest and the sample rate of the converter. If the A/D converter has sufficient bandwidth, then undersampling techniques can be used to downconvert IF/RF frequencies as part of the digitizing process, using the PDC to process a lower frequency alias of the input signal. For example, a 70MHz IF can be sampled at 40MHz and the resulting 10MHz signal alias can be processed by the PDC to perform the desired downconversion/tuning and filtering. If the IF signal is less than 1/2 the sample frequency then standard oversampling techniques can be used to process the signal. Of the two techniques, only undersampling allows part of the down conversion function to be brought into the digital domain just through sampling, assuming that a sampling frequency can be found that keeps the alias signals low and that the A/D converter has the bandwidth to accept the unconverted analog signal.

101 AGC Data

AGC (must write to location 10 to sample) 000- AGC LSB (lower 8-bits of linear Control Word 3 used by multiplier) mmmmmmmm LSB. 001- AGC MSB (4 shift control bits and first three bits of linear) Control Word oeeeemmm MSB. This yields 11-bits of the linear control mantissa. 010- Timing error LSB, not stabilized. 011- Timing error MSB, not stabilized.

110 Not Used

111 Not Used

Don’t Care Status 111- Status (6:0) consisting of (6:4)-FIFO depth when output is in FIFO Buffer RAM Output Mode. (3)-EMPTY signalling the FIFO is empty and the read pointer cannot be advanced (Active High). (2)-FULL signalling the FIFO is full and new samples will not be written (Active High). (1)-READYB Output buffer has reached the programmed threshold in FIFO mode or the programmed number of samples have been taken in snapshot mode. (Active Low). (0)-INTEGRATION has been completed in the input level detector and is ready to be read. (Active High). TABLE 22. DEFINITION OF ADDRESS MAP (Continued) FIGURE 47. RECEIVE SIG NAL FREQUENCY SPECTRUM

124 CHANNELS

45 FN4450.4 May 1, 2007 PDC Configuration For this example, the PDC is configured as follows: The basis for this configuration is: Sampling Rate: Select a high rate PROCCLK Output Rate: 1.083MHz (4x Bit Rate; 8x Baud Rate) CIC Filtering: Primarily Rate Reduction (39/18 = 2.166MHz). HB Filtering: Flat passband with rate reduction by 4 - low enough (541.66kHz) for sufficient FIR Taps to be used. FIR Filtering: Primary shaping filter/set final out of band suppression. Polyphase/HalfBand Filtering: Interpolate by two to output 8x baud rate or 4x bit rate. The CIC and halfband filter responses are shown in Figures 48A and 48B. The composite filter response constrained primarily by halfband filter 5 and the FIR filter, are shown in Figure 48C and 48D. For a more detailed discussion of design approaches and trades when designing with the PDC, refer to AN9720 [3], “Calculating the Maximum Processing Rates of the PDC”. References For Intersil documents available on the web, see www.intersil.com/ [1] HSP50210 Data Sheet, Intersil Corporation, FN3652. [2] Cellular Radio and Personal Communications: A Book of Selected Readings, Theodore S. Rappaport, 1995 by IEEE, Inc. [3] AN9720 Application Note, Intersil Corporation, “Calculating Maximum Processing Rates of the PDC (HSP50214B)”. [4] FO-007 Block Diagram of HSP50214. HSP50214B

47 FN4450.4 May 1, 2007 Configuration Control Word Definitions Note that in the Configuration Control Register Tables, some of the available 32-bits in a Control Word are not used. Unused bits do not need to be written to the Master Register. If the destination only has 16-bits, then only 2 bytes need to be written to the Master Register. Figure 45 details the timing for proper operation of the Microprocessor Write Section. Bits identified as “Reserved” should be programmed to a zero. NOTE: CLKIN or PROCCLK must be present to properly load control words. Note in the header which is applicable. CONTROL WORD 0: CHIP CONFIGURATION, INPUT SECTION, CIC GAIN (SYNCHRONOUS TO CLKIN) BIT POSITION FUNCTION DESCRIPTION 31-21 Reserved Reserved.

20 Carrier NCO External

0- The SYNCIN1 pin has no effect on the Carrier NCO. 1- When the SYNCIN1 pin is asserted, the carr ier center frequency and phase are updated from the holding registers to the active register. Also, if bit 0 of this word is active, the carrier phase accumulator feedback will be zeroed to set the Carrier NCO to a known phase, allowing the NCOs of multiple parts to be initialized and updated synchronously.

19 CIC External Sync

0- The SYNCIN1 pin has no effect on the CIC filter. 1- When the SYNCIN1 pin is asserted, the decim ation counter is loaded, allowing the decimation counters in multiple chips to be synchronized. When CW27 bit-22 is set to a 1, SYNCIN1 will reset both front end and back end circuitry. 18 Input Format 0- Two’s Complement Input Format. 1- Offset Binary Input Format. 17 Input Mode 0- Input operates in Gated Mode. 1- Input operates in Interpolated Mode. 16-13 CIC Shift Gain These bits control the barrel shifter at the input to the CIC filter. These bits are added to the GAINADJ(2:0) pins to determine the total shift. The sum is saturated at 15. See the CIC Decimation Filter Section for values to be programmed in this field based on CIC filter Decimation. Bit 16 is the MSB. SG = Floor [39 - (number of input bits) - 5log2(R)] for 4 < R < 31 SG = 15 for R = 4. SG = 0 for R = 32. 12-7 CIC Decimation Counter Preload These bits control the decimation in the CIC filter. Program this field to R-1, where R is the desired decimation factor in the filter. The decimation factor range is 4-32. See CIC Filter Section for effective decimation range relative to the CIC Shift Gain value. Bit 12 is the MSB. While this field allows values from 0 - 63, the valid values are in the range from 4- 32. 6 CIC Bypassed Active high, this bit routes the output of the input shifter to the output of the CIC with no filtering. When the CIC filter is bypassed, CLKIN must be at least twice the input sample rate (ENI should be toggled to achieve this). When the CIC filter is by passed, the bottom 24-bits of the barrel shifter output are routed to the halfband filters. 5-4 Number of Offset Frequency Bits 00 - 8-bits. 01 - 16. 10 - 24. 11 - 32. 3 Syncout CLK Select This bit selects whether the SYNCOUT signal is generated from CLKIN of from PROCCLK 0- CLKIN. 1- PROCLK. 2 Clear Phase Accum 0- Enable accumulator in Carrier NCO. 1- Zero feedback in accumulator.

1 Carrier NCO Offset

When set to 1, this bit enables the offset frequenc y word to be added to the center frequency Control Word. The offset is loaded serially via the COF and COFSYNC pins.

0 Carrier NCO Load

When this bit is set to 1, the μP update to the Carrier NCO frequency or an external carrier NCO load using SYNCIN1 will zero the feedback of the phase accumulator, as well as update the phase or frequency. This function can be used to set the NCO to a known phase synchronized to an external event. HSP50214B

48 FN4450.4 May 1, 2007 CONTROL WORD 1: INPUT LEVEL DETECTOR (SYNCHRONOUS TO CLKIN) BIT POSITION FUNCTION DESCRIPTION 31 Reserved Reserved. 30 Integration Mode 0- Integration of magnitude error stops when the interval counter times out. 1- Integration runs continuously. When the interval counter times out, the integrator reloads, and the results of the integration is sent to a register for the processor to read. 29-14 Integration Interval These are the top 16-bits of the 18-bit integration counter, ICPrel. ICPrel = (N)/4+1; where N is the desired integration period in CLKIN cycles, defined as the number of input samples to be integrated. N zeros must be accounted for, as they will be added to the threshold! If the gated input mode is used, the same input sample will be accumulated multiple times. 13-0 Input Threshold Input Magnitude Threshold. Bits 12-0 correspond to input bits 12-0. The magnitude of the input is added to this threshold, where the threshold is a signed number. Bit 13 is the MSB. CONTROL WORD 2: INPUT LEVEL DETECTOR START STROBE (SYNCHRONIZED TO CLKIN) BIT POSITION FUNCTION DESCRIPTION N/A Start Input Level Detector AGC Integrator Writing to this location starts/restarts the input AGC error integrator. The integrator will either restart or stop when the integration interval counter times out depending on bit 30 of Control Register 1 (see Microprocessor Write Section). CONTROL WORD 3: CARRIER NCO CENTER FREQUENCY (SYNCHRONIZED TO CLKIN) BIT POSITION FUNCTION DESCRIPTION 31-0 Carrier Center Frequency These bits control the frequency of the Carrier NCO. The frequency range of the NCO is ± fS / 2 where fS is the input sample rate. The bits are computed by the equation N = (FNCO / fS)*232. Bit 31 is the MSB. This location is a holding register. After loading, a transfer to the active register is done by writing to Control Word 5 or by generating a SYNCIN1 with Control Word 0, Bit 20 set to 1. The Carrier NCO only updates ENI is active. NOTE: In the HSP50214B, if the SYNCIN1 occurs when the NCO is not updating, the load signal is held internal to the part until the next NCO update. CONTROL WORD 4: CARRIER PHASE OFFSET (SYNCHRONIZED TO CLKIN) BIT POSITION FUNCTION DESCRIPTION 31-10 Reserved Reserved. 9-0 Carrier Phase Offset These bits, PO, are used to offset the phase of the carrier NCO. The bits are computed by the Equation PO = INT[(210φoff)/ 2π]HEX; (-π <φoff< π) for 10-bit 2’s complement representation or from 0 to 2π for 10- bit offset binary representation. Bit 9 is the MSB. This location is a holding register. After loading, a transfer to the active register is done by writing to Control Word 6 or by generating a SYNCIN1 with Control Word 0, Bit 20 set to 1. The carrier NCO only updates when ENI is active. CONTROL WORD 5: CARRIER FREQUENCY STROBE (SYNCHRONIZED TO CLKIN) BIT POSITION FUNCTION DESCRIPTION N/A Carrier Frequency Strobe Writing to this address updates the carrier frequency Control Word from the Holding Register. CONTROL WORD 6: CARRIER PHASE STROBE (SYNCHRONIZED TO CLKIN) BIT POSITION FUNCTION DESCRIPTION N/A Carrier Phase Strobe Writing to this address updates the carrier phase offset Control Word with the value written to the phase offset (PO) register. HSP50214B

49 FN4450.4 May 1, 2007 CONTROL WORD 7: HB, FIR CONFIGURATION (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-22 Reserved Reserved.

21 Enable External

0- The SYNCIN2 pin has no effect on the halfband and FIR filters. 1- When the SYNCIN2 pin is asserted, the filter control circuitry in the halfband filters, the FIR, the resampler, and the discriminator are reset. SYNCIN2 can be used to synchronize the computations of the filters in multiple parts for the alignment (see Synchronization Section).

20 Halfband (HB)

1- Bypass Halfband Filters. 0- Enable HB Filters (at least one HB must be enabled). 19 HB5 Enable 0- Disables HB number 5 (the last in the cascade). 1- Enables HB filter number 5. 18 HB4 Enable Setting this bit enables HB filter number 4. 17 HB3 Enable Setting this bit enables HB filter number 3. 16 HB2 Enable Setting this bit enables HB filter number 2. 15 HB1 Enable Setting this bit enables HB filter number 1. 14-11 FIR Decimation Load decimation from 1-16, where 0000 = 16. Bit 14 is the MSB. 0001 - 1 1001 - 9 0010 - 2 1010 - 10 0011 - 3 1011 - 11 0100 - 4 1100 - 12 0101 - 5 1101 - 13 0110 - 6 1110 - 14 0111 - 7 1111 - 15 1000 - 8 0000 - 16 10 FIR Real/Complex 0- Complex Filter. 1- Dual Real Filters. 9 FIR Sym Type 0- Odd Symmetry. 1- Even Symmetry. 8 FIR Symmetry 0- Symmetric Filters. 1- Asymmetric Filters. 7-0 FIR Taps Number of taps in the FIR filter. Range is 1 to 255, where 0000000 is invalid. CONTROL WORD 8: AGC CONFIGURATION 1 (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-30 Reserved Reserved.

29 Sync AGC Updates to

When this bit is 1, the SYNCIN2 pin loads the contents of the master registers into the AGC accumulator. 28-16 Threshold The magnitude measurement out of the cartesian to polar converter is subtracted from this value to get the gain error. A gain of 1.647 in the cartesian to polar conversion that must be taken into account when computing this threshold. These bits are weighted -22 down to 2-10. Bit 28 is the MSB. 15-12 Loop Gain 1 Mantissa Selected when AGCGNSEL = 1. These bits, MMMM, together with the exponent bits, EEEE (11-8), set the loop gain for the AGC loop. The gain adjustment per output sample is: 1.5dB (Threshold -[Magnitude * 1.6]) 0.MMMM * 2-(15 - EEEE) where magnitude ranges from 0 to 1.414 and the threshold is programmed in bits 28-16. The decimal value for the mantissa is calculated as DEC(MMMM)/16. Bit 15 is the MSB. 11-8 Loop Gain 1 Exponent Selected when AGCGNSEL = 1. These bits are EEEE. See description of bits 15-12. Bit 11 is the MSB. 7-4 Loop Gain 0 Mantissa Selected when AGCGNSEL = 0. These bits are MMMM. See description for bits 15-12. Same equations are used for Loop 0. Bit 7 is the MSB. 3-0 Loop Gain 0 Exponent Selected when AGCGNSEL = 0. These bits are EEEE. See description for bits 15-12. Same equations are used for Loop 0. Bit 3 is the MSB. HSP50214B

50 FN4450.4 May 1, 2007 CONTROL WORD 9: AGC CONFIGURATION 2 (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-28 Reserved Reserved. 27-16 Upper Limit Maximum Gain/Minimum Signal. The upper four bits are used for exponent; the remaining bits form the mantissa in the fractional offset binary: [eeeemmmmmmmm]. See the AGC Section for details. Bit 27 is eeee = Floor [log2(10GAIN dB/20)] mmmmmmmm = Floor [256(10GAIN dB/20/2eeee - 1)] 15-12 Reserved Reserved. 11-0 Lower Limit Minimum Gain/Maximum Signal. The upper four bits are used for exponent; the remaining bits form the mantissa in the fractional offset binary: [eeeemmmmmmmm]. See the AGC Section for details. Bit 11 is eeee = Floor [log2(10GAIN dB/20)] mmmmmmmm = Floor [256(10GAIN dB/20/2eeee - 1)] CONTROL WORD 10: AGC SAMPLE GAIN CONTROL STROBE (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION N/A Sample AGC Gain Level Writing to this location samples the output of the AGC loop filter to stabilize the value for μP reading. CONTROL WORD 11: TIMING NCO CONFIGURATION (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-6 Reserved Reserved.

5 Enable External

0- SYNCIN2 has no effect on the timing NCO. 1- When SYNCIN2 is asserted, the timing NCO center frequency and phase are updated with the value loaded in their holding registers. If bit 0 of this word is set to 1, the phase accumulator feedback is also zeroed. 4-3 Number of Offset Frequency Bits 00 - 8 bits. 01 - 16. 10 - 24. 11 - 32.

2 Enable Offset

0- Zero Offset Frequency to Adder. 1- Enable Offset Frequency.

1 Clear Phase

0- Enable Accumulator. 1- Zero Feedback in Accumulator.

0 Timing NCO Phase

When this bit is set to 1, the μP update to the timing NCO frequency or an external timing NCO load using SYNCIN2 will zero the feedback of the p hase accumulator as well as update the phase and frequency. This function can be used to set the NCO to a known phase synchronized to an external event. CONTROL WORD 12: TIMING NCO CENTER FREQUENCY (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-0 Timing NCO Center Frequency These bits control the frequency of the timing NC O. The frequency range of the NCO is from 0 to FRESAMP where FRESAMP is the input sample rate to the resampling filter. The bits are computed by the equation: N =(f OUT / FRESAMP)*232. Bit 31 is the MSB. This locati on is a holding register. After loading, a transfer to the Active Register is done by writing to Control Word 14 or by generating a SYNCIN2 with Control Word 11, Bit 5 set to 1. HSP50214B

51 FN4450.4 May 1, 2007 CONTROL WORD 13: TIMING PHASE OFFSET (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-8 Reserved Reserved. 7-0 Timing NCO Phase Offset These bits are used to offset the phase of the Timing NCO. The range is 0 to 1 times the resampler input period interpreted either as ± T/2 (2’s complement) or 0 to T (offset binary). Bit 7 is the MSB. This location is a holding register. After loading, a transfer to the Active Register is done by writing to Control Word 15 or by generating a SYNCIN2 with Control Word 11, Bit 5 set to 1. CONTROL WORD 14: TIMING FREQUENCY STROBE (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION N/A Timing Frequency Strobe Writing to this address updates the active timing NCO Frequency Register in the timing NCO (see Timing NCO Section). CONTROL WORD 15: TIMING PHASE STROBE (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION N/A Timing Phase Strobe Writing to this address updates the active timing NCO Phase Offset Register in the timing NCO (see Timing NCO Section). CONTROL WORD 16: RESAMPLING FILTER CONTROL (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-12 Reserved Reserved. 11-4 Re-Sampler Output Pulse Delay NOTE: These bits program the delay between output samples when interpolating. The extra outputs can be delayed from 2 to 255 clocks from the first output. A delay of 2 equals 255 clocks of delay. A delay of 0 or 1 is an invalid mode. When interpolating by 2, one extra output is generated; when interpolating by 4, 3 extra outputs are generated. Program by the equation (PROCCLK/fOUT) - 1. Bit 11 is the MSB. NOTE: If less than 5 is programmed, there will not be sufficient time to fully update the output buffer. If less than 16 is programmed, the serial output may be preempted. This means that it won’t finish and if the sync is programmed to follow the data, there may never be a sync. 3 Re-Sampler Bypass 0- Resampling Filter Enabled. A valid combination of bits 2-0 must also be selected. 1- Resampling Filter Section (including Interpolation halfband filters) is bypassed. 2-0 Filter Mode Select; 2- HB2 Enabled 1- HB1 Enabled 0- Re-Sampler Enabled 000- Not Valid. 001- Re-Sampler Enabled. 010- Halfband 1 Enabled. 011- Re-Sampler and Halfband Filter 1 Enabled. 100- Not Valid. 101- Not Valid. 110- Both Halfband Filters Enabled. 111- Re-Sampler and Both Halfband Filters Enabled. HSP50214B

52 FN4450.4 May 1, 2007 CONTROL WORD 17: DISCRIMINATOR FILTER CONTROL, DISCRIMINATOR DELAY (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-17 Reserved Reserved. 16-15 Phase Multiplier These bits program allow the phase output of the cartesian to polar converter to be multiplied by 1, 2, 4, or 8 (modulo 2π) to remove phase modulation before the frequency is measured. 00- No Shift on Phase Input to frequency discriminator. 01- Shift Phase Input to frequency discriminator up 1 (one bit), discarding the MSB and zero filling the LSB. 10- Shift Phase Input to frequency discriminator up 2 (two) bits, discarding the MSB and zero filling the LSB. 11- Shift Phase Input to frequency discriminator up 3 (three) bits, discarding the MSB and zero filling the LSB. 14 Discriminator Enable 0- Disable Discriminator. 1- Enable Discriminator. 13-11 Discriminator FIR Decimation The decimation can be programmed from 1 to 8, where 000 = decimate by 8; 001 = decimate by 1; 010 = decimate by 2; 011 = decimate by 3; 100 = decimate by 4; 101 = decimate by 5; 110 = decimate by 6; and 111 - decimate by 7. 10 FIR Symmetry Type 0- Odd Symmetry. 1- Even Symmetry. 9 FIR Symmetry 0- Symmetric. 1- Asymmetric. 8-3 Number of FIR Taps Number of FIR taps from 1 to 63, where 00000 is not valid (00001 = 1 tap, 00010 = 2 taps, etc. up to 11111 = 63 taps). Bit 8 is the MSB. 2-0 Discriminator Delay Sets the number of delays from 1 to 8 in the discriminator. Set delay ddd to delay minus 1, where 000 represents 1 delay; 001 represents 2 delays, 010 represents 3 delays, 011 represents 4 delays, 100 represents 5 delays, 101 represents 6 delays, 110 represents 7 delays, and 111 represents 8 delays. If ddd the decimal representation bits 2-0, then the discriminator a transfer function H(Z) = 1-Z-(ddd + 1). CONTROL WORD 18: TIMING ERROR PRELOADS (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-28 Reserved Reserved. 27-16 NCO Divide The Re-Sampler NCO output is divided down by the value loaded into this register plus 1. Load with a value that is one less than the desired period. Bit 27 is the MSB. 11-0 Reference Divide The reference clock is divided down by the value loaded into this register plus 1. Load with a value that is one less than the desired period. Bit 27 is the MSB. A minimum preload of “I” is required. CONTROL WORD 19: SERIAL OUTPUT ORDER (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31 Reserved Reserved. 30-28 Data Source for SEROUTA Serial Output A Source. The serial data source is selected using Table 12 (see Output Section). 27-25 Data Source for SEROUTB Serial Output B Source. The serial data source is selected using Table 12 (see Output Section). 24-21 Number of Serial Word Links in a Chain This parameter determines the number of SERSYNC pulses generated. It can be set from 1 to 7. If this parameter matches the number of serial words that are linked together to form a serial output chain, then there will be a sync pulse for every word in the serial output. In applications where a processor is receiving the serial data, it may be desirable to have a single SERSYNC pulse for the whole serial output chain, instead of a SERSYNC for each word in the data chain. The processor then parses out the various data words. As an example, if the I and Q are chained together and a single SERSYNC pulse is generated for this serial output chain, no ambiguity exists in the processor about which two data samples (one from I and one from Q) are related. 20-18 Link Following I Data The serial data word, or link, following the I data word is selected using Table 12 (see Output Section). HSP50214B

53 FN4450.4 May 1, 2007 17-15 Link Following Q Data The serial data word, or link, following the Q data word is selected using Table 12 (see Output Section). 14-12 Link Following Magnitude Data The serial data word, or link, following the MAG data word is selected using Table 12 (see Output Section). 11-9 Link Following Phase Data The serial data word, or link, following the PHAS data word is selected using Table 12 (see Output Section). 8-6 Link Following Frequency Data The serial data word, or link, following the FREQ data word is selected using Table 12 (see Output Section). 5-3 Link Following AGC Level Data The serial data word, or link, following the AGC data word is selected using Table 12 (see Output Section). 2-0 Link Following Timing Error Data The serial data word, or link, following the TIMER data word is selected using Table 12 (see Output Section). CONTROL WORD 20: BUFFER RAM, DIRECT PARALLEL, AND DIRECT SERIAL OUTPUT CONFIGURATION (SYNCHRONIZED WITH PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-26 Reserved Reserved.

25 Data Source for Least

Output LSBytes, bits (7:0), of AOUT and BOUT can provide: 0- Buffer RAM Mode Output or, 1- Parallel Direct Mode Output.

24 Buffered Output Mode

Buffered Mode Output interfaces to either: 0- 8-bit μP (address = μP ASEL(5:#); CLK = μP RAM read). 1- 16-bit μP (address = SEL(2:0); CLK = OEBL). 23-22 AOUT Direct Parallel Output Mode Data Source The data word sent by the Direct Parallel Output Mode to AOUT is: 00- I Data. (2’s complement) 01- Magnitude. (O; unsigned binary) 1X- Frequency. (2’s complement) 21-20 BOUT Direct Parallel Output Mode Data Source The data word sent by the Direct Parallel Output Mode to BOUT is: 00- Q Data (2’s complement). 01- Phase (2’s complement). 1X- Magnitude (O; unsigned binary).

19 Serial Output Sync

0- Normal Sync Mode (active high). 1- Sync Inverted (active low).

18 Serial Output Clock

0- Output Clock Inverted rising edge aligns with data transitions. 1- Output Clock Normal falling edge aligns with data transitions.

17 Serial Output Sync

0- Sync is asserted one bit time after the last bit of the serial word (Late Mode). 1- Sync is asserted one bit time prior to the first bit of the serial word (Early Mode). 16-14 Serial Out Clock Divider 000- Serial Output at PROCCLK/16. 001- Serial Output at PROCCLK/8. 010- Serial Output at PROCCLK/4. 011- Serial Output at PROCCLK/2. 1XX- Serial Output at PROCCLK rate. 13-12 I Data Serial Output Tag Bit 00- No Tag Bit. LSB of word is passed. 01- 0 Tag Bit. LSB of word is set to zero. 1X- 1 Tag Bit. LSB of word is set to one. CONTROL WORD 19: SERIAL OUTPUT ORDER (S YNCHRONIZED TO PROCCLK) (Continued) BIT POSITION FUNCTION DESCRIPTION 0 1 HSP50214B

54 FN4450.4 May 1, 2007 11-10 Q Data Serial Output Tag Bit (See I Data Serial Output Tag selection above). 9-8 Magnitude Data Serial Output Tag Bit (See I Data Serial Output Tag selection above). 7-6 Phase Data Serial Output Tag Bit (See I Data Serial Output Tag selection above). 5-4 Frequency Data Serial Output Tag Bit (See I Data Serial Output Tag selection above). 3-2 AGC Data Serial Output Tag Bit (See I Data Serial Output Tag selection above). 1-0 Timing Error Data Serial Output Tag Bit (See I Data Serial Output Tag selection above). CONTROL WORD 21: BUFFER RAM OUTPUT CONTROL REGISTER (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-16 Reserved Reserved. 15 Output Buffer Mode 0- The output buffer operates in snapshot mode. 1- The output buffer operates in FIFO mode. 14-12 FIFO Mode Depth Threshold In FIFO mode, when the FIFO depth reaches this threshold, an interrupt is generated and the READY flag is asserted. The threshold may be set from 0 to 7. Bit 14 is the MSB. The interrupt is generated when the FIFO depth reaches the threshold, as the FIFO fills. 11-4 Snapshot Mode Interval In snapshot mode, the interval between snapshots in the output sample times is determined by this 8- bit binary number, i.e. 256, (2 8), sample time counts between snapshot samples. Program this parameter to 1 less than the desired interval. Bit 11 is the MSB. 3-0 Snapshot Mode Number of Samples In snapshot mode, the number of samples stored each time the snapshot interval counter times out is equal to the decimal version of this 4-bit number. The range is 1- 8. Bit 3 is the MSB. CONTROL WORD 22: BUFFER RAM OUTPUT FIFO RESET (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION N/A FIFO reset A write to this address increments the output FIFO RAM address pointers to READ = 111 and WRITE = 000. CONTROL WORD 23: INCREMENT OUTPUT FIFO (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION N/A FIFO Strobe A write to this address increments the output FIFO/buffer to the next sample set. CONTROL WORD 24: SYNCOUT STROBE OUTPUT PIN (SYNCHRONIZED TO CLKIN OR PROCCLK DEPENDING ON PROGRAMMING IN CONTROL WORD 0) BIT POSITION FUNCTION DESCRIPTION N/A SYNCOUT Strobe A write to this address generates a one clock period wide strobe on the SYNCOUT pin that is synchronized to the clock. This strobe may be synchronized to CLKIN or PROCCLK based on the programming of bit 3 of Control Word 0. CONTROL WORD 20: BUFFER RAM, DIRECT PARALLEL, AND DIRECT SERIAL OUTPUT CONFIGURATION (SYNCHRONIZED WITH PROCCLK) (Continued) BIT POSITION FUNCTION DESCRIPTION HSP50214B

55 FN4450.4 May 1, 2007 CONTROL WORD 25: COUNTER AND ACCUMULATOR RESET (SYNCHRONIZED TO BOTH CLKIN AND PROCCLK) BIT POSITION FUNCTION DESCRIPTION N/A Counter and Accumulator Reset A write to this address initializes the counters and accumulators for testing. Items that are reset are: Carrier NCO. 1. Loads phase offset <9:0> into register to be used for adding to accumulator. 2. Enables feedback on the accumulator. CIC Filter 1. Resets the decimation counter. 2. Clears enables to CIC. 3. Clears accumulators in CIC. 4. Clears enable leaving CIC. Halfband Filters 1. Resets compute counter in Halfband control. 2. Resets read address for all Halfband Filters. 3. Resets write address for all Halfband Filters. 4. Clears input available strobe. 5. Resets Halfband control logic.

255 Tap FIR

1. Resets FIR read and write address pointers. 2. Zero’s coefficient read address. AGC Loop 1. Clears accumulator in loop filter. Re-Sampler and Interpolation Halfband Filters. 1. Resets counters for Halfband addresses for writing. 2. Resets output enable. 3. Reset controller for Re-Sampler. Timing NCO 1. Initializes counters for inserting extra pulse s when interpolating halfbands are enabled. In the HSP50214B, a configuration control word bit deter mines if a Timing NCO reset is executed. If Control Word 27, Bit 20 is set to a logic one, a reset will clear the feedback in the timing NCO phase accumulator. If Control Word 27, Bit 20 is ze ro, a reset will not clear the timing NCO phase accumulator feedback, which is how the HSP50214 operated. Discriminator 1. Resets read and write address pointers. 2. Zero’s coefficient read address. Cartesian to Polar Coordinate Counter 1. Resets Cordic counters (s tops current computation). FIFO Control 1. Resets decoder for controlling FIFO. 2. Resets write address for FIFO. 3. Clears RD and INTRRPT. 4. Resets “depth” and “full” flags. 5. Sets the empty flag. 6. Sets the read address to “7”, write address to “0”. Snapshot Control 1. Zeros the group number. 2. Load interval counter. 3. Resets write address and read address for FIFO. Output Serial Control 1. Reloads shift counter. 2. Reloads “Number of Words” counter. 3. Reloads counter for sync (for early or late). 4. Reloads counter for dividing down SERCLK. 5. In the HSP50214B, the Control Word 25 reset signal is designed such that the front end reset is 10 CLKIN periods wide and the back end reset is 10 PROCCLK periods wide. This guarantees that no enables will be caught in the pipelines. HSP50214B

56 FN4450.4 May 1, 2007 CONTROL WORD 26: LOAD AGC GAIN (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION (15:12) (11:5) (5:0) eeee - AGC Exponent mmmmmmm - AGC Mantissa 000000 - Not Used AGC LOAD. Writing to this location generates a strobe to load the AGC loop accumulator with bits (15:5) to the master registers. These bits are loaded into the MSBs of the AGC loop filter accumulator. Bits 15:12 are the exponent associated with the AGC gain shifter, while bits 11:5 are the mantissa associated with the AGC multiplier. The weighting of the AGC mantissa is 01.mmmmmmm. When considering Figure 23, the AGC Block Diagram, note the mux between the Register and the Limiter in the AGC Loop filter. The AGC LOAD controls the mux. Normally the mux would select the limiter output. When the AGC LOAD is asserted via the write command, the mux selects the Write Master Registers for data input See Table 20, Figure 45 and the associated text of the data sheet for an explanation of how data is loaded into the Master Registers for use internal to the part. Note that for the AGC LOAD only the lower 16-bits require data be valid to ensure a proper write of an AGC Value that will be loaded on write to CONTROL WORD 26. CONTROL WORD 27: TEST REGISTER (SYNCHRONIZED TO CLKIN) BIT POSITION FUNCTION DESCRIPTION 31-25 Reserved A fixed value of 0000 000 is loaded here for normal operation. 24 RAM Test Enable 0 = Normal Operation; 1 = RAM Test Enabled. The B Version includes test circuitry for the ROM and RAM blocks that was not present in the original release part. This circuitry must be disabled before loading the coefficient RAM’s. This is done by setting bit 24 to zero. Because the HSP50214 did not require a “write” to Control Word 27 and the HSP50214B does require that Control Word 27, Bit 24 be set to zero for normal operation, software that was written for the HSP50214 will require modification to work properly with the HSP50214B.

23 Input Level Detector

0 = The two LSB’s of the interpolation period preload are set to zero. 1 = The two LSB’s of the interpolation period preload are set to one.

22 SYNCIN1 Reset

0: SYNCIN1 causes only front end reset. 1: SYNCIN1 causes front end and back end resets.

21 Timing Error Input

0 = Operates as HSP50214. 1 = Corrects an error in the 4 LSB’s.

20 Timing NCO Reset

0 = Backend reset will not clear the timing NCO phase accumulator feedback. 1 = Backend reset clears the timing NCO phase accumulator. 19 - 18 Discriminator FIR Input 00 = 18-bits of delayed and subtracted (optionally shifted) phase. 01 = 18-bits of magnitude from coordinate converter. 1X = 18-bits of resampler/halfband filer I output.

17 Input Level Detector

0 = No external sync control of input end detector start/restart of integration period. 1 = SYNCIN causes the input level detector to start/restart its integration period.

16 AGC Average

0: AGC settles to mean. 1: AGC settles to median. 15 AGC Clear Inhibit When set to zero, this bit will clear the AGC loop filter accumulator on a SYNCIN2 assertion or a WRITE to CW25. When set to a one, a WRITE to CW25 will not clear the AGC loop filter accumulator.

14 Q Input to Coordinate

Converter (see bits 19 - 15) 0 = I and Q enabled to coordinate converter. I = Q input to coordinate converter is zeroed.

13 Coordinate Converter

0 = The Resampler HB filter output is routed to coordinate converter. 1 = The output of 255 tap FIR is routed to coordinate converter. 12-0 Reserved A fixed value 0 0010 0111 1000 [0278]hex is loaded here for normal operation. A fixed value 0 0010 0111 1010 [027A]hex is loaded here for setting the Sin/Cos Generator outputs to 7FFF. HSP50214B

57 FN4450.4 May 1, 2007 CONTROL WORDS 64-95: DISCRIMINATOR COEFFICIENT REGISTERS (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-10 Discriminator FIR Coefficient The discriminator FIR coefficients are 22-bit-two’s complement. If the filter is symmetric, the coefficients are loaded from the center coefficient at address 64 to the last coefficient. If the filter is asymmetric the coefficients C0 to CN are loaded with C 0 in address 64 up to 64+N, where N is number of asymmetric coefficients. CONTROL WORDS 128-255: 255 PROGRAMMABLE COEFFICIENT REGISTERS BIT POSITION FUNCTION DESCRIPTION 31-10 Programmable FIR Coefficient The programmable FIR coefficients are 22-bit-two ’s complement. If the filter is symmetric, the coefficients are loaded from the center coefficient at address 128 to the last coefficient. If the filter is asymmetric the coefficients C0 to CN are loaded with C0 in address 128 up to 128+N, where N is number of asymmetric coefficients. Real Filters are computed as: Xn-k+1 Ck1 + Xn-k+2 Ck-2 + ... XnC0), where C0 is the coefficient in address 128 and Xo is the oldest data sample. Complex filters outputs are computed as follows: Xn is the most recent data sample. k is the number of samples = number of (complex) taps. C0_re is the coefficient loaded into CW128. C0_im is the coefficient loaded into CW129. The convolution starts with the oldest data, times the last complex coefficient, and ends with the newest data, times the first complex coefficient loaded. Iout = (-Xn-k+1_q * Ck-1_im + Xn-k+1_i * Ck-1_re). + (-Xn-k+2_q * Ck-2_im + Xn-1+2_i * Ck-2_re). + ... + (-Xn_q * C0_im + Xn_i * C0_re). Qout = (Xn-k+1_i * Ck-1_im + Xn-k+1_q * Ck-1_re). + (Xn-k+2_i * Ck-2_im + Xn-1+2_q * Ck-2_re). + ... + (Xn_i * C0_im + Xn_q * C0_re). HSP50214B

58 FN4450.4 May 1, 2007 Absolute Maximum Ratings Thermal Information Operating Conditions Temperature Range Thermal Resistance (Typical, Note 4) θJA (°C/W) http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 4. θJA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Logical One Input Voltage VIH VCC = 5.25V 2.0 - V Logical Zero Input Voltage VIL VCC = 4.75V - 0.8 V Clock Input High VIHC VCC = 5.25V 3.0 - V Clock Input Low VILC VCC = 4.75V - 0.8 V Output High Voltage VOH IOH = -400μA, VCC = 4.75V 2.6 - V Output Low Voltage VOL IOL = +2.0mA, VCC = 4.75V - 0.4 V Input Leakage Current II VIN = VCC or GND, VCC = 5.25V -10 +10 μA Standby Power Supply Current ICCSB VCC = 5.25V, Outputs Not Loaded - 500 μA Output Leakage Current IO VIN = VCC or GND, VCC = 5.25V -10 +10 μA Operating Power Supply Current ICCOP CLK = PROCCLK = 52MHz, VIN = VCC or GND, VCC = 5.25V, Outputs Not Loaded - 420 mA (Note 5) Input Capacitance CIN Freq = 1MHz, VCC open, all measurements are referenced to device ground - 8 pF (Note 6)Output Capacitance COUT NOTES: 5. Power Supply current is proportional to operation frequency. Typical rating for ICCOP is 7mA/MHz. 6. Capacitance TA = +25°C, controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes. PARAMETER SYMBOL 65MHz UNITSMIN MAX CLKIN Clock Period tCP 15 - ns CLKIN High tCH 6 - ns CLKIN Low tCL 6 - ns PROCCLK Period tPCP 18 - ns PROCCLK High tPCH 7 - ns PROCCLK Low tPCL 7 - ns REFCLK Clock Frequency fRCP - PROCCLK/2 Hz REFCLK High tRCH 7 - ns REFCLK Low tRCL 7 - ns Setup Time GAINADJ(2:0), IN(13:0), ENI, COF, COFSYNC, and SYNCIN1 to CLKIN tDS 7 - ns HSP50214B

59 FN4450.4 May 1, 2007 Hold Time GAINADJ(2:0), IN(13:0), ENI, COF, COFSYNC, and SYNCIN1 from CLKIN tDH 0 - ns Setup Time AGCGNSEL, SOF, MCSYNCI, SOFSYNC, and SYNCIN2 to PROCCLK tDSS 7 - ns Hold Time AGCGNSEL, SOF, MCSYNCI, SOFSYNC, and SYNCIN2 from PROCCLK tDHS 0 - ns Setup Time, A(2:0) to Rising Edges of WR tWSA 8 - ns Setup Time, A(2:0) C(7:0) to Rising Edges of WR tWSC 10 - ns Hold Time, A(2:0) from Rising Edges of WR tWHA 2 - ns Hold Time, A(2:0) C(7:0) from Rising Edges of WR tWHC 0 - ns WR to CLKIN tWC 14 - ns (Note 9) PROCCLK to AOUT(15:0), BOUT (15:0), DATARDY, SEROUTA, SEROUTB, INTRRP tDO_OUT - 8 ns PROCCLK to SYNCOUT tDO_SYNCI - 8 ns PROCCK to MCSYNCO tDO_SYNCO - 6 ns PROCCLK to SERCLK, SERSYNC Valid tDOS - 12 ns WR High tWRH 15 - ns WR Low tWRL 8 - ns RD Low tRL 20 - ns Address Setup to Read Low tAS - 3 ns RD LOW to Data Valid tRDO - 18 ns RD HIGH to Output Disable tROD - 10 ns (Note 8) Output Enable Time tOE - 6 ns Output Enable Time - FIFO Read Mode tOEBL - 15 ns Output Disable Time tOD - 8 ns (Note 8) Output Rise, Fall Time tRF - 3 ns (Note 8) NOTES: Test VIH = 3.0V, VIHC = 4.0V, VIL = 0V. 8. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes. 9. Setup time required to ensure action initiated by WR will be seen by a particular CLKIN. PARAMETER SYMBOL 65MHz UNITSMIN MAX HSP50214B

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN4450.4 May 1, 2007 HSP50214B Metric Plastic Quad Flatpack Packages (MQFP/PQFP) D E E1 -A- PIN 1 A2 A1 A 5o-16o 5o-16o 0o-7o 0.40

0.016 MIN

L 0o MIN PLANE B 0.005/0.009 0.13/0.23WITH PLATING BASE METAL SEATING 0.005/0.007 0.13/0.17 -B- e 0.008

0.20 A-B SD SCM

0.10 0.004 -C- -D- -H- Q120.28x28 (JEDEC MO-108DA-1 ISSUE A)

120 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE

A - 0.160 - 4.07 - A2 0.125 0.144 3.17 3.67 - B 0.012 0.018 0.30 0.45 6 B1 0.012 0.016 0.30 0.40 - D 1.219 1.238 30.95 31.45 3 D1 1.098 1.106 27.90 28.10 4, 5 E 1.219 1.238 30.95 31.45 3 E1 1.098 1.106 27.90 28.10 4, 5 L 0.026 0.037 0.65 0.95 - N 120 120 7 e 0.032 BSC 0.80 BSC - Rev. 0 1/94 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and toler ances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane . 4. Dimensions D1 and E1 to be determined at datum plane 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. “N” is the number of terminal positions. -C- -H-