HSP50214AVI

HSP50214A INTERSIL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 60

Technical content

Features

• Up to 65 MSPS Front-End Processing Rates (CLKIN) and

55 MSPS (41 MSPS Using the Discriminator) Back-End

Processing Rates (PROCCLK) Clocks May Be Asynchronous

• Processing Capable of >100dB SFDR
• Up to 255-Tap Programmable FIR
• Overall Decimation Factor Ranging from 4 to 16384
• Output Samples Rates to≅12.94 MSPS with Output Band- widths to≅ 982kHz Lowpass
• 32-Bit Programmable NCO for Channel Selection and Car- rier Tracking
• Digital Resampling Filter for Symbol Tracking Loops and Incommensurate Sample-to-Output Clock Ratios
• Digital AGC with Programmable Limits and Slew Rate to Optimize Output Signal Resolution; Fixed or Auto Gain Adjust
• Serial, Parallel, and FIFO 16-Bit Output Modes
• Cartesian to Polar Converter and Frequency Discriminator for AFC Loops and Demodulation of AM, FM, FSK, and DPSK
• Input Level Detector for External I.F . AGC Support

Applications

• Single Channel Digital Software Radio Receivers
• Base Station Rx’s: AMPS, NA TDMA, GSM, and CDMA
• Compatible with HSP50210 Digital Costas Loop for PSK Reception
• Evaluation Platform Available

Description

The HSP50214A Programmable Downconverter converts dig- itized IF data into filtered baseband data which can be pro- cessed by a standard DSP microprocessor. The Programmable Downconverter (PDC) performs down conver- sion, decimation, narrowband low pass filtering, gain scaling, resampling, and Cartesian to Polar coordinate conversion. The 14-bit sampled IF input is down converted to baseband by digital mixers and a quadrature NCO, as shown in the Block Diagram. A decimating (4 to 32) fifth order Cascaded Integrator-Comb (CIC) filter can be applied to the data before it is processed by up to 5 decimate-by-2 halfband fil- ters. The halfband filters are followed by a 255-tap pro- grammable FIR filter. The output data from the programmable FIR filter is scaled by a digital AGC before being re-sampled in a polyphase FIR filter. The output sec- tion can provide seven types of data: Cartesian (I, Q), polar (R, q), filtered frequency (dq/dt), Timing Error (TE), and AGC level in either parallel or serial format. Block Diagram

Ordering Information

TEMP. RANGE ( oC) PACKAGE PKG. NO. HSP50214AVC 0 to 70 120 Ld MQFP Q120.28x28 HSP50214AVI -40 to 85 120 Ld MQFP Q120.28x28 HALFBAND POLYPHASE FIR AND FILTERS INPUT SECTION LEVEL DETECT CARRIER 5TH CARTESIAN TO OUTPUT FORMATTER DISCRIMINATOR AGC LOOP FILTER MAG. PHASE RESAMPLING I OUT Q OUT FREQ AGC TIMING ERROR IN(13:0) REFCLK SEROUTA SEROUTB AOUT(15:0) BOUT(15:0) CONTROL C(7:0) MICROPROCESSOR READ/WRITE GAIN (2:0) HALFBAND FILTERSFILTER CIC ORDER HALFBAND FILTERS POLAR COORDINATE CONVERTER HALFBAND POLYPHASE FIR AND FILTERS NCO NCOCOF SOF ADJ CLKIN PROCCLK 255-TAP FIR FILTER 255-TAP FIR FILTER 5TH FILTER CIC ORDER File Number 4449.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143| Copyright © Intersil Corporation 1999 [ /Title (HSP5 0214A /Sub- ject ( Pro- gram- mable Down- con- verter) /Autho r () /Key- words (Inter- sil Semi- con- ductor, Down- con- verter, Down Con- verter, Pro- gram- mable Down- con- verter, DSP, AMPS, TDMA , North Ameri- can OBSOLETE PR ODUCT POSSIBLE SUBSTITUTE PR ODUCT HSP50214B

120 LEAD MQFP

V CC MSYNCI GND BOUT7 BOUT6 BOUT5 GND MSYNCO GND BOUT15 BOUT14 V CC NC BOUT12 BOUT11 BOUT10 BOUT9 BOUT8 BOUT13 OEBH DATARD Y SYNCOUT INTRRP WR RD GND NC V CC NC GND SEL2 SEL1 SEL0 GND SEROUTA SEROUTB SERSYNC SER OE SERCLK VCC SYNCIN2 SYNCIN1 COF GAINADJ0 COFSYNC GND SOF SOFSYNC VCC VCC IN0 IN1 GND IN3 CLKIN GND NC ENI GAINADJ2 IN4 IN8 IN9 IN10 GND IN7 NC IN6 IN5 IN2 OEAL GND AOUT0 AOUT1 AOUT2 AOUT3 AOUT4 NC V CC AOUT5 AOUT6 AOUT7 AOUT8 AOUT9 NC GND AOUT10 AOUT11 AOUT12 IN11 AOUT13 AOUT14 AOUT15 OEAH GND REFCLK V CC AGCGNSEL IN13 IN12 GAINADJ1 HSP50214A

VCC - Positive Power Supply Voltage. GND - Ground. CLKIN I Input Clock. This clock should be a multiple of the input sample rate. All input section processing oc- curs on the rising edge of CLKIN. The frequency of CLKIN is designated fCLKIN . IN(13:0) I Input Data. The format of the input data may be set to offset binary or 2’s complement. IN13 is the MSB (see Control Word 0). ENI I Input Enable. Active Low. This pin enables the input to the part in one of two modes, gated or inter- polated (see Control Word 0). In gated mode, one sample is taken per CLKIN whenENI is asserted. The input sample rate is designated fS, which can be different from fCLKIN When ENI is used. GAINADJ(2:0) I GAINADJ Input. Adds an offset to the gain via the shifter following the mixer. GAINADJ value is added to the shift code from the microprocessor (µP) interface. The shift code is saturated to a maximum code of F . The gain is offset by (6dB)(GAINADJ); (000 = 0dB gain adjust; 111 = 42dB gain adjust) GAINADJ2 is the MSB. See “Using the Input Gain Adjust Control Signals” Section. PROCCLK I Processing Clock. PROCCLK is the clock for all processing functions following the CIC Section. Pro- cessing is performed on PROCCLK’s rising edge. All output timing is derived from this clock. NOTE: This clock may be asynchronous to CLKIN. AGCGNSEL I AGC Gain Select. This pin selects between two AGC loop gains. This input is setup and held relative to PROCCLK. Gain setting 1 is selected when AGCGNSEL = 1. COF I Carrier Offset Frequency Input. This serial input pin is used to load the carrier offset frequency into the Carrier NCO (see Serial Interface Section). The offset may be 8, 16, 24, or 32 bits. The setup and hold times are relative to CLKIN. This input is compatible with the output of the HSP50210 Costas loop [1]. COFSYNC I Carrier Offset Frequency Sync. This signal is asserted one CLK before the most significant bit (MSB) of the offset frequency word (see Serial Interface Section). The setup and hold times are relative to CLKIN. This input is compatible with the output of the HSP50210 Costas loop [1]. SOF I Re-Sampler Offset Frequency Input. This serial input pin is used to load the offset frequency into the Re-Sampler NCO (see Serial Interface Section). The offset may be 8, 16, 24, or 32 bits. The setup and hold times are relative to PROCCLK. This input is compatible with the output of the HSP50210 Costas loop [1]. SOFSYNC I Re-Sampler Offset Frequency Sync. This signal is asserted one CLK before the MSB of the offset frequency word (see Serial Interface Section). The setup and hold times are relative to PROCCLK. This input is compatible with the output of the HSP50210 Costas loop [1]. AOUT(15:0) O Parallel Output Bus A. Two parallel output modes are available on the HSP50214A. The first is called the Direct Output Port, where the source is selected through Control Word 20 (see the Microproces- sor Write Section) and comes directly from the Output MUX Section (see Output Control Section). The most significant byte of AOUT always outputs the most significant byte of the Parallel Direct Out- put Port whose data type is selected viaµP interface. AOUT15 is the MSB. In this mode, the AOUT(15:0) bus is updated as soon as data is available. DATARD Y is asserted to indicate new data. The second mode for parallel data is called the Buffer RAM Output Port. The Buffer RAM Output Port acts like a FIFO for blocks of information called data sets. Within a data set is I, Q, magnitude, phase, and frequency information; a data type is selected using SEL(2:0). Up to 7 data sets are stored in the Buffer RAM Output Port. The LSBytes of the AOUT and BOUT busses form the 16 bits for the buffered output mode and can be used for buffered mode while the MSBytes are outputting data in the direct output mode. BOUT(15:0) O Parallel Output Bus B. Two parallel output modes are available on the HSP50214A. The first is called the Direct Output Port, where the source is selected through Control Word 20 (see the Microproces- sor Write Section) and comes directly from the Output MUX Section (see Output Control Section). The most significant byte of BOUT always outputs the most significant byte of the Parallel Direct Out- put Port whose data type is selected viaµP interface. BOUT15 is the MSB. In this mode, the BOUT(15:0) bus is updated as soon as data is available. DATARD Y is asserted to indicate new data. The second mode for parallel data is called the Buffer RAM Output Port. The Buffer RAM Output Port acts like a FIFO for blocks of information called data sets. Within a data set is I, Q, magnitude, phase, and frequency information; a particular information is selected using SEL(2:0). Up to 7 data sets is stored in the Buffer RAM Output Port. The least significant byte of BOUT can be used to either output the least significant byte of the B Parallel Direct Output Port or the least significant byte of the Buffer RAM Output Port. See Output Section. HSP50214A

DATARD Y O Output Strobe Signal. Active Low. Indicates when new data from the Direct Output Port Section is available. DATARDY is asserted for one PROCCLK cycle during the first clock cycle that data is avail- able on the parallel out busses. See Output Section. OEAH I Output enable for the MSByte of the AOUT bus. Active Low. OEAL I Output enable for the LSByte of the AOUT bus. Active Low. OEBH I Output enable for the MSByte of the BOUT bus. Active Low. OEBL I Output enable for the LSByte of the BOUT bus. Active Low. SEL(2:0) I Select Address is used to choose which information in a data set from the Buffer RAM Output Port is sent to the least significant bytes of AOUT and BOUT. SEL2 is the MSB. INTRRP O Interrupt Output. Active Low. This output is asserted for 8 PROCCLK cycles when the Buffer RAM Output Port is ready for reading. SEROUTA O Serial Output Bus A Data. I, Q, magnitude, phase, frequency, timing error and AGC information can be sequenced in programmable order. See Output Section and Microprocessor Write Section. SEROUTB O Serial Output Bus B Data. Contents may be related to SEROUTA. I, Q, magnitude, phase, frequency, timing error and AGC information can be sequenced in programmable order. See Output Section and Microprocessor Write Section. SERCLK O Output Clock for Serial Data Out. Derived from PROCCLK as given by Control Word 20 in the Micro- processor Write Section. SERSYNC O Serial Output Sync Signal. Serves as serial data strobes. See Output Section and Microprocessor Write Section. SER OE I Serial Output Enable. When high, the SEROUTA, SEROUTB, SERCLK, and SERSYNC signals are set to a high impedance. C(7:0) I/O Processor Interface Data Bus. See Microprocessor Write Section. C7 is the MSB. A(2:0) I Processor Interface Address Bus. See Microprocessor Write Section. A2 is the MSB. WR I Processor Interface Write Strobe. C(7:0) is written to Control Words selected by A(2:0) in the Pro- grammable Down Converter on the rising edge of this signal. See Microprocessor Write Section. RD I Processor Interface Read Strobe. C(7:0) is read from output or status locations selected by A(2:0) in the Programmable Down Converter on the falling edge of this signal. See Microprocessor Read Section. REFCLK I Reference Clock. Used as an input clock for the timing error detector. The timing error is computed relative to REFCLK. REFCLK frequency must be less than or equal to PROCCLK/2. MSYNCO O Multiple Chip Sync Output. Provided for synchronizing multiple parts when CLKIN and PROCCLK are asynchronous. MSYNCO is the synchronization signal between the input section operating under CLKIN and the back end processing operating under PROCCLK. This output sync signal from one part is connected to the MSYNCI signal of all the HSP50214As. MSYNCI I Multiple Chip Sync Input. The MSYNCI pin of all the parts should be tied to the MSYNCO of one part. NOTE: MSYNCI must be connected to an MSYNCO signal for operation. SYNCIN1 I CIC Decimation/Carrier NCO Update Sync. Can be used to synchronize the CIC Section, carrier NCO update, or both. See the Multiple Chip Synchronization Section and Control Word 0 in the Micropro- cessor Write Section. Active High. SYNCIN2 I FIR/Timing NCO Update/AGC Gain Update Sync. Can be used to synchronize the FIR, Timing NCO update, AGC gain update, or any combination of the above. See the Multiple Chip Synchronization Section and Control Words 7, 8, and 10 in the Microprocessor Write Section. Active High. SYNCOUT O Strobe Output. This synchronization signal is generated by the µP interface for synchronizing multiple parts. Can be generated by PROCLK or CLKIN (see Control Word 0 and Control Word 24 in the Mi- croprocessor Write Section). Active High. Pin Descriptions (Continued) NAME TYPE DESCRIPTION HSP50214A

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF THE HSP50214A PROGRAMMABLE DOWNCONVERTER

to pass baseband and status data. configured through a microprocessor interface. NOTE: All of the clocks may be asynchronous. many waveforms required in the communications marketplace. tions of this table were corroborated with reference [2]. gain value at the arrival of the next user burst. pattern to aid in burst acquisition. TABLE 1. CELLULAR PHONE BASE STATION APPLICATIONS

mum detection of the GMSK signals. signals are required, such as base-stations. band and 255-tap programmable, 22-bit coefficient FIR filter. signal. AMPS is an example of an FM application. timing recovery loop filters to complete the receiver design. while preserving time resolution in the baseband data. changes in the incoming signal. TABLE 2. CELLULAR BASESTATION APPLICATIONS USING

mental in almost all of the applications. sources are used for CLKIN and PPOCCLK. still be controlled independently. ter frequency and phase offset. associated spectral results. PDC A is the Master sync through MSO. PDC A configures the PROCCLK sync through SYNCIN2. PDC B configures the CLKIN sync through SYNCIN1. FIGURE 2. SYNCHRONIZATION CIRCUIT

FIGURE 9. INPUT GATING LOGIC |X| R+ + E G R E G ACCUMULATOR CLKIN CLKIN INPUT_THRESHOLD † INTEGRATION_INTERVAL † START † INTEGRATION_MODE † IN(13:0) “0” TO µPROC ADDR(2:0) CONTINUOUS SINGLE R E G M U X COUNTER † Controlled via microprocessor interface. HSP50214A

instructions for writing Control Word 3. Section on instructions for writing Control Word 4. the signal of interest to baseband. The mixer output is rounded symmetrically to 15 bits. isters are transferred to active registers in one of two ways. Offset Holding Registers to be transferred to active registers. of the NCO synchronous with a specific event. † Controlled via microprocessor interface. FIGURE 12. BLOCK DIAGRAM OF NCO SECTION

adjusted in 6dB steps to control the CIC output level. where R is the decimation factor and N is the number of stages. maximum decimation in the CIC to 32 for a full scale input. the CIC filter is used, the value 40 replaces 39). 0 to 63, limited by the input resolution as cited above. level constant as the analog front end attenuation is changed. need for the software to continually normalize. Gain has been programmed per Equation 7 or 8A.

1. Figure 18 shows the frequency response of each of the

TABLE 3. GAIN ADJUST CONTROL AND CIC DECIMATION

Depending on the number of halfbands used, PROCCLK must operate at a minimum rate above the input sample rate, F S, to the halfband. This relationship depends on the num- ber of multiplies for each of the halfband filter stages. The fil- ter calculations take 3, 4, 5, 6, and 7 multiplies per input for HB1, HB2, HB3, HB4, and HB5 respectively. If we keep the assumption that f S is the input sampling frequency, then Equation 10 shows the minimum ratio needed. fPROCCLK /fS ≥ ([(7)(HB5)(2HB5 )+ (6)(HB4)(2(HB4 + HB5))+ (5)(HB3)(2(HB3+HB4+HB5) )+ (4)(HB2)(2(HB2+HB3+ HB4+HB5) )+ (3)(HB1)(2(HB1+HB2+HB3+HB4+HB5) )]/2T (EQ. 10)) where HB1 = 1 if this section is selected and 0 if it is bypassed; HB2 = 1 if this section is selected and 0 if it is bypassed; HB3 = 1 if this section is selected and 0 if it is bypassed; HB4 = 1 if this section is selected and 0 if it is bypassed; HB5 = 1 if this section is selected and 0 if it is bypassed; T = number of Halfband Filters Selected. The range for T is from 0 to 5. Examples of PROCCLK Rate Calculations Suppose we enable HB1, HB3, and HB5. Using Figure 16, HB1= 1, HB3 = 1, and HB5 = 1. Since stage 2 and stage 4 are not used, HB2 and HB4 = 0. PROCCLK must operate faster than (7x2+5x4+3x8)/8 = 7.25 times faster than F If all five halfbands are used, then PROCCLK must operate at (7x2+6x4+5x8+4x16+3x32)/32 = 7.4375 times faster than FS . 255-Tap Programmable FIR Filter The Programmable FIR filter can be used to implement real filters with even or odd symmetry, using up to 255 filter taps, or complex filters with up to 64 taps. The FIR filter takes advantage of symmetry in coefficients by summing data samples that share a common coefficient, prior to multiplica- tion. In this manner, two filter taps are calculated per multiply accumulate cycle. Asymmetric filters cannot share common coefficients, so only one tap per multiply accumulate cycle is calculated. The filter can be effectively bypassed by setting the coefficient C 0 = 1 and all other coefficients, CN = 0. Additionally, the Programmable FIR filter provides for deci- mation factors, R, from 1 to 16. The processing rate of the Filter Compute Engine is PROCCLK. As a result, the fre- quency of PROCCLK must exceed a minimum value to ensure that a filter calculation is complete before the result is required for output. In configurations which do not use deci- mation, one input sample period is available for filter calcula- tion before an output is required. For configurations which employ decimation, up to 16 input sample periods may be available for filter calculation. For real filter configurations, use Equation 11 to calculate the number of taps available at a given input filter sample rate. for real filters, and for complex filters, where floor is defined as the integer por- tion of a number; PROCCLK is the compute clock; F SAMP = the FIR input sample rate; R = Decimation Factor; SYM = 1 for symmetrical filter, 0 for asymmetrical filter; ODD# = 1 for an odd number of filter taps, 0 = an even number of taps. Use Equation 12 to calculate the maximum input rate. for real filters, and for complex filters, where floor[x], PROCCLK, F SAMP ,R= Decimation Factor, SYM, and ODD# are defined as in Equa- tion 11. Use Equation 13 to calculate the maximum output sample rate for both real and complex filters. The coefficients are 22 bits and are loaded using writes to Control Words 128 through 255 (see Microprocessor Write Section). For real filters, the same coefficients are used by I and Q paths. If the filter is configured as a symmetric filter using Control Word 17, Bit 9, then coefficients are loaded starting with the center coefficient in Control Word 128 and proceeding to last coefficient in Control Word 128+n. The fil- ter symmetry type can be set to even or odd symmetric, and the number of filter coefficients can be even or odd, as illus- trated in Figure 20. Note that complex filters can also be realized but are only allowed to be asymmetric. Only the coefficients that are used need to be loaded. TAPS floor PROCCLK F SAMP R⁄()⁄ R ]–[() 1 +(= (EQ. 11A) SYM) SYM() ODD#()[]– TAPS floor (PROCCLK F SAMP R⁄()⁄ R ) 2]⁄–[= (EQ. 11B) (EQ. 12A)FSAMP PROCCLK() R() R floor Taps()[[+[⁄ += SYM() ODD#() ] 1S Y M+()⁄] ] (EQ. 12B)FSAMP PROCCLK() R()[] R floor Taps() 2() ][+[]⁄= (EQ. 13)FFIR OUT FSAMP() R⁄= HSP50214A

TABLE 6A. AGC LIMIT EXPONENT vs GAIN GAIN(dB) EXPONENT MANTISSA 96.330 15 511 90.309 15 0 84.288 14 0 78.268 13 0 72.247 12 0 66.227 11 0 60.206 10 0 54.185 9 0 48.165 8 0 42.144 7 0 36.124 6 0 30.103 5 0 24.082 4 0 18.062 3 0 12.041 2 0 6.021 1 0 0.000 0 0 TABLE 6B. AGC LIMIT MANTISSA vs GAIN GAIN(dB) EXPONENT MANTISSA 6.000 0 509 5.750 0 480 5.500 0 452 5.250 0 425 5.000 0 398 4.750 0 372 4.500 0 347 4.250 0 323 4.000 0 299 3.750 0 276 3.500 0 254 3.250 0 232 3.000 0 211 2.750 0 190 2.500 0 170 2.250 0 151 2.000 0 132 1.750 0 114 1.500 0 96 1.250 0 79 1.000 0 62 0.750 0 46 0.500 0 30 0.250 0 14 0.020 0 1 TABLE 6C. AGC LIMIT DATA FORMAT CONTROL WORD 9 BIT: 27 26 25 24 23 22 21 20 19 18 17 16 FORMAT eeee m m m m m m m m HSP50214A

† Controlled via microprocessor interface. FIGURE 23. AGC BLOCK DIAGRAM

15 E LG–()–

signals than for “under range” signals (or vice versa). after an initial AGC settling period. independent of the signal level. works identically to the HSP50214. AGC loop gains to adjust the data path gain. input to the AGC Multiplier. TABLE 7. AGC LOOP GAIN BINARY MANTISSA TO GAIN TABLE 8. AGC LOOP GAIN BINARY EXPONENT TO GAIN

TABLE 9A. BIT WEIGHTING FOR AGC LOOP FEEDBACK PATH AGC ACCUM BIT POSITION GAIN ERROR INPUT GAIN ERROR BIT WEIGHT AGC LOOP FILTER GAIN (MANTISSA) AGC LOOP FILTER GAIN MULTIPLIER (OUTPUT) SHIFT = 0 SHIFT = 4 SHIFT = 8 SHIFT = 15 AGC OUTPUT AND AGC LIMITS BIT WEIGHT AGC GAIN RESOLUTION (dB) 3 1 2222 0 30 222 2 E3 4 8 29 222 2 E2 2 4 28 222 2 E1 1 2 2 7 1 2 = 2 2 2222 E0 6 2 6 1 1 = 1 1 2221 M- 1 3 2 4 9= 1 x 1 2221 M -3 0.75 2 3 8= 2 x 2 2222 M -4 0.375 2 2 7= 3 x 3 2223 M -5 0.1875 2 1 6= 4 x 4 2224 M -6 0.09375 2 0 5= 5 5 2225 M -7 0.04688 1 9 4= 6 6 2216 X -8 0.02344 18 3 = 7 7 2 2 0 . 7 -9 0.01172 1 7 2= 8 8 2218 -10 0.00586 1 6 1= 9 9 2229 -11 0.00293 15 0 = 10 10 2 1 3 10 -12 0.00146 14 11 2 0 . 4 11 -13 0.000732 13 12 2 1 5 12 -14 0.000366 12 13 2 2 6 13 -15 0.000183 11 14 1 3 7 14 -16 0.0000916 10 0 . 4 8 G -17 0.0000458 9 1 5 9 G -18 0.0000229 8 2 6 10 G -19 0.0000114 7 3 7 11 G -20 0.00000572 6 4 8 12 G -21 0.00000286 55 9 1 3 G 4 6 10 14 G 37 1 1 G G 28 1 2 G G 19 1 3 G G 01 0 1 4 G G AGC Response Max = Input(Cart/PolarGain)(Error Det Gain)(AGC Loop GainMax )(AGC Output Weighting). G = Ground = 0. AGC Response Max = (1)(1.64676)(2-0)(1)(0.75dB) ~ 1.23dB/symbol time. AGC Response Min = (1)(1.64676)(2-15)(1)(0.75dB) ~ 0.00004dB/symbol time. Thus, the expected range for the AGC rate is ~ 0.00004 to 1.23dB/symbol time. HSP50214A

TABLE 9B. PDC BIT WEIGHTING BIT WEIGHT INPUT SIN/COS MIX OUT CIC IN SHIFT = 0 CIC IN SHIFT = 15 CIC BIT WEIGHTS IIIIICCCCC CIC OUT HB DATA IN HB DATA OUT/FIR IN FIR COEF FIR MULTI/ ACC FIR OUT 0 0 0 0 S S xxxxxxxxxx 0 0 0 0 1 1 1 1 1 S S xxxxxxxxxx 1 1 1 1 0 0 2 2 2 2 S S xxxxxxxxxx 2 2 2 2 1 1 3 3 3 3 S S xxxxxxxxxx 3 3 3 3 2 2 4 4 4 4 S S xxxxxxxxxx 4 4 4 4 3 3 5 5 5 5 S S xxxxxxxxxx 5 5 5 5 4 4 6 6 6 6 S S xxxxxxxxxx 6 6 6 6 5 5 7 7 7 7 S S xxxxxxxxxx 7 7 7 7 6 6 8 8 8 8 S S xxxxxxxxxx 8 8 8 8 7 7 9 9 9 9 S S xxxxxxxxxx 9 9 9 9 8 8 10 10 10 10 S 10(S) xxxxxxxxxx 10 10 10 10 9 9 11 11 11 11 S 11 xxxxxxxxxx 11 11 11 11 10 10 12 12 12 12 S 12 xxxxxxxxxx 12 12 12 12 11 11 13 13 13 13 S 13 xxxxxxxxxx 13 13 13 13 12 12 14 14 14 S 14 xxxxxxxxxx 14 14 14 14 13 13 15 15 SRnd S 15 xxxxxxxxxx 15 15 15 15 14 14 16 16 S 16 xxxxxxxxxx 16 16 16 16 15 15 17 17 S 17 xxxxxxxxxx 17 17 17 17 16 16

18 S 18 xxxxxxxxxx 18 18 18 18 17 17

19 S 19 xxxxxxxxxx 19 19 19 19 18 18

20 S 20 xxxxxxxxxx 20 20 20 20 19 19

21 S 21 xxxxxxxxxx 21 21 21 21 20 20

22 S 22 xxxxxxxxxx 22 22 22 21 21

23 S 23 xxxxxxxxxx 23 23 23 22 22

24 S 24 xxxxx Rnd Rnd Rnd 23 23

25 25(S) 25 xxxxx SAT SAT SAT 24 24 26 26 26 xxxxx 25 Rnd 27 27 27 xxxxx 26 SAT 28 28 28 xxxxx 27 29 29 29 xxxxx 28 30 30 30 xxxxx 29 31 31 31 xxxxx 30 32 32 32 xx 31 33 33 33 xx 32 34 34 34 xx (Rnd Out of Mult.) 35 35 35 xx 36 36 36 x 37 37 37 x 38 38 38 x 39 39 39 x NOTES: 1. SRnd = Symmetric Round; Rnd = Round; SAT = Saturation. 2. The NBW out of the CIC filter is 0.5 x F SOUT . If the NBWIN =F S/4 and NBWOUT = FSOUT /2, then the processing gain for a decimation x 16 CIC should be ~ 8 (9dB or 1.5 bits) versus A/D noise, the processing gain should be 10log (BWIN/BW OUT ). HSP50214A

ing by decimating down and interpolating back up. filter process described in the Re-sampler Filter Section. TABLE 10. POLYPHASE AND INTERPOLATING HALFBAND

1 Halfband Filter

2 Halfband Filters

1 Halfband Filter 7 55/7

2 Halfband Filters 17 55/17

1. This frequency is set by the Resampler NCO.

FIGURE 25. GENERATING DATA READY PULSES FOR OUTPUT

0 BYPASS

and phase of the I/Q vector. The I and Q inputs are 18 bits. sion gain is 1.64676. The magnitude resolution is 16 bits. 16 bits output from the PDC. stage, either the output formatter or frequency discriminator. always be worse than the Cartesian to Polar conversion. FIR filter to be routed directly to the coordinate converter. phase, and frequency computations. still routed to the discriminator. TABLE 11. MAG/PHASE BIT WEIGHTING FIGURE 28. PHASE BIT MAPPING OF COORDINATE TABLE 12. MAG/PHASE ACCURACY vs CLOCK CYCLES

Control Word 27, Bit 13 to a logic zero. by 4, and a multiply of 23 reduces the range by 8. 2) 18 bits of magnitude from the coordinate converter block. to provide for processing SSB signals. 00 Item (1) described above. 01 Item (2) described above. 1X Item (3) described above. 0 I and Q enabled to the I/Q to R/Theta block. 1 The Q input to the I/Q to R/Theta block is zeroed.

1 The data ready strobe from the coordinate con-

2 The data ready strobe from the coordinate con-

† Controlled via microprocessor interface. FIGURE 29. FREQUENCY DISCRIMINATOR BLOCK DIAGRAM

AGC output data ready signal. when the resampler/halfband filters are enabled. the frequency discriminator. controller and the Programmable Down Converter are ready. 8-bit processor interface or a 16-bit processor interface. DATARD Y is asserted can be different. output transitions at the discriminator FIR filter output rate. † Controlled via microprocessor interface. FIGURE 30. PARALLEL OUTPUT BLOCK DIAGRAM

identical number of words in the serial output streams. while the remaining signals are 2’s complement format. output using the Serial Output mode. TABLE 13. LINKING CONTROL WORDS FOR SERIAL OUTPUT

000 I Data

001 Q Data

010 Magnitude (MAG) Data

011 Phase (PHAS) Data

100 Frequency (FREQ) Data

101 Timing Error (TIMER) Data

110 AGC Gain

111 Zeros

FIGURE 34. SERIAL OUTPUT FORMATTER BLOCK DIAGRAM

010 MAG

011 PHASE

100 FREQUENCY

101 TIMING ERROR

110 AGC

illustrates how Control Word 19 should be programmed. nize to the serial data stream. TABLE 14. EXAMPLE 1 SERIAL OUTPUT CONTROL SETTINGS TABLE 15. EXAMPLE 2 SERIAL OUTPUT CONTROL SETTINGS

RAM controller supports both FIFO and Snapshot modes. that the RAM is ready to be read. nals are defined in Table 18. TABLE 16. RAM DATA STORAGE MAP sample time until a new value appears at the filter output. TABLE 17. BUFFER RAM OUTPUT SELECT DEFINITIONS

010 Magnitude

101 Unused

110 Memory Status

111 Reading this address increments to the next

FIGURE 37. 16-BIT MICROPROCESSOR INTERFACE

NOTE: In the Status output, BOUT(7:0) are all GND. pointer has already been incremented into a sample. Figure 39 showsINTRRP going low before the FIFO is read. FIFO must be monitored by the user via a status read. buffer has sufficient data to be read. same address (the circuitry will not allow this). are read or the FIFO is reset). TABLE 18. STATUS BIT DEFINITIONS are the current depth of the FIFO.

4 EMPTY - When in FIFO mode, the FIFO is

3 FULL - When in FIFO mode, the FIFO is full,

and new samples will not be written.

2 READYB - When in FIFO mode, the output buff-

of samples have been taken. Active Low. FIGURE 38. INTERFACE BETWEEN A 16-BIT MICROPROCES-

8 CLKS

FIGURE 39. TIMING DIAGRAM FOR PDC IN FIFO MODE WITH

Rule #4: Y ou cannot write over what you have not read. and Read address pointer = 111. is generated when the depth increments past the threshold. number of samples in the FIFO must be monitored by the user. FIGURE 40. FIFO REGISTER OPERATION

FIGURE 41. 8-BIT MICROPROCESSOR INTERFACE BUFFER RAM MODE BLOCK DIAGRAM

000000 RAM I LSB

000001 RAM I MSB

000010 RAM Q LSB

000011 RAM Q MSB

001000 RAM |r| LSB

001001 RAM |r| MSB

001010 R A M φ LSB

001011 R A M φ MSB

010000 R A M ƒ LSB

010001 R A M ƒ MSB

100000 INPUT INTEG LSB

100001 INPUT INTEG NMSB

100010 INPUT INTEG MSB

101000 AGC LSB

101001 AGC MSB

101010 TIMING LSB

101011 TIMING MSB

FIGURE 42. RAM LOAD SEQUENCE

Composite Filter Response Example For this example consider a total receive band roughly 25MHz wide containing 124 200kHz wide FDM channels as shown in Figure 44. The design goal for the PDC is to tune to and filter out a single 200kHz FDM channel from the FDM band, passing only baseband samples onto the baseband processor at a multiple of the 270.8 KBPS bit rate. RF/IF Considerations The input frequency to the PDC is dependent on the A/D converter selected, the RF/IF frequency, the bandwidth of interest and the sample rate of the converter. If the A/D con- verter has sufficient bandwidth, then undersampling tech- niques can be used to downconvert IF/RF frequencies as part of the digitizing process, using the PDC to process a lower frequency alias of the input signal. For example, a 70MHz IF can be sampled at 40MHz and the resulting 10MHz signal alias can be processed by the PDC to perform the desired downconversion/tuning and filtering. If the IF signal is less than 1/2 the sample frequency then stan- dard oversampling techniques can be used to process the signal. Of the two techniques, only undersampling allows part of the down conversion function to be brought into the digital domain just through sampling, assuming that a sam- pling frequency can be found that keeps the alias signals low and that the A/D converter has the bandwidth to accept the unconverted analog signal. TABLE 22. DEFINITION OF ADDRESS MAP

0 Buffer

1 Buffer

2 Buffered

3 Not Used

4 Input Level

5 AGC Data

the linear control mantissa. 010- Timing error LSB, not stabilized. 011- Timing error MSB, not stabilized.

6 Not Used

7 Not Used

FIGURE 47. RECEIVE SIGNAL FREQUENCY SPECTRUM

124 CHANNELS

PDC Configuration For this example, the PDC is configured as follows: s = 541.667kHz The basis for this configuration is: Sampling Rate: Select a high rate PROCCLK Output Rate:1.083MHz (4x Bit Rate; 8x Baud Rate) CIC Filtering: Primarily Rate Reduction (39/18 = 2.166MHz). HB Filtering:Flat passband with rate reduction by 4 - low enough (541.66kHz) for sufficient FIR Taps to be used. FIR Filtering:Primary shaping filter/set final out of band suppression. Polyphase/HalfBand Filtering:Interpolate by two to output 8x baud rate or 4x bit rate. The CIC and halfband filter responses are shown in Figures 48A and B. The composite filter response, constrained primarily by half- band filter 5 and the FIR filter, are shown in Figure 45. For a more detailed discussion of design approaches and trades when designing with the PDC, refer to AN9720 [3], “Calculating the Maximum Processing Rates of the PDC”. References For Intersil documents available on the web, see http://www.intersil.com/ Intersil AnswerFAX (407) 724-7800. [1]HSP50210 Data Sheet,Intersil Corporation, AnswerFAX Doc. No. 3652. [2]Cellular Radio and Personal Communications: A Book of Selected Readings, Theodore S. Rappaport, 1995 by IEEE, Inc. [3]AN9720 Application Note,Intersil Corporation, “Calcu- lating Maximum Processing Rates of the PDC (HSP50214A)”, AnswerFAX Doc. No. 99720. [4] FO-007 Block Diagram of HSP50214. HSP50214A

Configuration Control Word Definitions Note that in the Configuration Control Register Tables, some of the available 32 bits in a Control Word are not used. Unused bits do not need to be written to the Master Register. If the destination only has 16 bits, then only 2 bytes need to be written to the Master Register. Figure 45 details the timing for proper operation of the Microprocessor Write Section. Bits identified as “Reserved” should be programmed to a zero. CONTROL WORD 0: CHIP CONFIGURATION, INPUT SECTION, CIC GAIN (SYNCHRONOUS TO CLKIN) BIT POSITION FUNCTION DESCRIPTION 31-21 Reserved Reserved.

20 Carrier NCO External

0- The SYNCIN1 pin has no effect on the Carrier NCO. 1- When the SYNCIN1 pin is asserted, the carrier center frequency and phase are updated from the holding registers to the active register. Also, if bit 0 of this word is active, the carrier phase accumulator feedback will be zeroed to set the Carrier NCO to a known phase, allowing the NCOs of multiple parts to be initialized and updated synchronously.

19 CIC External Sync

0- The SYNCIN1 pin has no effect on the CIC filter. 1- When the SYNCIN1 pin is asserted, the decimation counter is loaded, allowing the decimation counters in multiple chips to be synchronized. When CW27 bit-22 is set to a 1, SYNCIN1 will re- set both front end and back end circuitry. 18 Input Format 0- Two’s Complement Input Format. 1- Offset Binary Input Format. 17 Input Mode 0- Input operates in Gated Mode. 1- Input operates in Interpolated Mode. 16-13 CIC Shift Gain These bits control the barrel shifter at the input to the CIC filter. These bits are added to the GAINADJ(2:0) pins to determine the total shift. The sum is saturated at 15. See the CIC Decima- tion Filter Section for values to be programmed in this field based on CIC filter decimation. Bit 16 is the MSB. SG = Floor [39 - (number of input bits) - 5log 2(R)] for 4 < R < 31 SG = 15 for R = 4. SG = 0 for R = 32. 12-7 CIC Decimation Counter Preload These bits control the decimation in the CIC filter. Program this field to R-1, where R is the de- sired decimation factor in the filter. The decimation factor range is 4-32. See CIC Filter Section for effective decimation factor range relative to the CIC Shift Gain value. Bit 12 is the MSB. While this field allows values from 0 - 63, the valid values are in the range from 4- 32. 6 CIC Bypassed Active high, this bit routes the output of the input shifter to the output of the CIC with no filtering. When the CIC filter is bypassed, CLKIN must be at least twice the input sample rate (ENI should be toggled to achieve this). When the CIC filter is bypassed, the bottom 24 bits of the barrel shifter output are routed to the halfband filters. 5-4 Number of Offset Frequency Bits 00 - 8 bits. 01 - 16. 10 - 24. 11 - 32. 3 Syncout CLK Select This bit selects whether the SYNCOUT signal is generated from CLKIN of from PROCCLK 0- CLKIN. 1- PROCLK. 2 Clear Phase Accum 0- Enable accumulator in Carrier NCO. 1- Zero feedback in accumulator.

1 Carrier NCO Offset

When set to 1, this bit enables the offset frequency word to be added to the center frequency Control Word. The offset is loaded serially via the COF and COFSYNC pins.

0 Carrier NCO Load

When this bit is set to 1, theµP update to the Carrier NCO frequency or an external carrier NCO load using SYNCIN1 will zero the feedback of the phase accumulator, as well as update the phase or frequency. This function can be used to set the NCO to a known phase synchronized to an external event. HSP50214A

CONTROL WORD 1: INPUT LEVEL DETECTOR (SYNCHRONOUS TO CLKIN) BIT POSITION FUNCTION DESCRIPTION 31 Reserved Reserved. 30 Integration Mode 0- Integration of magnitude error stops when the interval counter times out. 1- Integration runs continuously. When the interval counter times out, the integrator reloads, and the results of the integration is sent to a register for the processor to read. 29-14 Integration Interval These are the top 16 bits of the 18-bit integration counter, ICPrel. ICPrel = (N)/4+1; where N is the desired integration period in CLKIN cycles, defined as the number of input samples to be 18]. Bit 29 is the MSB. If the input is interpolated, then the zeros must be accounted for, as they will be added to the threshold! If the gated input mode is used, the same input sample will be accumulated multiple times. 13-0 Input Threshold Input Magnitude Threshold. Bits 12-0 correspond to input bits 12-0. The magnitude of the input is added to this threshold, where the threshold is a signed number. Bit 13 is the MSB. CONTROL WORD 2: INPUT LEVEL DETECTOR START STROBE (SYNCHRONIZED TO CLKIN) BIT POSITION FUNCTION DESCRIPTION N/A Start Input Level Detector AGC Integrator Writing to this location starts/restarts the input AGC error integrator. The integrator will either restart or stop when the integration interval counter times out depending on bit 30 of Control Register 1 (see Microprocessor Write Section). CONTROL WORD 3: CARRIER NCO CENTER FREQUENCY (SYNCHRONIZED TO CLKIN) BIT POSITION FUNCTION DESCRIPTION 31-0 Carrier Center Frequency These bits control the frequency of the Carrier NCO. The frequency range of the NCO is± F S/2 where fS is the input sample rate. The bits are computed by the equation N = (FNCO /FS)*232. Bit 31 is the MSB. This location is a holding register. After loading, a transfer to the active reg- ister is done by writing to Control Word 5 or by generating a SYNCIN1 with Control Word 0, Bit 20 set to 1. The Carrier NCO only updates when ENI is active. NOTE: In the HSP50214A, if the SYNCIN1 occurs when the NCO is not updating, the load signal is held internal to the part until the next NCO update. CONTROL WORD 4: CARRIER PHASE OFFSET (SYNCHRONIZED TO CLKIN) BIT POSITION FUNCTION DESCRIPTION 31-10 Reserved Reserved. 9-0 Carrier Phase Offset These bits, PO, are used to offset the phase of the carrier NCO. The bits are computed by the Equation PO = INT[(210φoff)/ 2π]HEX ;( -π <φoff< π) for 10-bit 2’s complement representation or from 0 to 2π for 10-bit offset binary representation. Bit 9 is the MSB. This location is a holding register. After loading, a transfer to the active register is done by writing to Control Word 6 or by generating a SYNCIN1 with Control Word 0, Bit 20 set to 1. CONTROL WORD 5: CARRIER FREQUENCY STROBE (SYNCHRONIZED TO CLKIN) BIT POSITION FUNCTION DESCRIPTION N/A Carrier Frequency Strobe Writing to this address updates the carrier frequency Control Word from the Holding Register. CONTROL WORD 6: CARRIER PHASE STROBE (SYNCHRONIZED TO CLKIN) BIT POSITION FUNCTION DESCRIPTION N/A Carrier Phase Strobe Writing to this address updates the carrier phase offset Control Word with the value written to the phase offset (PO) register. HSP50214A

CONTROL WORD 7: HB, FIR CONFIGURATION (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-22 Reserved Reserved.

21 Enable External

0- The SYNCIN2 pin has no effect on the halfband and FIR filters. 1- When the SYNCIN2 pin is asserted, the filter control circuitry in the halfband filters, the FIR, the resampler, and the discriminator are reset. SYNCIN2 can be used to synchronize the com- putations of the filters in multiple parts for the alignment (see Synchronization Section).

20 Halfband (HB)

1- Bypass Halfband Filters. 0- Enable HB Filters (at least one HB must be enabled). 19 HB5 Enable 0- Disables HB number 5 (the last in the cascade). 1- Enables HB filter number 5. 18 HB4 Enable Setting this bit enables HB filter number 4. 17 HB3 Enable Setting this bit enables HB filter number 3. 16 HB2 Enable Setting this bit enables HB filter number 2. 15 HB1 Enable Setting this bit enables HB filter number 1. 14-11 FIR Decimation Load decimation from 1-16, where 0000 = 16. Bit 14 is the MSB. 10 FIR Real/Complex 0- Complex Filter. 1- Dual Real Filters. 9 FIR Sym Type 0- Odd Symmetry. 1- Even Symmetry. 8 FIR Symmetry 0- Symmetric Filters. 1- Asymmetric Filters. 7-0 FIR Taps Number of taps in the FIR filter. Range is 1 to 255, where 0000000 is invalid. CONTROL WORD 8: AGC CONFIGURATION 1 (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-30 Reserved Reserved.

29 Sync AGC Updates

When this bit is 1, the SYNCIN2 pin loads the contents of the master registers into the AGC accumulator. 28-16 Threshold The magnitude measurement out of the cartesian to polar converter is subtracted from this val- ue to get the gain error. A gain of 1.647 in the cartesian to polar conversion that must be taken into account when computing this threshold. These bits are weighted -2 2 down to 2-10. Bit 28 is the MSB. 15-12 Loop Gain 1 Mantissa Selected when AGCGNSEL = 1. These bits, MMMM, together with the exponent bits, EEEE (11-8), set the loop gain for the AGC loop. The gain adjustment per output sample is: 1.5dB (Threshold -[Magnitude * 1.6]) 0.MMMM * 2 -(15 - EEEE)where magnitude ranges from 0 to 1.414 and the threshold is programmed in bits 28-16. The decimal value for the mantissa is calculated as DEC(MMMM)/16. Bit 15 is the MSB. 11-8 Loop Gain 1 Exponent Selected when AGCGNSEL = 1. These bits are EEEE. See description of bits 15-12. Bit 11 is the MSB. 7-4 Loop Gain 0 Mantissa Selected when AGCGNSEL = 0. These bits are MMMM. See description for bits 15-12. Same equations are used for Loop 0. Bit 7 is the MSB. 3-0 Loop Gain 0 Exponent Selected when AGCGNSEL = 0. These bits are EEEE. See description for bits 15-12. Same equations are used for Loop 0. Bit 3 is the MSB. HSP50214A

CONTROL WORD 9: AGC CONFIGURATION 2 (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-28 Reserved Reserved. 27-16 Upper Limit Maximum Gain/Minimum Signal. The upper four bits are used for exponent; the remaining bits form the mantissa in the fractional offset binary: [eeeemmmmmmmm]. See the AGC Section for details. Bit 27 is the MSB. The gain is in dB. G = (6.02)(eeee) + 20log 10(1.0 + 0.mmmmmmmm) eeee = Floor [log2(10GAIN dB/20)] mmmmmmmm = Floor [512(10 GAIN dB/20/2eeee - 1)] 15-12 Reserved Reserved. 11-0 Lower Limit Minimum Gain/Maximum Signal. The upper four bits are used for exponent; the remaining bits form the mantissa in the fractional offset binary: [eeeemmmmmmmm]. See the AGC Section for details. Bit 11 is the MSB. The gain is in dB. G = (6.02)(eeee) + 20log 10(1.0 + 0.mmmmmmmm) eeee = Floor [log2(10GAIN dB/20)] mmmmmmmm = Floor [512(10 GAIN dB/20/2eeee - 1)] CONTROL WORD 10: AGC SAMPLE GAIN CONTROL STROBE (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION N/A Sample AGC Gain Level Writing to this location samples the output of the AGC loop filter to stabilize the value forµP reading. CONTROL WORD 11: TIMING NCO CONFIGURATION (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-6 Reserved Reserved.

5 Enable External

0- SYNCIN2 has no effect on the timing NCO. 1- When SYNCIN2 is asserted, the timing NCO center frequency and phase are updated with the value loaded in their holding registers. If bit 0 of this word is set to 1, the phase accumulator feedback is also zeroed. 4-3 Number of Offset Frequency Bits 00 - 8 bits. 01 - 16. 10 - 24. 11 - 32.

2 Enable Offset

0- Zero Offset Frequency to Adder. 1- Enable Offset Frequency.

1 Clear Phase

0- Enable Accumulator. 1- Zero Feedback in Accumulator.

0 Timing NCO Phase

When this bit is set to 1, theµP update to the timing NCO frequency or an external timing NCO load using SYNCIN2 will zero the feedback of the phase accumulator as well as update the phase and frequency. This function can be used to set the NCO to a known phase synchronized to an external event. CONTROL WORD 12: TIMING NCO CENTER FREQUENCY (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-0 Timing NCO Center Frequency These bits control the frequency of the timing NCO. The frequency range of the NCO is from 0 to F RESAMP where FRESAMP is the input sample rate to the resampling filter. The bits are com- puted by the equation: N =(fOUT /FRESAMP )*232. Bit 31 is the MSB. This location is a holding register. After loading, a transfer to the Active Register is done by writing to Control Word 14 or by generating a SYNCIN2 with Control Word 11, Bit 5 set to 1. HSP50214A

CONTROL WORD 13: TIMING PHASE OFFSET (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-8 Reserved Reserved. 7-0 Timing NCO Phase Offset These bits are used to offset the phase of the Timing NCO. The range is 0 to 1 times the resa- mpler input period interpreted either as± T/2 (2’s complement) or 0 to T (offset binary). Bit 7 is the MSB. This location is a holding register. After loading, a transfer to the Active Register is done by writing to Control Word 15 or by generating a SYNCIN2 with Control Word 11, Bit 5 set to 1. CONTROL WORD 14: TIMING FREQUENCY STROBE (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION N/A Timing Frequency Strobe Writing to this address updates the active timing NCO Frequency Register in the timing NCO (see Timing NCO Section). CONTROL WORD 15: TIMING PHASE STROBE (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION N/A Timing Phase Strobe Writing to this address updates the active timing NCO Phase Offset Register in the timing NCO (see Timing NCO Section). CONTROL WORD 16: RESAMPLING FILTER CONTROL (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-12 Reserved Reserved. 11-4 Re-Sampler Output Pulse Delay NOTE: These bits program the delay between output samples when interpolating. The extra out- puts can be delayed from 2 to 255 clocks from the first output. A delay of 2 equals 255 clocks of delay. A delay of 0 or 1 is an invalid mode. When interpolating by 2, one extra output is generated; when interpolating by 4, 3 extra outputs are generated. Program by the equation (PROCCLK/f OUT ) - 1. Bit 11 is the MSB. NOTE: If less than 5 is programmed, there will not be sufficient time to fully update the out- put buffer. If less than 16 is programmed, the serial output may be preempted. This means that it won’t finish and if the sync is programmed to follow the data, there may never be a sync. 3 Re-Sampler Bypass 0- Resampling Filter Enabled. A valid combination of bits 2-0 must also be selected. 1- Resampling Filter Section (including Interpolation halfband filters) is bypassed. 2-0 Filter Mode Select; 2- HB2 Enabled 1- HB1 Enabled 0- Re-Sampler Enabled 000- Not Valid. 001- Resampler Enabled. 010- Halfband 1 Enabled. 011- Resampler and Halfband Filter 1 Enabled. 100- Not Valid. 101- Not Valid. 110- Both Halfband Filters Enabled. 111- Resampler and Both Halfband Filters Enabled. HSP50214A

CONTROL WORD 17: DISCRIMINATOR FILTER CONTROL, DISCRIMINATOR DELAY (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-17 Reserved Reserved. 16-15 Phase Multiplier These bits program allow the phase output of the cartesian to polar converter to be multiplied by 1, 2, 4, or 8 (modulo 2π) to remove phase modulation before the frequency is measured. 00- No Shift on Phase Input to frequency discriminator. 01- Shift Phase Input to frequency discriminator up 1 (one bit), discarding the MSB and zero filling the LSB. 10- Shift Phase Input to frequency discriminator up 2 (two) bits, discarding the MSB and zero filling the LSB. 11- Shift Phase Input to frequency discriminator up 3 (three) bits, discarding the MSB and zero filling the LSB. 14 Discriminator Enable 0- Disable Discriminator. 1- Enable Discriminator. 13-11 Discriminator FIR Decimation The decimation can be programmed from 1 to 8, where 000 = decimate by 8; 001 = decimate by 1; 010 = decimate by 2; 011 = decimate by 3; 100 = decimate by 4; 101 = decimate by 5; 110 = decimate by 6; and 111 - decimate by 7. 10 FIR Symmetry Type 0- Odd Symmetry. 1- Even Symmetry. 9 FIR Symmetry 0- Symmetric. 1- Asymmetric. 8-3 Number of FIR Taps Number of FIR taps from 1 to 63, where 00000 is not valid (00001 = 1 tap, 00010 = 2 taps, etc. up to 11111 = 63 taps). Bit 8 is the MSB. 2-0 Discriminator Delay Sets the number of delays from 1 to 8 in the discriminator. Set delay ddd to delay minus 1, where 000 represents 1 delay; 001 represents 2 delays, 010 represents 3 delays, 011 repre- sents 4 delays, 100 represents 5 delays, 101 represents 6 delays, 110 represents 7 delays, and 111 represents 8 delays. If ddd the decimal representation bits 2-0, then the discriminator a transfer function H(Z) = 1-Z -(ddd + 1). CONTROL WORD 18: TIMING ERROR PRELOADS (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-28 Reserved Reserved. 27-16 NCO Divide The Re-Sampler NCO output is divided down by the value loaded into this register plus 1. Load with a value that is one less than the desired period. Bit 27 is the MSB. 11-0 Reference Divide The reference clock is divided down by the value loaded into this register plus 1. Load with a value that is one less than the desired period. Bit 27 is the MSB. A minimum preload of “I” is required. CONTROL WORD 19: SERIAL OUTPUT ORDER (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31 Reserved Reserved. 30-28 Data Source for SEROUTA Serial Output A Source. The serial data source is selected using Table 12 (see Output Section). 27-25 Data Source for SEROUTB Serial Output B Source. The serial data source is selected using Table 12 (see Output Section). 24-21 Number of Serial Word Links in a Chain This parameter determines the number of SERSYNC pulses generated. It can be set from 1 to 7. If this parameter matches the number of serial words that are linked together to form a serial output chain, then there will be a sync pulse for every word in the serial output. In applications where a processor is receiving the serial data, it may be desirable to have a single SERSYNC pulse for the whole serial output chain, instead of a SERSYNC for each word in the data chain. The processor then parses out the various data words. As an example, if the I and Q are chained together and a single SERSYNC pulse is generated for this serial output chain, no am- biguity exists in the processor about which two data samples (one from I and one from Q) are related. HSP50214A

20-18 Link Following I Data The serial data word, or link, following the I data word is selected using Table 12 (see Output Section). 17-15 Link Following Q Data The serial data word, or link, following the Q data word is selected using Table 12 (see Output Section). 14-12 Link Following Magnitude Data The serial data word, or link, following the MAG data word is selected using Table 12 (see Output Section). 11-9 Link Following Phase Data The serial data word, or link, following the PHAS data word is selected using Table 12 (see Output Section). 8-6 Link Following Frequency Data The serial data word, or link, following the FREQ data word is selected using Table 12 (see Output Section). 5-3 Link Following AGC Level Data The serial data word, or link, following the AGC data word is selected using Table 12 (see Output Section). 2-0 Link Following Timing Error Data The serial data word, or link, following the TIMER data word is selected using Table 12 (see Output Section). CONTROL WORD 20: BUFFER RAM, DIRECT PARALLEL, AND DIRECT SERIAL OUTPUT CONFIGURATION (SYNCHRONIZED WITH PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-26 Reserved Reserved.

25 Data Source for

Output LSBytes, bits (7:0), of AOUT and BOUT can provide: 0- Buffer RAM Mode Output or, 1- Parallel Direct Mode Output.

24 Buffered Output

Buffered Mode Output interfaces to either: 0- 8-bitµP (address =µP ASEL(5:#); CLK =µP RAM read). 1- 16-bitµP (address = SEL(2:0); CLK = OEBL). 23-22 AOUT Direct Parallel Output Mode Data Source The data word sent by the Direct Parallel Output Mode to AOUT is: 00- I Data. 01- Magnitude. 1X- Frequency. 21-20 BOUT Direct Parallel Output Mode Data Source The data word sent by the Direct Parallel Output Mode to BOUT is: 00- Q Data. 01- Phase. 1X- Magnitude.

19 Serial Output Sync

0- Normal Sync Mode (active high). 1- Sync Inverted (active low).

18 Serial Output Clock

0- Output Clock Inverted rising edge aligns with data transitions. 1- Output Clock Normal falling edge aligns with data transitions.

17 Serial Output Sync

0- Sync is asserted one bit time after the last bit of the serial word (Late Mode). 1- Sync is asserted one bit time prior to the first bit of the serial word (Early Mode). 16-14 Serial Out Clock Divider 000- Serial Output at PROCCLK/16. 001- Serial Output at PROCCLK/8. 010- Serial Output at PROCCLK/4. 011- Serial Output at PROCCLK/2. 1XX- Serial Output at PROCCLK rate. 13-12 I Data Serial Output Tag Bit 00- No Tag Bit. LSB of word is passed. 01- 0 Tag Bit. LSB of word is set to zero. 1X- 1 Tag Bit. LSB of word is set to one. CONTROL WORD 19: SERIAL OUTPUT ORDER (SYNCHRONIZED TO PROCCLK) (Continued) BIT POSITION FUNCTION DESCRIPTION 0 1 HSP50214A

11-10 Q Data Serial Output Tag Bit (See I Data Serial Output Tag selection above). 9-8 Magnitude Data Se- rial Output Tag Bit (See I Data Serial Output Tag selection above). 7-6 Phase Data Serial Output Tag Bit (See I Data Serial Output Tag selection above). 5-4 Frequency Data Se- rial Output Tag Bit (See I Data Serial Output Tag selection above). 3-2 AGC Data Serial Output Tag Bit (See I Data Serial Output Tag selection above). 1-0 Timing Error Data Serial Output Tag Bit (See I Data Serial Output Tag selection above). CONTROL WORD 21: BUFFER RAM OUTPUT CONTROL REGISTER (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-16 Reserved Reserved. 15 Output Buffer Mode 0- The output buffer operates in snapshot mode. 1- The output buffer operates in FIFO mode. 14-12 FIFO Mode Depth Threshold In FIFO mode, when the FIFO depth reaches this threshold, an interrupt is generated and the READY flag is asserted. The threshold may be set from 0 to 7. Bit 14 is the MSB. The interrupt is generated when the FIFO depth reaches the threshold, as the FIFO fills. 11-4 Snapshot Mode Interval In snapshot mode, the interval between snapshots in the output sample times is determined by this 8-bit binary number, i.e. 256, (2 8), sample time counts between snapshot samples. Program this parameter to 1 less than the desired interval. Bit 11 is the MSB. 3-0 Snapshot Mode Number of Samples In snapshot mode, the number of samples stored each time the snapshot interval counter times out is equal to the decimal version of this 4-bit number. The range is 1- 8. Bit 3 is the MSB. CONTROL WORD 22: BUFFER RAM OUTPUT FIFO RESET (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION N/A FIFO reset A write to this address increments the output FIFO RAM address pointers to READ = 111 and WRITE = 000. CONTROL WORD 23: INCREMENT OUTPUT FIFO (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION N/A FIFO Strobe A write to this address increments the output FIFO/buffer to the next sample set. CONTROL WORD 24: SYNCOUT STROBE OUTPUT PIN (SYNCHRONIZED TO CLKIN OR PROCCLK DEPENDING ON PROGRAMMING IN CONTROL WORD 0) BIT POSITION FUNCTION DESCRIPTION N/A SYNCOUT Strobe A write to this address generates a one clock period wide strobe on the SYNCOUT pin that is synchronized to the clock. This strobe may be synchronized to CLKIN or PROCCLK based on the programming of bit 3 of Control Word 0. CONTROL WORD 20: BUFFER RAM, DIRECT PARALLEL, AND DIRECT SERIAL OUTPUT CONFIGURATION (SYNCHRONIZED WITH PROCCLK) (Continued) BIT POSITION FUNCTION DESCRIPTION HSP50214A

CONTROL WORD 25: COUNTER AND ACCUMULATOR RESET (SYNCHRONIZED TO BOTH CLKIN AND PROCCLK) BIT POSITION FUNCTION DESCRIPTION N/A Counter and Accumulator Reset A write to this address initializes the counters and accumulators for testing. Items that are reset are: Carrier NCO. 1. Loads phase offset <9:0> into register to be used for adding to accumulator. 2. Enables feedback on the accumulator. CIC Filter 1. Resets the decimation counter. 2. Clears enables to CIC. 3. Clears accumulators in CIC. 4. Clears enable leaving CIC. Halfband Filters 1. Resets compute counter in Halfband control. 2. Resets read address for all Halfband Filters. 3. Resets write address for all Halfband Filters. 4. Clears input available strobe. 5. Resets Halfband control logic.

255 Tap FIR

1. Resets FIR read and write address pointers. 2. Zero’s coefficient read address. AGC Loop 1. Clears accumulator in loop filter. Re-Sampler and Interpolation Halfband Filters. 1. Resets counters for Halfband addresses for writing. 2. Resets output enable. 3. Reset controller for Re-Sampler. Timing NCO 1. Initializes counters for inserting extra pulses when interpolating halfbands are enabled. In the HSP50214A, a configuration control word bit determines if a Timing NCO reset is ex- ecuted. If Control Word 27, Bit 20 is set to a logic one, a reset will clear the feedback in the timing NCO phase accumulator. If Control Word 27, Bit 20 is zero, a reset will not clear the timing NCO phase accumulator feedback, which is how the HSP50214 operated. Discriminator 1. Resets read and write address pointers. 2. Zero’s coefficient read address. Cartesian to Polar Coordinate Counter 1. Resets Cordic counters (stops current computation). FIFO Control 1. Resets decoder for controlling FIFO. 2. Resets write address for FIFO. 3. Clears RD and INTRRPT. 4. Resets “depth” and “full” flags. 5. Sets the empty flag. 6. Sets the read address to “7”, write address to “0”. Snapshot Control 1. Zeros the group number. 2. Load interval counter. 3. Resets write address and read address for FIFO. Output Serial Control 1. Reloads shift counter. 2. Reloads “Number of Words” counter. 3. Reloads counter for sync (for early or late). 4. Reloads counter for dividing down SERCLK. 5. In the HSP50214A, the Control Word 25 reset signal is designed such that the front end reset is 10 CLKIN periods wide and the back end reset is 10 PROCCLK periods wide. This guarantees that no enables will be caught in the pipelines. HSP50214A

24 Test Circuit Disable The A Version includes test circuitry for the ROM and RAM blocks that was not present in the orig- inal release part. This circuitry must be disabled before loading the coefficient RAM’s. This is done by setting bit 24 to zero. NOTE: Because the HSP50214 did not require a “write” to Control Word 25 and the HSP50214A does require that Control Word 25, Bit 24 be set to zero for normal operation, software that was written for the HSP50214 will require modification to work properly with the HSP50214A. CONTROL WORD 26: LOAD AGC GAIN (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION N/A AGC Load Writing to this location generates a strobe to load the AGC loop accumulator with bits (15:5) to the master registers. These bits are loaded into the MSBs of the AGC loop filter accumulator with bits (15:12) mapping to the shift (exponent) control bits and bits (11:5) mapping to the mul- tiplier (mantissa) bits. Bits (11:5) represent a binary mantissa mapped to the linear gain as: 01.XXXXXXX. See AGC Section. CONTROL WORD 27: TEST REGISTER (SYNCHRONIZED TO CLKIN) BIT POSITION FUNCTION DESCRIPTION 31-25 Reserved A fixed value of 0000 000 is loaded here for normal operation. 24 RAM Test Enable 0 = Normal Operation; 1 = RAM Test Enabled.

23 Input Level Detector

0 = The two LSB’s of the interpolation period preload are set to zero. 1 = The two LSB’s of the interpolation period preload are set to one.

22 SYNCIN1 Reset

0: SYNCIN1 causes only front end reset. 1: SYNCIN1 causes front end and back end resets.

21 Timing Error Input

0 = Operates as HSP50214. 1 = Corrects an error in the 4 LSB’s.

20 Timing NCO Reset

0 = Backend reset will not clear the timing NCO phase accumulator feedback. 1 = Backend reset clears the timing NCO phase accumulator. 19 - 18 Discriminator FIR Input 00 = 18 bits of delayed and subtracted (optionally shifted) phase. 01 = 18 bits of magnitude from coordinate converter. 1X = 18 bits of resampler/halfband filer I output.

17 Input Level Detector

0 = No external sync control of input end detector start/restart of integration period. 1 = SYNCIN causes the input level detector to start/restart its integration period.

16 AGC Average

0: AGC settles to mean. 1: AGC settles to median. 15 AGC Clear Inhibit When set to zero, this bit will clear the AGC loop filter accumulator on a SYNCIN2 assertion or a WRITE to CW 25. When set to a one, a WRITE to CW25 will not clear the AGC loop filter accumulator.

14 Q Input to Coordi-

nate Converter (see bits 19 - 15) 0 = I and Q enabled to coordinate converter. I = Q input to coordinate converter is zeroed.

13 Coordinate Convert-

0 = The Resampler HB filter output is routed to coordinate converter. 1 = The output of 255 tap FIR is routed to coordinate converter. 12-0 Reserved A fixed value 0 0010 0111 1000 [0278]hex is loaded here for normal operation. A fixed value 0 0010 0111 1010 [027A]hex is loaded here for setting the Sin/Cos Generator out- puts to 7FFF . CONTROL WORD 25: COUNTER AND ACCUMULATOR RESET (SYNCHRONIZED TO BOTH CLKIN AND PROCCLK) (Continued) BIT POSITION FUNCTION DESCRIPTION HSP50214A

CONTROL WORDS 64-95: DISCRIMINATOR COEFFICIENT REGISTERS (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION DESCRIPTION 31-10 Discriminator FIR Coefficient The discriminator FIR coefficients are 22-bit-two’s complement. If the filter is symmetric, the co- efficients are loaded from the center coefficient at address 64 to the last coefficient. If the filter is asymmetric the coefficients C 0 to CN are loaded with C0 in address 64 up to 64+N, where N is number of asymmetric coefficients. CONTROL WORDS 128-255: 255 PROGRAMMABLE COEFFICIENT REGISTERS BIT POSITION FUNCTION DESCRIPTION 31-10 Programmable FIR Coefficient The programmable FIR coefficients are 22-bit-two’s complement. If the filter is symmetric, the coefficients are loaded from the center coefficient at address 128 to the last coefficient. If the filter is asymmetric the coefficients C 0 to CN are loaded with C0 in address 128 up to 128+N, where N is number of asymmetric coefficients. Real Filters are computed as: Xn-k+1 Ck1 + Xn-k+2 Ck-2 + ... XnC0), where C0 is the coefficient in address 128 and Xo is the oldest data sample. Complex filters outputs are computed as follows: Xn is the most recent data sample. k is the number of samples = number of (complex) taps. C0_re is the coefficient loaded into CW128. C0_im is the coefficient loaded into CW129. The convolution starts with the oldest data, times the last complex coefficient, and ends with the newest data, times the first complex coefficient loaded. Iout = (-Xn-k+1_q * Ck-1_im + Xn-k+1_i * Ck-1_re). + (-Xn-k+2_q * Ck-2_im + Xn-1+2_i * Ck-2_re). + ... + (-Xn_q * C0_im + Xn_i * C0_re). Qout = (Xn-k+1_i * Ck-1_im + Xn-k+1_q * Ck-1_re). + (Xn-k+2_i * Ck-2_im + Xn-1+2_q * Ck-2_re). + ... + (Xn_i * C0_im + Xn_q * C0_re). HSP50214A

Absolute Maximum Ratings Thermal Information Operating Conditions Temperature Range oC to 70oC CC Thermal Resistance (Typical, Note 4) θJA (oC/W) (Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 4. θJA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Logical One Input Voltage V IH VCC = 5.25V 2.0 - V Logical Zero Input Voltage V IL VCC = 4.75V - 0.8 V Clock Input High V IHC VCC = 5.25V 3.0 - V Clock Input Low V ILC VCC = 4.75V - 0.8 V Output High Voltage V OH IOH = -400µA, VCC = 4.75V 2.6 - V Output Low Voltage V OL IOL = +2.0mA, VCC = 4.75V - 0.4 V Input Leakage Current I I VIN = VCC or GND, VCC = 5.25V -10 +10 µA Standby Power Supply Current I CCSB VCC = 5.25V, Outputs Not Loaded - 500 µA Output Leakage Current I O VIN = VCC or GND, VCC = 5.25V -10 +10 µA Operating Power Supply Current I CCOP CLK = PROCCLK = 55MHz, VIN =V CC or GND, V CC = 5.25V, Outputs Not Loaded - 420 mA (Note 5) Input Capacitance C IN Freq = 1MHz, VCC open, all measure- ments are referenced to device ground -8 p F (Note 6)Output Capacitance C OUT NOTES: 5. Power Supply current is proportional to operation frequency. Typical rating for ICCOP is 7.0mA/MHz. 6. Capacitance TA =2 5oC, controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes. HSP50214A

CLKIN Clock Period t CP 15 - ns CLKIN High t CH 6- n s CLKIN Low t CL 6- n s PROCCLK Period t PCP 18/24 (Note 10) - ns PROCCLK High t PCH 7- n s PROCCLK Low t PCL 7- n s REFCLK Clock Frequency f RCP - PROCCLK/2 Hz REFCLK High t RCH 7- n s REFCLK Low t RCL 7- n s Setup Time GAINADJ(2:0), IN(13:0),ENI, COF, COFSYNC, and SYNCIN1 to CLKIN tDS 7- n s Hold Time GAINADJ(2:0), IN(13:0),ENI, COF, COFSYNC, and SYNCIN1 from CLKIN tDH 0- n s Setup Time AGCGNSEL, SOF, MCSYNCI, SOFSYNC, and SYNCIN2 to PROCCLK tDSS 7- n s Hold Time AGCGNSEL, SOF, MCSYNCI, SOFSYNC, and SYNCIN2 from PROCCLK tDHS 0- n s Setup Time, A(2:0) to Rising Edges ofWR t WSA 8- n s Setup Time, C(7:0) to Rising Edges ofWR t WSC 10 - ns Hold Time, A(2:0) from Rising Edges ofWR t WHA 2- n s Hold Time, C(7:0) from Rising Edges ofWR t WHC 0- n s WR to CLKIN t WC 14 - ns (Note 9) PROCCLK to AOUT(15:0), BOUT (15:0),DATARD Y, SEROUTA, SEROUTB, INTRRP tDO_OUT -8 n s PROCCLK to SYNCOUT t DO_SYNCO -8 n s PROCCK to MCSYNCO t DO_MCSYNCO -6 n s PROCCLK to SERCLK, SERSYNC Valid t DOS -1 2 n s WR High t WRH 15 - ns WR Low t WRL 8- n s RD Low t RL 20 - ns Address Setup to Read Low t AS -3 n s RD LOW to Data Valid t RDO -1 8 n s RD HIGH to Output Disable t ROD -1 0 n s (Note 8) Output Enable Time t OE -6 n s Output Enable Time - FIFO Read Mode t OEBL -1 5 n s Output Disable Time t OD -8 n s (Note 8) Output Rise, Fall Time t RF -3 n s (Note 8) NOTES: Test VIH = 3.0V, VIHC = 4.0V, VIL = 0V. 8. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes. 9. Without discriminator/with discriminator. HSP50214A

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. ties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

1130 Brussels, Belgium

FIGURE 54. OUTPUT ENABLE/DISABLE FIGURE 55. TIMING RELATIVE TO PROCCLK FIGURE 56. REFCLK