HSP50210 INTERSIL | Alldatasheet
Document overview
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- PDF pages: 51
Technical content
Features
- Clock Rates Up to 52MHz
- Selectable Matched Filtering with Root Raised Cosine or Integrate and Dump Filter
- Second Order Carrier and Symbol Tracking Loop Filters
- Automatic Gain Control (AGC)
- Discriminator for FM/FSK Detection and Discriminator Aided Acquisition
- Swept Acquisition with Programmable Limits
- Lock Detector
- Data Quality and Signal Level Measurements
- Cartesian-to-Polar Converter
- 8-Bit Microprocessor Cont rol - Status Interface
- Designed to Work With the HSP50110 Digital Quadrature Tuner
- 84 Lead PLCC
- Pb-Free Available (RoHS compliant)
Applications
- Satellite Receivers and Modems
- BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM Demodulators
- Digital Carrier Tracking
- Related Products: HSP50110 Digital Quadrature Tuner, D/A Converters HI5721, HI5731, HI5741
- HSP50110/210EVAL Digital Demod Evaluation Board Block Diagram DATA PATH MULTIPLEXER FILTER CONTROL INTERFACESTATUS TRACK CONTROL OUT(9-0) OUT(9-0) BUS TRACK CONTROL RRC DUMP INTEGRATE/ LOOP FILTER MAGNITUDE PHASE I Q 10 CARRIER ACQ/TRK LOOP FILTER SYMBOL Q I LEVEL DETECTHI/LO SLICER CARTESIAN TO POLAR FILTER RRC DUMP INTEGRATE/ NCO LEVEL DETECT COS SIN CARRIER CONTROL/ TRACKING LOCK DETECT SERCLK (COF) (SOF) A B SMBLCLK THRESH LKINT OEA OEB SYMBOL I SER OR IIN (9-0) CARRIER PHASE ERROR DETECT LOOP FILTER SYMBOL PHASE DETECT ERROR OR CLK Q SER OR QIN (9-0) Data Sheet July 2, 2008
FN3652.5 July 2, 2008 Pinout HSP50210 (84 LD PLCC) TOP VIEW 535251504948474645444342414039383736353433 757677787980818283841234567891011 AOUT4 AOUT5 AOUT6 GND AOUT7 AOUT8 AOUT9 OEA THRESH SLOCLK HI/LO ISER QSER VCC SSYNC GND SERCLK IIN9 IIN8 IIN7 IIN6 GND LKINT FZ-CT FZ-ST COF VCC GND RD WR COFSYNC IIN5 IIN4 IIN3 IIN2 GND IIN1 IIN0 SYNC QIN9 QIN8 QIN7 QIN6 QIN5 QIN4 VCC QIN3 QIN2 QIN1 QIN0 SOFSYNC SOF AOUT1 AOUT3 AOUT2 AOUT0 SMBLCLK VCC CLK GND BOUT9 BOUT8 BOUT7 BOUT6 BOUT5 GND BOUT4 BOUT2 BOUT1 BOUT0 OEB VCC BOUT3
Ordering Information
PART NUMBER PART MARKING TEMP . RANGE (°C) PACKAGE PKG. DWG. # HSP50210JC-52 HSP50210JC-52 0 to +70 84 Ld PLCC N84.1.15 HSP50210JC-52Z (Note) HSP50210JC-52Z 0 to +70 84 Ld PLCC (Pb-free) N84.1.15 HSP50210JI-52 HSP50210JI-52 -40 to +85 84 Ld PLCC N84.1.15 HSP50210JI-52Z (Note) HSP50210JI-52Z -40 to +85 84 Ld PLCC (Pb-free) N84.1.15 NOTE: These Intersil Pb-free plas tic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. HSP50210
FN3652.5 July 2, 2008 Pin Description NAME TYPE DESCRIPTION VCC - +5V Power Supply. GND - Ground. IIN9-0 I In-Phase Parallel Input. Data may be two’s complement or offset binary format (see Table 15). These inputs are sampled by CLK when the SYNC signal is active Low. IIN9 is the MSB. See “Input Controller” on page 6. QIN9-0 I Quadrature Parallel Input. Data may be two’s complement or offset binary format (see Table 15). These inputs are sampled by CLK when the SYNC signal is active Low. QIN9 is the MSB. “Input Controller” on page 6. SYNC I Data Sync. When SYNC is asserted “Low”, data on IIN9-0 and QIN9-0 is clocked into the processing pipeline by the rising edge of CLK. COF O Carrier Offset Frequency. The frequency term generated by the Carrier Tracking Loop Filter is output serially via this pin. The new offset frequency is shifted out MSB first by CLK or SLOCLK starting with the clock cycle after the assertion of COFSYNC. COFSYNC O Carrier Offset Frequency Sync. This signal is asserted one CLK or SLOCLK cycle before the MSB of the serial data word. (Programmable Polarity, see Table 42 on page 42, Bit 11). SOF O Sampler Offset Frequency. Sample frequency correcti on term generated by the Symbol Tracking Loop Filter is output serially via this pin. The frequency word is shifte d out MSB first by CLK or SLOCLK starting with the clock cycle after assertion of SOFSYNC. SOFSYNC O Sampler Offset Frequency Sync. Th is signal is asserted one CLK or SLOCLK cycle before the MSB of the serial data word. (Programmable Polarity, see Table 42 on page 42, Bit 12). A2-0 I Address Bus. The address on these pins specify a tar get register for reading or writing (see “Microprocessor Interface” on page 27). A0 is the LSB. C7-0 I/O Microprocessor Interface Data Bus. This bi-directional bus is used for reading and writing to the processor interface. These are the data I/O pins for the processor interface. C0 is the LSB. WR I Write. This is the write strobe fo r the processor interface (see “Microprocessor Interface” on page 27). RD I Read. This is the read enable for the processor inte rface (see “Microprocessor Interface” on page 27). FZ_ST I Freeze Symbol Tracking Loop. Assert ing this pin “high” zeroes the sampling error into the Symbol Tracking Loop Filter (see “Symbol Tracking Loop Filter” on page 17). FZ_CT I Freeze Carrier Tracking Loop. Asserting this pin “high” ze roes the carrier Phase Error input to the Carrier Tracking Loop Filter. LKINT O Lock Detect Interrupt. This pin is asserted “high” for at least 4 CLK cycles when the Lock Detector Integration cycle is finished (see “Lock Detector” on page 23). Used as an interrupt for a processor. The Lock Detect Interrupt may be asserted “high” longer than 4 CLK cycles, depending on the Lock Detector mode. THRESH O Threshold Exceeded. This output is asserted “low” when the magnitude out of the Cartesian to Polar converter exceeds the programmable Power Detect Threshold (see Table 16 on page 33 and “AGC” on page 10). SLOCLK O Slow Clock. Optional serial clock used for outputting data from the Carrier and Symbol Tracking Loop Filters. The clock is programmable and has a 50% duty cycle. Note: Not used when the HSP50110 is used with the HSP50210 (see Table 42 page 42). ISER I In-Phase Serial Input. Serial data input for In-Phase Data . Data on this pin is shifted in MSB first and is synchronous to SERCLK (see “Input Controller” on page 6). QSER I Quadrature Serial Input. Serial data input for Quadratur e Data. Data on this pin is shifted in MSB first and is synchronous to SERCLK (see “Input Controller” on page 6). SSYNC I Serial Word Sync. This input is asserted “high” one CLK before the first data bit of the serial word (see Figure 2). SERCLK I Serial Clock. May be asynchronous to other clocks. Us ed to clock in serial data (see “Input Controller” on page 6). AOUT9-0 O A Output. Data on this output depend on the configuration of Output Selector. AOUT9 is the MSB (see Table 43 on page 44). BOUT9-0 O B Output. Data on this output depend on the configuration of Output Selector. BOUT9 is the MSB (see Table 43 page 44). SMBLCLK O Symbol Clock. 50% dut y cycle clock aligned with soft bit decisions (see Figure 19). HSP50210
FN3652.5 July 2, 2008 OEA I A Output Enable. This pin is the three- state control pin for the AOUT9-0. When OEA is high, the AOUT9-0 is high impedance. OEB I B Output Enable. This pin is the three-st ate control pin for the BOUT9-BOUT0. When OEB is high, the AOUT9-0 is high impedance. HI/LO 0 HI/LO. The output of the Input Level Detector is provi ded on this pin (see “Input Level Detector” on page 6). This signal can be externally averaged and used to control the gain of an amplifier to close an AGC loop around the A/D converter. This type of AGC sets the level based on the median value on the input. CLK I System Clock. Asynchronous to the processor interface and serial inputs. Pin Description (Continued) NAME TYPE DESCRIPTION HSP50210
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF THE HSP50210
15 TAP RRC
FIGURE 3. MAIN DATA PATH
FN3652.5 July 2, 2008 NCO/Mixer The NCO/Mixer performs a complex multiply between the baseband input and the output of a quadrature NCO (Numerically Controlled Oscillator). When the HSP50210 (DQT) is used with the HSP50110 (DCL), the NCO/Mixer shortens the Carrier Tracking Loop (i.e., minimizes pipeline delay around the loop) while providing wide loop bandwidths. This becomes important when operating at symbol rates near the maximum range of the part. There are three configurations possible for closing the Carrier Tracking Loop when the DQT and the DCL are used together. The first configuration utilizes the NCO on the DQT and bypasses the NCO in the DCL. The Data Path Configuration Control Register (see Table 15 on page 32), Bit 10, and Carrier Loop Filter Control Register #1 (see Table 21 on page 34), Bit 6, are used to bypass the DCL NCO/Mixer and route the Loop filter outputs, respectively. The DQT provides maximum flexibility in NCO control with respect to frequency and phase offsets. The second configuration feeds the lead Carrier Loop filter term to the DCL NCO/Mixer, and the lag Loop filter Term to the DQT NCO. This reduces the loop transport delay while maintaining wide loop bandwidths and reasonable loop damping factors. This configuration is especially useful in SATCOM applications with medium to high symbol rates. The Carrier Loop Filter Control Register #1, Bit 5 is where the lead/lag destination is set. The final configuration feeds both the lead and lag Carrier Loop Filter terms back to the DCL NCO/Mixer. This provides the shortest transport delay. The DCL NCO/Mixer provides only for frequency/phase control from the Carrier Loop filter. The center frequency of this NCO/Mixer is set to the average of the Upper and Lower Carrier Loop Limits programmable parameters. These parameters are set in the two control registers bearing their names (see Tables 23 and 24 on page 35). The NCO/Mixer uses a complex multiplier to multiply the baseband input by the output of a quadrature NCO. This operation is represented by Equations 2 and 3: Equation 3 illustrates how the complex multiplier implicitly performs the summing function when the DCL is configured as a modulator. The quadrature outputs of the NCO are generated by driving a sine/cosine look-up table with the output of a phase accumulator, as shown in Figure 3 on page 7. Each time the phase accumulator is clocked, its sum is incremented by the contents of the Carrier Frequency (CF) Register. As the accumulator sum increments from 0 to 2 32, the SIN/COS ROM produces quadrature outputs whose phase advances from 0 to 360°. The CF Register contains a 32-bit phase increment, which is updated with the output of Carrier Tracking Loop. Large phase increments take fewer clocks to step through the sine wave cycle, which results in a higher frequency NCO output. The CF Register sets the NCO frequency using Equation 4: where f CLK is the CLK frequency, and CF is the 32-bit two’s complement hexadecimal value loaded into the Carrier Frequency Register. As an example, if the CF Register is loaded with a value of 4000 0000 (Hex), and the CLK frequency is 40MHz, the NCO would produce quadrature terms with a frequency of 10MHz. When CF is a negative value, a clockwise cos/sin vector rotation is produced. When CF is positive, a counterclockwise vector rotation is produced. Note: The NCO is set to a fixed frequency by programming the upper and lower limits of the Carrier Tracking Loop Filter to the same value and zeroing the lead gain. Matched Filtering The HSP50210 provides two selectable matched filters: a Root Raised Cosine Filter (RRC) and an Integrate and Dump (I and D) filter. These are shown in Figure 3. The RRC filter is provided for shaped data pulses and the I and D filter is provided for square wave data. The filters may be cascaded for better adjacent channel rejection for square wave data. If these two filters do not meet baseband filtering requirements, then they can be bypassed and an external digital filter (such as the HSP43168 Dual FIR Filter or the HSP43124 Serial I/O Filter) used to implement the desired matched filter. The desired filter configuration is set in the Data Path Configuration Control Register, bits 1 through 7 (see Table 15 on page 32). The sample rate of the baseband input depends on the symbol rate and filtering configuration chosen. In configurations which bypass both filters or use only the RRC Filter, the input sample rate must be twice the symbol rate. In configurations which use the I and D Filter, the input sample rate is decimated by the I and D Filter, down to two samples per symbol. I and D configurations support input sample rates up to 32x the input symbol rate. The RRC filter is a fixed coefficient 15 Tap FIR filter. It has ~40% excess bandwidth beyond Nyquist, which equates to α = ~0.4 shape factor. The filter frequency response is shown in Figures 4 and 5. In addition, the 9-bit filter coefficients are listed as integer values in Table 1. The noise equivalent bandwidth of the RRC filter and other filter configurations possible with the HSP50110/210 chipset are given in Appendix A. IOUT IIN ωC()cos Q IN ωC()sin–= QOUT IIN ωC()sin Q IN ωC()cos+= (EQ. 2) (EQ. 3) FC fCLK CF() 2⁄ 32×= CF INT F C fCLK⁄() 232[] H= (EQ. 4) HSP50210
Decision Slicer to yield optimum performance. system Bit Error Rate performance. power detection or external AGC around the A/D converter. page 33). This bit is used to disable the AGC loop. characteristics: gain tracking, tracking rate and tracking limits. scaling from 0.000 to 0.9375, with a resolution of 0.0625. TABLE 2. AGC LOOP GAIN BINARY MANTISSA TO DECIMAL TABLE 3. AGC LOOP BINARY EXPONENT TO SCALED
Loop Gain, (2-7) is the maximum shift gain, and 24 is the maximum loop filter gain. A similar procedure is used to calculate the minimum AGC response rate. Thus, the expected range for the AGC rate is approximately 0.0004 to 0.0469dB/symbol time. TABLE 6. AGC BIT WEIGHTING
22 Shifter → E1 1 2
21 Shifter → E0 6
20 Multiplier → M- 1 3
The gain distribution in the DCL is shown in Figure 10. numbers with relative bit weightings, as shown in Figure 10. is unity gain since its output is scaled by one-half. NCO (see HSP50110 Datasheet).
20 TO 23
- If the Root Raised Cosine Filter is enabled, a gain of G = 1.13 is introduced. If the RRC filters bypassed, the gain is unity.
- If the integrate and Dump Filter is bypassed the Sample Pair summer has a gain of G = 1.0 and the 2-7-bit position is set to 1. If the integrate
and dump is enabled, the sample pair sum is scaled by one half (G = 0.5).
- The negative sign on the MSBs indicates use of 2’s complement data format.
FIGURE 10. GAIN DISTRIBUTION AND INTERMEDIATE BIT WEIGHTINGS
FIGURE 11. SYMBOL TRACKING
5 MSPS (f
be scaled accordingly if the accumulator is used. accumulated to give the integral response (see Figure 11). and ~1.0 as given by Equation 10. programmable soft decision threshold (see Figure 13). FIGURE 12. TRACKING ERROR ASSOCIATED WITH
FIGURE 13. OVERLAY OF THE HARD/SOFT DECISION TABLE 7. SLICER INPUT TO OUTPUT MAPPING
exceeds CLK/6, error terms will be missed. Cartesian-to-Polar converter. accordingly if the accumulator is used. through 28 beginning on page 34. are set through a programmable mantissa and exponent. -32 and ~1.0 as given by Equation 11. Control Registers (see Tables 25 through 26 on page 36). loop gain, the Phase Error is passed almost unattenuated. both tracking and acquisition sweep modes. Microprocessor Interface” on page 27. TABLE 8. BASIC PHASE ERROR DETECTOR SETTINGS FIGURE 14. PHASE ERROR DETECTOR OPERATION (QPSK)
FIGURE 15. CARRIER ACQUISITION/TRACKING LOOP BLOCK DIAGRAM
TABLE 9. BIT WEIGHTING IN THE CARRIER LOOP FILTER TO THE NCO - TRACKING
TABLE 10. BIT WEIGHTING IN THE CARRIER LOOP FILTER TO THE NCO - SWEEP
carrier acquisition (see “Lock Detector Control” on page 24). allow the loop to settle before starting the integration. Control Register; Table 19). Cartesian-to-Polar converter. Register, Table 42 on page 42). output from the DCL through two separate serial interfaces. Note: Data must be loaded MSB first. FIGURE 16. SERIAL OUTPUT TIMING FOR COF AND SOF
FN3652.5 July 2, 2008 State Machine (see Figure 16). The function of the Lock Detector is to monitor the baseband symbols and to decide whether the Carrier Tracking Loop is locked to the input signal. Note: The Symbol Tracking Loop locks independently; under most circumstances, it will lock before the Carrier Tracking Loop locks up. Based on the in-lock/out-of-lock decision, either the Acquisition or Tracking parameters are selected in the Carrier Tracking Loop, the Symbol Tracking Loop and in the Lock Detector itself. The Lock Detector can be configured either to make the “lock” decision automatically using the State Machine Control Mode, or to collect the necessary data so that an external microprocessor can control the acquisition/tracking process via the Microprocessor Control Mode (see Figure 22). In State Machine Control Mode, the Lock Detector State Machine monitors the outputs of the Phase Error Accumulator and the False Lock Accumulator to determine the Lock Detector state. Accumulation effectively averages the Phase Error and false lock count, reducing their variance. Lock is detected by accumulating the magnitude of the Phase Error over a predetermined interval up to 1025 symbols (the Integration Time). When the Carrier Loop is locked, the Integration Period will end before an overflow occurs in the Phase Error Accumulator. At the beginning of a lock detection cycle, the Phase Error Accumulator and the Integration Counter are loaded with their respective pre-load values. With each end bit sample, the Phase Error Accumulator adds the magnitude of the current Phase Error to its accumulated sum, while the Integration Counter decrements one count. The Lock Detector State Machine monitors the overflow bit of the Phase Error Accumulator and the output of the Integration Counter. If the Phase Error Accumulator overflows before the Integration Counter reaches zero, then the accumulated Phase Error is too large for the Carrier Tracking Loop to be in lock and the Lock Detector State Machine goes into the Search state (see Lock Detector State Machine in Figure 17). In the search state, the loop parameters are reloaded with “Acquisition” rather than “Tracking” values. When the Phase Accumulator overflows or when the Integration Counter reaches zero, the Integration Counter and the accumulators are re-initialized and the process begins again. The Integration Counter Pre-load corresponds to the number of symbols over which to integrate. The Phase Error Preload corresponds to the distance the Phase Error Accumulator starts away from overflow. This distance divided by the Integration Period equals the average Phase Error. The pre-load value is calculated using Equation 12: where Full scale = 2 18-1 Full scale phase = 180° for CW, 90° for BPSK, 45° for QPSK, etc; Lock Threshold <45° for BPSK, <22.5° for QPSK, etc. (typical after shift); and Integration Count = Integration Period measured in symbol times. The False Lock Detector is used to indicate false lock on square wave data in a high SNR environment. A false lock condition is detected by monitoring the final integration stage in the Q branch of the Integrate and Dump Filter (see Figure 3 on page 7). If the magnitude of the integration over the symbol period is less than the integration over half a symbol period, a possible false lock condition is detected; (integration over a symbol period has gone from end-bit to end-bit, while integration over half the symbol period has gone from the previous end-bit to mid-bit). By accumulating the number of these occurrences over the Integration Period, the Lock Detector State Machine determines whether a false lock condition exists. The False Lock Accumulator is used to accumulate the number of possible false lock occurrences over the Integration Period. The False Lock Accumulator can also be configured to accumulate the output of the Frequency Error Detector (see Lock Detection Configuration Control Register Bit 27: Table 35 on page 40). The Gain Error Accumulator provides a mechanism to estimate data quality (E s/No). The accumulator integrates the magnitude of the gain error of the end-bit samples, over the Integration Period. Note: The Gain Error end-bit data is valid only after lock has been declared, and the demod is the tracking mode. The accumulated value gives an indication of the variance about the ideal constellation points. The accumulator output is read via the Microprocessor Interface. T he Gain Error Accumulator is always pre-loaded with zero. For applications where stepped acquisition is used, a Dwell Counter is provided. In this mode, the lag accumulator in the Carrier Loop Filter is stepped to a new frequency after each Lock Detector integration. The Dwell Counter is used to hold off Lock Accumulator integration until the loop has a chance to settle. Lock Detector Control The selection of acquisition and tracking modes is controlled by either the internal state machine or an external microprocessor. The internal state machine monitors the rollover of the Phase Error Accumulator and the False Lock Accumulator relative to the Integration Counter. Depending on whether the accumulators or counter roll over first, the acquisition or tracking parameters are selected for the Loop Filters and the Lock Detector Accumulators. In addition, the state machine controls the frequency sweep input to the Carrier Tracking Loop. The flow of the acquisition control is shown in the State Diagram in Figure 18 on page 26. The state machine controls the acquisition process described as follows: Full Scale Lock Threshold ⎛⎞– (EQ. 12) Preload = HSP50210
(average Phase Error is less than the lock threshold). threshold for a programmable number of Integration Periods. before the Integration Counter, a false lock condition exists. Periods before returning to the search state. output is asserted and the False Lock Detector is disabled. Counter rolls over before the Phase Error Accumulator. function is enabled via the Microprocessor Interface. FIGURE 17. LOCK DETECTOR BLOCK DIAGRAM
end-symbol samples, as shown in Figure 20. from the Microprocessor Interface. than 4 CLKs after an address register write (see Figure 21). a particular control register do not have to be loaded. TABLE 11. STATUS BIT DEFINITIONS
6 Carrier Tracking Loop Lock
4 Frequency Sweep Direction
3 High Power
2 Low Power
1 Data Rdy
TABLE 12. READ/WRITE ADDRESS MAP FOR 32-bit target control register. Note: Addresses outside the range 0-31 are invalid. FIGURE 20. OUTPUT DATA CLOCK TIMING C7-0, respectively. Bit 31 is the MSB. TABLE 12. READ/WRITE ADDRESS MAP FOR
read procedures are summarized in Figures 21 through 23. the Write Address Register of the Microprocessor Interface. register contents are updated each CLK. TABLE 13. READ ENABLE ADDRESS MAP 1 Symbol Tracking Loop Filter Lag Accumulator. MSBs of the lag accumulator. containing 8 MSBs of the AGC accumulator. of the False Lock Accumulator.
required to be synchronous to CLK. They are shown that way to clarify the illustration. FIGURE 21. CONTROL REGISTER LOADING SEQUENCE required to be synchronous to CLK. They are shown that way to clarify the illustration.
- Load the Write Address Register with 29 dec to load the output holding registers.
- Enable Carrier Loop Filter Lag Accumulator holding register for reading.
- Select the MSByte of the output holding register for output.
low to output data on C0-7. (Must wait for 6 CLKs after loading the holding registers).
- Select other bytes of holding register by changing A0-2 and asserting RD .
FIGURE 22. LOOP FILTER ACCUMULATOR READ SEQUENCE
6 CLKs
TABLE 14. INTERNAL STATUS REGISTER (SR7-0) BIT MAP required to be synchronous to CLK. They are shown that way to clarify the illustration.
- Load the Write Address Register with 24dec to halt the Lock Detector after the current integration cycle. This disables the reload of the integration
counter in the lock detector. The verify counter is not reset and will resume at the stopped value when the lock detector is restarted.
- Load the Read Address Register with 3 dec to enable the Lock Detector Phase Error Accumulator for reading.
- Read Internal Status Register to monitor SR-7 to det ermine when the Lock Detector is stopped and ready to be read.
- SR-7 goes high, indicating the Lock Detector in tegration cycle is complete, and ready to be read.
- Read Internal Status Register and find SR-7 = 1; the Lock Detector is ready to be read.
- Change Read address to (3; 2; 1; 0) for (Phase Error MSW; PE LSW; False Lock MSW; FL LSW) read.
- End of Internal Status Valid Data.
- Load The Write Address Register with 30dec to initialize Lock Detector Accumulators and Reset the Integration counters. (Not needed for state
- Load the Write Address Register with 25 dec to restart the Lock Detector.
FIGURE 23. PROCESSOR MONITORING INTE RNAL STATUS/READING LOCK DETECTOR
7 Lock Detector Stopped and Ready for Reading
(State Machine Control Mode). 0 = Lock Detector not stopped. 1 = Lock Detector stopped, ready for read.
6 Lock Detector Stopped and Ready for Reading
(Microprocessor Control Mode). 0 = Lock Detector not stopped. 1 = Lock Detector stopped, ready for read.
4 Symbol Tracking Loop Filter Lag Accumulator Load
Register with 19 (decimal) as described in Table 34. 3 Lock. Carrier Lock state achieved by Lock Detector. acquisition or tracking mode.
0 Frequency Sweep Direction, defined for upper sideband
TABLE 15. DATA PATH CONFIGURATION CONTROL REGISTER 31-27 Reserved Reserved. Set to 0 for proper operation. These bits set the shifter attenuation in the Integrate/Dump Filter. 15 Input Data Format Select 0 = Two’s Complement Input.
14 Serial/Parallel Input
13 Input Level Detector
0 = HI/LO output of 1 means input ≤ threshold. 1 = HI/LO output of 1 means input > threshold.
12 Q Input to Complex
0 = QIN9-0 enabled to Complex Multiplier. 1 = Q input to Complex Multiplier zeroed.
11 I Input to Complex
0 = IIN9-0 enabled to Complex Multiplier. 1 = I input to complex multiplier set to negative full scale (200 Hex).
10 Complex Multiplier
0 = Data enabled to Complex Multiplier (Multiplied by output of NCO). 1 = Complex Multiplier Bypassed.
9 Demodulation/Loop
0 = Error detector outputs routed to Loop Filters (Normal Mode of Operation).
8 Cartesian/Polar Input
0 = Enable output of AGC Multiplier to Cartesian to Polar Converter. 1 = Enable output of Integrate and Dump Filter to the Cartesian to Polar Converter. 7 RRC Filter Enable 0 = Enable RRC filter.
6 Integrate and Dump
0 = End-Symbol Samples routed to Output Formatter. SMBLCLK is high; Mid-Symbol samples occur when SMBLCLK is low.
5 Integrate and Dump
0 = Input taken from output of Frequency Discriminator (FSK routing). 1 = Input taken from output of AGC Multiplier (Select this setting for PSK demodulation). 1000 = No Decimation (no accumulation, no sample pair summing). 0000 = Decimation by 2 (no accumulation, sample pair summing). 0001 = Decimation by 4 (accumulate 2 samples, sample pair summing). 0010 = Decimation by 8 (accumulate 4 samples, sample pair summing). 0011 = Decimation by 16 (accumulate 8 samples, sample pair summing). 0100 = Decimation by 32 (accumulate 16 samples, sample pair summing). All other codes are invalid.
0 OQPSK Data
0 = Disables Q channel data delay. 1 = Delays Q Channel by 1/2 Symbol time to remove OQPSK stagger.
TABLE 16. POWER DETECT THRESHOLD CONTROL REGISTER 31-8 Not Used No programming required. Using this format, the possible range of threshold values is between 0 to 1.9961. Bit position 7 is the MSB. TABLE 17. AGC LOOP PARAMETERS CONTROL REGISTER 31 Enable AGC 0 = Gain error enabled to AGC Loop Filter. 1 = Gain error into AGC Loop Filter set to zero. may be achieved for EEE = 000 to 111 Binary. Bit position 30 is the MSB. See Table 3 on page 11. AGC Loop Gain Mantissa = 0. 2-12-22-32-4; 0.MMMM. This format provides a mantissa range from 0.0 to 0.9375 for mantissa settings from 0000 to 1111 Binary. Bit position 27 is the MSB. Mantissa resolution = 0.0625. See Table 2 on page 11. same as that for the Power Threshold given in Table 15 on page 32. the AGC can be set to a fixed gain. the AGC upper and lower limits to the same value, the AGC can be set to a fixed gain. TABLE 18. CARRIER PHASE ERROR DETECTOR CONTROL REGISTER 31-8 Not Used No programming required. 7-6 Reserved Reserved. Set to 0 for proper operation.
from 7π/8 to -π respectively. Resolution of 22.5° is provided. Bit position 5 is the MSB. of 0, 1, 2 or 3 places. MSBs are discarded and LSBs are zero-filled. Bit 1 is the MSB. TABLE 18. CARRIER PHASE ERROR DETECTOR CONTROL REGISTER (Continued) TABLE 19. FREQUENCY DETECTOR CONTROL REGISTER 31-8 Not Used No programming required. 7-3 Reserved Reserved. Set to 0 for proper operation. where K is the 3-bit value programmed here. Delays of 1, 2, 4, 8, and 16 are possible. TABLE 20. FREQUENCY ERROR DETECTOR CONTROL REGISTER 31-8 Not Used No programming required. acquisition with PSK waveforms. using frequency aided acquisition with PSK waveforms. TABLE 21. CARRIER LOOP FILTER CONTROL REGISTER #1 31-8 Not Used No programming required. 7 Reserved Reserved. Set to 0 for proper operation.
6 Lead/Lag to Serial
0 = The Carrier Loop Filter’s Lag Accumulator is routed to the Serial Output Controller.
5 Lead/Lag to Internal
0 = Sum of lead and lag paths routed to the internal NCO. (32 MSBs of sum are routed). 1 = The lead term is routed to the internal NCO. (32 MSBs of lead term are routed). cause 4 error terms to be accumulated. A total range from 1 to 32 is provided. TABLE 21. CARRIER LOOP FILTER CONTROL TABLE 22. CARRIER LOOP FILTER CONTROL REGISTER #2 31-8 Not Used No programming required. 7-6 Reserved Reserved. Set to 0 for proper operation.
5 Lead Phase Error
0 = Carrier Phase Error enabled to lead processing path of loop filter. 1 = Carrier Phase Error to lead processing path of loop filter zeroed.
4 Lag Phase Error
0 = Carrier Phase Error enabled to lag processing path of loop filter. 1 = Carrier Phase Error to lag processing path of loop filter zeroed (First Order Loop). 3 AFC Enable 0 = Frequency error enabled to lag processing path of Carrier Loop Filter. 2 Carrier Sweep Enable 0 = Frequency sweep input to the lag path of the Carrier Loop Filter enabled. 1 = Sweep input to Carrier Loop Filter zeroed.
1 Invert Carrier Phase
0 = Carrier Phase Error is normal into Carrier Loop Filter. 1 = Carrier Phase Error is inverted into Carrier Loop Filter.
0 Invert Carrier
0 = Carrier Frequency Error is normal into AFC loop filter. 1 = Carrier Frequency Error is inverted into AFC Loop filter. TABLE 23. CARRIER LOOP FILTER UPPER LIMIT CONTROL REGISTER bits of the 40-bit accumulator are set to the limit, and the 8 LSBs are set to zero. TABLE 24. CARRIER LOOP FILTER LOWER LIMIT CONTROL REGISTER the upper 32 bits of the 40-bit accumulator are set to the limit, and the 8 LSBs are set to zero.
TABLE 25. CARRIER LOOP FILTER GAIN (ACQ) CONTROL REGISTER 31-24 Not Used No programming required. 23-18 Reserved Reserved. Set to 0 for proper operation. These bits are the 4 fractional bits of the lead gain mantissa shown as follows. This format provides a mantissa range from 1.0 to 1.9375 for mantissa settings from 0000 to 1111 Binary. Carrier Lead Gain Exponent = 2 -(32-E). Binary. Bit position 13 is the MSB. Format same as lead gain mantissa. Bit position 8 is the MSB. Format same as lead gain exponent. Bit position 4 is the MSB. TABLE 26. CARRIER LOOP FILTER GAIN (TRK) CONTROL REGISTER 31-24 Not Used No Programming required. 23-18 Reserved Reserved. Set to 0 for proper operation. Format same as lead gain mantissa (see Table 25). Bit position 17 is the MSB. Format same as lead gain exponent (see Table 25). Bit position 13 is the MSB. Format same as lead gain mantissa (see Table 25). Bit position 8 is the MSB. Format same as lead gain exponent (see Table 25). Bit position 4 is the MSB. TABLE 27. FREQUENCY SWEEP/ AFC LOOP CONTROL REGISTER 31-27 Reserved Reserved. Set to 0 for proper operation. same as lead gain mantissa (see Table 25). Bit position 22 is the MSB. Sets Frequency Error Gain. Format same as lead gain exponent (see Table 25). Bit position 4 is the MSB.
Sets Frequency Error Gain. Format same as lead gain exponent (see Table 25). Bit position 4 is the MSB. TABLE 28. CARRIER LAG ACCUMULATOR INITIALIZATION CONTROL REGISTER MSBs of the lag accumulator and the 8 LSBs are zeroed. It is good practice to load the LAG Accumulators at the very end of a configuration load sequence. TABLE 29. SYMBOL TRACKING LOOP CONFIGURATION CONTROL REGISTER 31-16 Not Used No programming required. 15-13 Reserved Reserved. Set to 0 for proper operation. 00 = x2 2 levels on each rail (BPSK, QPSK). 01 = x4 4 levels on each rail (8 PSK). 10 = x8 8 levels on each rail. 11 = x16 16 levels on each rail. Note: Saturation is provided in case of overflow. 00 = 2ary signal (Use this setting for BPSK, QPSK, and OQPSK signals). TABLE 27. FREQUENCY SWEEP/ AFC LOOP CONTROL REGISTER (Continued)
8 Single/Double Rail
Note: Set to 1 for BPSK operation and 0 for QPSK operation.
2 Lead Sampling Error
0 = Sampling error enabled to lead path of loop filter. 1 = Sampling error to lead path of loop filter zeroed.
1 Lag Sampling Error
Sampling error enabled to lag path of loop filter. 1 = Sampling error to lag path of loop filter zeroed (First Order Loop). 0 Invert Sampling Error 0 = Sampling error normal. 1 = Sampling error inverted. TABLE 30. SYMBOL TRACKING LOOP FILTER UPPER LIMIT CONTROL REGISTER 40-bit accumulator are set to the limit, and the 8 LSBs are set to zero. TABLE 31. SYMBOL TRACKING LOOP FILTER LOWER LIMIT CONTROL REGISTER 32 bits of the 40-bit accumulator are set to the limit, and the 8 LSBs are set to zero. TABLE 32. SYMBOL TRACKING LOOP FILTER GAIN (ACQ) CONTROL REGISTER 31-24 Not Used No programming required. 23-18 Reserved Reserved. Set to 0 for proper operation. Symbol Tracking Lead Gain Mantissa = 01. 2-12-22-32-4. This format provides a mantissa range from 1.0 to 1.9375 for mantissa settings from 0000 to 1111 Binary. TABLE 29. SYMBOL TRACKING LOOP CONFIG URATION CONTROL REGISTER (Continued)
Binary. Bit position 13 is the MSB. Format same as lead gain mantissa. Bit position 8 is the MSB. Format same as lead gain exponent. Bit position 4 is the MSB. TABLE 32. SYMBOL TRACKING LOOP FILTER GAIN (ACQ) CONTROL REGISTER (Continued) TABLE 33. SYMBOL TRACKING LOOP FILTER GAIN (TRK) CONTROL REGISTER 31-24 Not Used No programming required. 23-18 Reserved Reserved. Set to 0 for proper operation. Format same as lead gain mantissa (see Table 32). Bit position 17 is the MSB. Format same as lead gain exponent (see Table 32). Bit position 13 is the MSB. Format same as lead gain mantissa (see Table 32). Bit position 8 is the MSB. Format same as lead gain exponent (see Table 32). Bit position 4 is the MSB. TABLE 34. SYMBOL TRACKING LOOP FILTER LAG ACCUMULATOR INITIALIZATION CONTROL REGISTER accumulator and the 8 LSBs are zeroed. It is a good practice to load the LAG accumulators at the very end of a configuration load sequence.
TABLE 35. LOCK DETECTOR CONF IGURATION CONTROL REGISTER 31-28 Reserved Reserved. Set to 0 for proper operation.
27 False Lock
This bit selects the input to the False Lock Accumulator. 0 = Frequency Error input enabled to accumulator. 1 = False Lock Bit enabled to accumulator. is zeroed during Track Mode. Only used during stepped acquisition mode. desired in the Integration Period. Total Range 2 to 1025. Bit 19 is the MSB. Function is identical to Acquisition Integration Counter Pre-Load. See previous. TABLE 36. LOCK ACCUMULATOR PRE-LOADS CONTROL REGISTER The accumulator roll over is at the 211 bit position. Function is identical to Acquisition Lock Accumulation Pre-Load. See previous. TABLE 37. FALSE LOCK ACCUMULATOR PRE-LOAD CONTROL REGISTER error input relative to accumulator full scale are shown as follows. which the Track parameters are used.
TABLE 38. ACQUISITION/TRACKING CONTROL REGISTER 31-16 Not Used No programming required. 15 Reserved Set to 0 for proper operation.
14 False Lock Detect
This bit enables the false lock detection during the verify state of state machine controlled acquisition. disabled, the overflow of the False Lock Accumulator has no effect on state machine operation. waveforms false lock detection should be disabled or frequency error should be used.
13 Frequency Sweep
0 = Stepped Frequency Sweep (provided for microprocessor controlled acquisition mode). 1 = Continuous Frequency Sweep. or false lock. The 4-bit value programmed here sets the verify state from 0 to 15 Integration Periods. 8-5 False Lock Sweep These bits set the duration of forc ed frequency sweep before returning to the acquisition state. sweep input to the lag accumulator. 1 = Internal State Machine Control.
3 Microprocessor
0 = Track Parameters Chosen. 1 = Acquisition Parameters Chosen. 1 Reserved Set to zero for proper operation.
0 Microprocessor
Loop Filter. This bit is only used under microprocessor control of the Lock Detector.
TABLE 39. HALT LOCK DETECTOR FOR READING CONTROL REGISTER Microprocessor Interface to determine when the Lock Detector has stopped and is ready for reading. restarted (see Restart Lock Detector Control Register: Table 40). TABLE 40. RESTART LOCK DETECTOR CONTROL REGISTER Detector Accumulators stop at the end of each integration cycle. See also Table 45. TABLE 41. SOFT DECISION SLICER CONFIGURATION CONTROL REGISTER 31-8 Not Used No programming required. 7 Slicer Output Format 0 = Soft decision outputs are in sign/magnitude format. 1 = Soft decision outputs are in two’s complement format. value should not exceed 1.0/3 = 0.33. Bit position 6 is the MSB. TABLE 42. SERIAL OUTPUT CONFIGURATION CONTROL REGISTER 31-16 Not Used No programming required. 15-13 Reserved Set to zero for proper operation.
12 Serial Data Sync
0 = SOFSYNC pulses “High” one serial clock before data word on SOF. 1 = SOFSYNC pulses “Low” one serial clock before data word on SOF. Set to 0 for use with the HSP50110.
11 Serial Data Sync
0 = COFSYNC pulses “High” one serial clock before data word on COF. 1 = COFSYNC pulses “Low” one serial clock before data word on COF. Set to 0 for use with the HSP50110.
10 Serial Clock Phase
0 = Rising edge of serial clock at center of data bit. 1 = Falling edge of serial clock at center of data bit. Set to 0 for use with the HSP50110. 9-8 Serial Clock Divider These bits set the clock rate of SLOCLK.
7 Serial Clock Select for
0 = CLK is used as the serial clock. 1 = SLOCLK is used as the serial clock. the SOF and COF outputs, and the same CLK must be used by both chips.
3 Serial Clock Select for
0 = CLK is used as the serial clock. 1 = SLOCLK is used as the serial clock. the SOF and COF outputs, and the same CLK must be used by both chips. TABLE 42. SERIAL OUTPUT CONFIGURATION CONTROL REGISTER (Continued)
TABLE 43. OUTPUT SELECTOR CONFIGURATION CONTROL REGISTER 31-8 Not Used No programming required. 7-4 Reserved Set to zero for proper operation. selections are listed below in Tables 43A and 43B. by CW26 bit 7, with one sign bit (ISOFT2) and two soft decision bits. by CW26 bit 7, with one sign bit (QSOFT2) and two soft decision bits. complement format. (MSB = Iend7). complement format. (MSB = Qend7). binary format. (MSB = MAG7). complement format. (MSB = FE7). complement format. (MSB = GE7). complement format. (MSB = TE7). complement format. (MSB = PE7). Bits 7-13 are output as LKACC(6.0). These outputs are zero otherwise. 0-6 are output as LKCNT(6-0). These outputs are zero otherwise. signals are included in all but one of the programmable multiplexer output configurations. These signals are useful when input to a D/A converter and displayed on an oscilloscope in the X-Y plot. This will yield the constellation signal display with which analog modem designers are familiar. This signal is useful in monitoring the AGC operation, signal detection and antenna tracking applications. Other single bit signals are provided for direct use in external AGC. particular signal magnitude or phase.
demodulator and matched filter are examples of such applications. dependent. These signals are also useful in fault detection in BIT/BITE applications. signal can be useful in fault detection in BIT/BITE applications.
0000 ISOFT2 ISOFT1 ISOFT0 QSOFT2 QSOFT1 QSOFT0 STATUS6 STATUS5 STATUS4 STATUS3
0001 ISOFT2 QSOFT2 MAG7 MAG6 MAG5 MAG4 MAG3 MAG2 MAG1 MAG0
0010 ISOFT2 ISOFT1 ISOFT0 QSOFT2 QSOFT1 QSOFT0 STATUS6 STATUS5 STATUS4 STATUS3
0011 ISOFT2 ISOFT1 ISOFT0 QSOFT2 QSOFT1 QSOFT0 STATUS6 STATUS5 STATUS4 STATUS3
0100 ISOFT2 ISOFT1 ISOFT0 QSOFT2 QSOFT1 QSOFT0 STATUS6 STATUS5 STATUS4 STATUS3
0101 ISOFT2 ISOFT1 ISOFT0 QSOFT2 QSOFT1 QSOFT0 STATUS6 STATUS5 STATUS4 STATUS3
0110 ISOFT2 ISOFT1 ISOFT0 QSOFT2 QSOF T1 QSOFT0 LKACC6 LKACC5 LKACC4 LKACC3
0111 ISOFT2 ISOFT1 ISOFT0 QSOFT2 QSOFT1 QSOFT0 Iend7 Iend6 Iend5 Iend4
1000 RSRVD7 RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 RSRVD0 STATUS5 STATUS6
0000 STATUS2 STATUS1 STATUS0 AGC7 AGC6 AGC5 AGC4 ACG3 AGC2 AGC1
0001 STATUS6 STATUS0 PHASE7 PHASE6 PHASE5 PHASE4 PHASE3 PHASE2 PHASE1 PHASE0
0010 STATUS2 STATUS1 STATUS0 FE7 FE6 FE5 FE4 FE3 FE2 FE1
0011 STATUS2 STATUS1 STATUS0 GE7 GE6 GE5 GE4 GE3 GE2 GE1
0100 STATUS2 STATUS1 STATUS0 TE7 TE6 TE5 TE4 TE3 TE2 TE1
0101 STATUS2 STATUS1 STATUS0 CARPE7 CARPE6 CARPE5 CARPE4 CARPE3 CARPE2 CARPE1
0110 LKACC2 LKACC1 LKACC0 LKCNT6 LKCNT5 LKCNT4 LKCNT3 LKCNT2 LKCNT1 LKCNT0
0111 Iend3 Iend2 Iend1 Qend7 Q end6 Qend5 Qend4 Qend3 Qend2 Qend1
1000 NCOCOS9 NCOCOS8 NCOCOS7 NCO COS6 NCOCOS5 NCOCOS4 NCOCOS3 NCOCOS2 NCOCOS1 NCOCOS0
TABLE 44. UPDATE READ REGISTER CONFIGURATION CONTROL REGISTER Microprocessor Interface. Allow 6 CLKs until the output holding register is stable for reading. TABLE 43. OUTPUT SELECTOR CONFIGURATION CONTROL REGISTER (Continued)
TABLE 45. INITIALIZE LOCK DETECTOR ( μP CONTROL MODE) CONTROL REGISTER Acquisition/Tracking Control Register; Table 38 on page 41). TABLE 46. TEST CONFIGURATION CONTROL REGISTER 31-16 Not Used No programming required. 15-6 Reserved Set to 0 for proper operation. of the NCO to a known value. 0 = Enable normal NCO operation. 1 = Zero phase accumulator feedback for test.
4 Zero Symbol Tracking
This bit is used to zero the lag accumulator in the Symbol Tracking Loop Filter. 0 = Enable normal loop filter operation.
3 Zero Carrier Loop Filter
This bit is used to zero the lag accumulator in the Carrier Loop Filter. 0 = Enable normal loop filter operation. 2-0 Reserved Set to 0 for proper operation. TABLE 47. STATUS 6-0 SIGNAL DESCRIPTIONS 6 Carrier Lock 0 = Lock Detector is not in locked state (Carrier Tracking Loop is not locked). 1 = Lock Detector has achieved the locked state (Carrier lock has been achieved).
5 Acquisition/Track
0 = Tracking Parameters currently being used by Tracking Loops. 1 = Acquisition Parameters currently being used by Tracking Loops.
3 Frequency Sweep
path of the Carrier Tracking Loop Filter (Defined for upper sideband signals). 0 = Up (Sweep increasing in frequency). 1 = Down (Sweep decreasing in frequency). 0 = AGC is at or below its upper limit. 1 = AGC is above its upper limit.
and without the root raised cosine filter in the HSP50210. TABLE 48. TABLE A
- Noise Bandwidth of RRC Filter is 0.492676.
FN3652.5 July 2, 2008 Absolute Maximum Ratings Thermal Information Operating Conditions Temperature Range Thermal Resistance (Typical, Note 7) θ JA°C/W http://www.intersil.com/pbfree/Pb-FreeReflow.asp Die Characteristics CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 7. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Power Supply Current I CCOP VCC = Max, CLK = 52.6MHz (Notes 8, 9) - 225 mA Standby Power Supply Current I CCSB VCC = Max, Outputs Not Loaded - 500 µA Input Leakage Current I I VCC = Max, Input = 0V or VCC -10 10 µA Output Leakage Current I O VCC = Max, Input = 0V or VCC -10 10 µA Clock Input High V IHC VCC = Max, CLK 3.0 - V Clock Input Low V ILC VCC = Min, CLK - 0.8 V Logical One Input Voltage V IH VCC = Max 2.0 - V Logical Zero Input Voltage V IL VCC = Min - 0.8 V Logical One Output Voltage V OH IOH = -400µA, VCC = Min 2.6 - V Logical Zero Output Voltage V OL IOL = 2mA, VCC = Min - 0.4 V Input Capacitance C IN fCLK = SCLK = 1MHz All measurements referenced to GND. TA = +25°C (Note 10) -1 0 p F Output Capacitance C OUT -1 0 p F NOTES: 8. Power supply current is proportional to frequency. Typical rating is 4mA/MHz. 9. Output load per test circuit and C L = 40pF. 10. Not tested, but characterized at initial design and at major process/design changes. Electrical Specifications VCC = 5.0V ±5%, TA = 0°C to +70°C (Commercial), TA = -40°C to +85°C (Industrial), (Note 11) Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER SYMBOL 52MHz UNITSMIN MAX CLK Period t CP 19 - ns CLK High t CH 7- n s CLK Low t CL 7- n s SERCLK High t SH 7- n s SERCLK Low t SL 7- n s HSP50210
FN3652.5 July 2, 2008 AC Test Load Circuit † Test head capacitance. Setup Time IIN9-0, QIN9-0, SYNC, FZ_CT, FZ_ST to CLK t DS 8- n s Hold Time IIN9-0, QIN9-0, SYNC, FZ_CT, FZ_ST FROM CLK t DH 1- n s Setup Time ISER, QSER, SSYNC to SERCLK t DSS 8- n s Hold Time ISER, QSER, SSYNC FROM SERCLK t DSH 0- n s Setup Time A0-2, C0-7 to Rising Edge of WR tWS 15 - ns Hold Time A0-2, C0-7 from Rising Edge of WR tWH 0- n s WR to CLK t WC 15 - ns (Note 13) SERCLK to CLK t SC 10 - ns (Note 13) CLK to AOUT9-0, BOUT9-0, COF, COFSYNC, SOF, SOFSYNC, SMBLCLK, HI/LO, SLOCLK, LKINT, THRES tDO -8n s Read Address Low to Data Valid t ADO -2 6n s CLK to Status Out on C0-7 t CDO -1 5n s WR High t WRH 16 - ns WR Low t WRL 16 - ns RD Low t RL 16 - ns RD LOW to Data Valid t RDO -1 5n s RD HIGH to Output Disable t ROD - 10 ns (Note 12) Output Enable t OE -8n s Output Disable Time t OD - 8 ns (Note 12) Output Rise, Fall Time t RF - 5 ns (Note 12) NOTES: Test VIH = 3.0V, VIHC = 4.0V, VIL = 0V. 12. Controlled via design or process parame ters and not directly tested. Characterized upon initial design and after major process and/or design changes. 13. Set-up time required to ensure action initiated by WR or SERCLK will be seen by a particular CLK. Electrical Specifications VCC = 5.0V ±5%, TA = 0°C to +70°C (Commercial), TA = -40°C to +85°C (Industrial), (Note 11) Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER SYMBOL 52MHz UNITSMIN MAX EQUIVALENT CIRCUIT CL † IOH 1.5V IOL DUT SWITCH S1 OPEN FOR ICCSB AND ICCOP HSP50210
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN3652.5 July 2, 2008 HSP50210 Plastic Leaded Chip Carrier Packages (PLCC) NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0 .25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. -C- A SEATING PLANE 0.020 (0.51) MIN VIEW “A” D2/E2 0.025 (0.64) 0.045 (1.14) R 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP EE1 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER CL D 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. 0.004 (0.10) C -C- D2/E2 CL N84.1.15 (JEDEC MS-018AF ISSUE A)
84 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 1.185 1.195 30.10 30.35 - D1 1.150 1.158 29.21 29.41 3 D2 0.541 0.569 13.75 14.45 4, 5 E 1.185 1.195 30.10 30.35 - E1 1.150 1.158 29.21 29.41 3 E2 0.541 0.569 13.75 14.45 4, 5 N8 4 8 4 6 Rev. 2 11/97