HSP50110

HSP50110 RENESAS | Alldatasheet

Document overview

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• PDF pages: 25

Technical content

Features

• Input Sample Rates to 52MSPS
• Internal AGC Loop for Output Level Stability
• Parallel or Serial Output Data Formats
• 10-Bit Real or Complex Inputs
• Bidirectional 8-Bit Microprocessor Interface
• Frequency Selectivity <0.013Hz
• Low Pass Filter Configurable as Three Stage Cascaded- Integrator-Comb (CIC), Integrate and Dump, or Bypass
• Fixed Decimation from 1-4096, or Adjusted by NCO Synchronization with Baseband Waveforms
• Input Level Detection for External IF AGC Loop
• Designed to Operate with HSP50210 Digital Costas Loop
• 84 Lead PLCC

Applications

• Satellite Receivers and Modems
• Complex Upconversion/Modulation
• Tuner for Digital Demodulators
• Digital PLLs
• Related Products: HSP50210 Digital Costas Loop; A/D Products HI5703, HI5746, HI5766
• HSP50110/210EVAL Digital Demod Evaluation Board Block Diagram

Ordering Information

TEMP. RANGE (oC) PACKAGE PKG. NO. HSP50110JC-52 0 to 70 84 Ld PLCC N84.1.15 HSP50110JI-52 -40 to 85 84 Ld PLCC N84.1.15 LEVEL DETECT NCO RE-SAMPLING 90o LOW PASS FIR FILTER DUMP INTERFACE PROGRAMMABLE CONTROL I DATA Q DATA CARRIER SAMPLE RATE TRACKING CONTROL CONTROLCONTROL/STATUS SAMPLE STROBE LOOP FILTER GCA REAL OR COMPLEX INPUT DATA IF AGC CONTROL BUS NCO GCA LOW PASS FIR FILTER LEVEL DETECTCOMPLEX MULTIPLIER NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc

FN3651 Rev 6.00 Page 2 of 25 March 2001 Pinout HSP50110 (PLCC) TOP VIEW Pin Descriptions NAME TYPE DESCRIPTION VCC - +5V Power Supply. GND - Ground. IIN9-0 I In-Phase Input. Data input for in-phase (real) samples. Format may be either two’s complement or offset binary format (see I/O Formatting/Control Register in Table 9). IIN9 is the MSB. QIN9-0 I Quadrature Input. Data input for quadrature (imaginary) samples. Format may be either two’s complement or offset bi- nary format (see I/O Formatting/Control Register in Table 9). QIN9 is the MSB. ENI I Input Enable. When ENI is active ‘low’, data on IIN9-0 and QIN9-0 is clocked into the processing pipeline by the rising edge of CLK. This input also controls the internal data process ing as described in the Input Controller Section of the data sheet. ENI is active ‘low’. PH1-0 I Carrier Phase Offset. The phase of the internally generated carrier frequency may be shifted by 0, 90, 180, or 270 de- grees by controlling these pins (see Synthesizer/Mixer Section). The phase mapping for these inputs is given in Table 1. CFLD I Carrier Frequency Load. This i nput loads the Carrier Frequency Register in the Synthesizer NCO (see Synthesizer/Mixer Section). When this input is sampled ‘high’ b y clock, the contents of the Microprocessor Interface Holding Registers are transferred to the carrier frequency regi ster in the Synthesizer NCO (see Microprocessor Inter - face Section). NOTE: This pin must be ‘low’ when loading other configuration data via the Microprocessor In- terface. Active high Input. COF I Carrier Offset Frequency Input. This serial input is used to load the Carrier Offset Frequency into the Synthesizer NCO (see Serial Interface Section). The new offset frequency is shifted in MSB first by CLK starting with the clock cycle after the assertion of COFSYNC. COFSYNC I Carrier Offset Frequency Sync. This signal is asserted one CLK cycle before the MSB of the offset frequency data word (see Serial Interface Section). 1 11 0 9 8 7 6 5 4 3 2 1 8 48 38 28 18 07 97 87 77 67 5 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 IOUT4 IOUT5 IOUT6 GND IOUT7 IOUT8 IOUT9 OEI LOTP SPH0 SPH1 SPH2 SPH3 V CC SPH4 SSTRB HI/LO IIN9 IIN8 IIN7 IIN6 GND SOFSYNC SOF COFSYNC COF V CC GND RD WR CFLD IIN5 IIN4 IIN3 IIN2 GND IIN1 IIN0 ENI QIN9 QIN8 QIN7 QIN6 QIN5 QIN4 V CC QIN3 QIN2 QIN1 QIN0 PH1 PH0 IOUT1 IOUT3 IOUT2 IOUT0 DATARDY V CC CLK GND QOUT9 QOUT8 QOUT7 QOUT6 QOUT5 GND QOUT4 QOUT2 QOUT1 QOUT0 OEQ VCC QOUT3

FN3651 Rev 6.00 Page 3 of 25 March 2001 SOF I Sampler Offset Frequency. This serial input is used to load the Sampler Offset Frequency into the Re-Sampler NCO (see Serial Interface Section). The new offset frequency is shifted in MSB first by CLK starting with the clock cycle after assertion of SOFSYNC. SOFSYNC I Sampler Offset Frequency Sync. This signal is asserted one CLK cycle before the MSB of Sampler Offset Frequency data word (see Serial Interface Section). A2-0 I Address Bus. These inputs specify a target register within the Microprocessor Interface (see Table 5). A2 is the MSB. This input is setup and held to the rising edge of WR. C7-0 I/0 Control Bus. This is the bidirectional data bus for reads and writes to the Microprocessor Interface (see Microprocessor Interface Section). C7 is the MSB. WR I Write. This is the write strobe for the Microprocessor Interface (see Microprocessor Interface Section). RD I Read. This is the read enable for the Microprocessor Interface (see Microprocessor Interface Section). IOUT9-0 O In-Phase Output. The data on these pins is output synchronous t o CLK. New data on IOUT9-0 is indicated by the as - sertion of the DATARDY pin. Data may be output parallel or serial mode (see Output Formatter Section). In the parallel mode, IOUT9 is the MSB. When the serial mode is used, IOUT0 is data, and IOUT9 is the serial clock. Other pins not used in serial mode may be set high or low via the control interface. QOUT9-0 O Quadrature Output. The data on these pins is output synchronous to CLK. New data on the QOUT(9-0) pins is indicated by the DATARDY pin. Data may be output parallel or serial mode. In the parallel mode, IOUT9 is the MSB. When the serial mode is used, QOUT0 is data. DATARDY O Data Ready. This output is asserted on the first clock cycle th at new data is available on the IOUT and QOUT data busses (see Output Formatter Section). This pin may be active ‘high’ or ‘low’ depending on the configuration of the I/O Formatting/Control Register (see Table 9). In serial mode, DATARDY is asserted one IQ clock before for first bit of serial data. OEI I In-Phase Output Enable. This pin is the three-state control for IOUT9-0. When OEI is ‘high’, the IOUT bus is held in the high impedance state. OEQ I Quadrature Output Enable. This pin is the three-state control for QOUT9-0. When OEQ is ‘high’, the QOUT bus is held in the high impedance state. LOTP 0 Local Oscillator Test Point. This output is the MSB of the Synthesizer NCO phase accumulator (see Synthesizer/Mixer Section). This is provided as a test point for monitoring the frequency of the Synthesizer NCO. SSTRB 0 Sample Strobe. This is the bit rate strobe for the bit rate NCO. SSTRB has two modes of operation: continuous update and sampled. In continuous update mode, this is the carry output of the Re-Sampler NCO. In sampled mode, SSTRB is active synchronous to the DA TARDY signal for parallel output mode. The sampled mode is provided to signal the nearest output sample aligned with or following the symbol boundary. This signal can be used with SPH(4-0) below to control a resampling filter to time shift its impulse response to align with the symbol boundaries. SPH4-0 0 Sample Phase. These are five of the most significant 8 bits of the Re-Sampler NCO phase accumulator. Which five bits of the eight is selected via the Chip Configuration Register (s ee Table 11). These pins update continuously when the SSTRB output is in the continuous update mode. When the SSTRB pin is in the sampled mode, SPH4-0 update only when the SSTRB pin is asserted. In the sampled mode, these pins indicate how far the bit phase has advanced past the symbol boundary when the output sample updates. SPH4 is the MSB. HI/LO 0 HI/LO. The output of the Input Level Detector is provided on this pin (see Input Level Detector Section). The sense of the HI/LO pin is set via the Chip Configuration Register (see Table 11). This signal can be externally averaged and used to control the gain of an amplifier to close an AGC loop around the A/D converter. This type of AGC sets the level based on the median value on the input. CLK I Clock. All I/O’s with the exception of the output enables and the microprocessor interface are synchronous to clock. Pin Descriptions (Continued) NAME TYPE DESCRIPTION

on the HSP50210 Digital Costas Loop. gain and gain limits are programmable. FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF HSP50110

which improves the time resolution of the processing chain. value detector with negligible error. FIGURE 2. SYNTHESIZER NCO

quadrature outputs whose phase advances from 0o to 360o. sample rate is equal to the CLK rate. Microprocessor Interface Section and the Serial Input Section. Register would produce a phase offset of 45o. despreading of CDMA signals. to produce gain correction (see Figure 4). TABLE 1. PH0-1 INPUT PHASE MAPPING

portion of the limit set a gain range from 0 to ~48dB. lower limits to the same value. Figure 3. The loop gain is added or subtracted from the accumulator depending on the output of the Level Detector. Gains between 01(HEX) and FF (HEX) respectively. loop delay for different matched filter configurations.

0 TO 7

FIGURE 3. BINARY FORMAT FOR LOOP FILTER This Value Can Be Read By The Microprocessor. See The Microprocessor Interface Section. † Indicates data downloaded via microprocessor interface. FIGURE 4. AGC BLOCK DIAGRAM FIGURE 5. GAIN CONTROL TRANSFER FUNCTION

1. The uncompensated I & D (1st order CIC) filter yields about
2. The compensated I & D filter offers a flatter, wider bandwidth

quency roll off due to the A/D converter.

1. The uncompensated 3rd order CIC filter yields over 60dB of
2. The 3rd order CIC with compensation yields alias suppres-

accurately reflect the digital filter performance. Table 3. These noise bandwidths are provided so that output this bandwidth indicates the detection bandwidth. output represents the decimation factor. Table 10 Decimating Filter Configuration Register). based on whether a fixed or adjustable sample rate is desired. TABLE 3. DOUBLE SIDED NOISE EQUIVALENT BANDWIDTH

the decimation factor would be 320. decimation factors up to 4096. frequency (see Input Controller Section). are output simultaneously at rates up to the maximum CLK. Figure 14. Output enables (OEI, OEQ) are provided to

10 MSBs of the serial word, and the I sample is differentiated

† Controlled via microprocessor interface. FIGURE 13. RE-SAMPLER NOTE: DATARDY may be programmed active high or low. FIGURE 14. PARALLEL OUTPUT TIMING

output SNR or ES/N0 specification. Table 4 to show how the DQT’s gain settings can be derived. rate (i.e., there are 2 samples per symbol). system parameters are given in Table 4. TABLE 4. EXAMPLE SYSTEM PARAMETERS

1. Two samples per symbol assumed.
2. Decimation = 40 MSPS/32 KSPS = 1250.

FN3651 Rev 6.00 Page 14 of 25 March 2001 Thus, the minimum input signal will be -21.66dB below full scale (-9.66 -12 for A/D Backoff). As before the maximum input signal in the absence of noise is -12dB down due to A/D backoff. From Equation 14, the gain relationships for maximum and minimum input can be written as follows: Min Input Level -6.02dB  -21.66 -6.02 - 216.74 + GAGC + GSHIFTER + Max Input Level -6.02dB  -12 - 6.02 - 216.74 + GAGC + GSHIFTER + 20 x log((40 x 106/32 x 103)3) -2.27 (EQ. 22) Using the upper and lower limits found above, the gain range can be expressed as, 45.20dB < GAGC + GSHIFTER < 54.86dB. (EQ. 23) Using Equation 2 in the previous example, the shifter gain is determined to be 27, resulting in an AGC gain range of 3.05dB < GAGC <12.72dB. (EQ. 24) Basic Architectural Configurations Detailed architectural diagrams are presented in Figures 18 through 20 for the basic configurations, Integrate/Dump filtering with optional compensation, 3rd Order CIC filtering with optional compensation, and Decimating Filter bypass. Only one of the data paths is shown since the processing on either the inphase or quadrature legs is identical. These diagrams are useful for determining the throughput pipeline delay or the loop delay of the AGC as all the internal registers are shown. All registers with the exception of those denoted by daggers ( †) are enabled every CLK rate to minimize pipeline latency. The registers marked by daggers are enabled at the output sample rate as required by the filtering operation performed. The Loop Filter accumulator in the AGC is enabled once per output sample, and represents a delay of one output sample. The accumulators in the CIC filter each represent a delay of one CLK, but they are enabled for processing once per input sample. In Interpolated Input Mode the accumulators are enabled every CLK since the sample rate is determined by the CLK rate (see Input Controller Section). In Gated Input Mode, the processing delay of the accumulators is one CLK but they are only enabled once for each sample gated into the processing pipeline. As a result, the latency through the accumulators is 3 CLKs rather than 3 input sample periods when configured as a 3rd order CIC filter.

FIGURE 18. DATA FLOW FOR INTEGRATE/DUMP CONFIGURATION FIGURE 19. DATA FLOW FOR 3RD ORDER CIC CONFIGURATION FIGURE 20. DATA FLOW WITH CIC STAGE BYPASSED

11 TAP

15 TAP

TABLE 6. CENTER FREQUENCY REGISTER Format: [XXXXXXXX]H Range: (0000000 - FFFFFFF)H. TABLE 7. SAMPLER CENTER FREQUENCY REGISTER Format: [XXXXXXXX]H Range: (0000000 - FFFFFFF)H. TABLE 7. INPUT THRESHOLD REGISTER This register sets the magnitude threshold for the Input Level Detector (see Input Level Detector Section). TABLE 8. AGC CONTROL REGISTER . Threshold values of greater than 1.4142 will force the AGC gain to the upper limit. to bit positions 15-13 (15 is the MSB) and the five mantissa bits map to bit positions 12-8 (12 is the MSB). bits map to bit positions 20-16 (20 is the MSB). (EEE.MMMMM)2. gain is loaded into bit positions 31-24 (31 is the MSB and maps to the 2-6 position in the Accumulator).

• –== SamplerCenter Frequency SCF H FNCO FS H SCOF H.–== I2 Q2+ 2 1.4142==

TABLE 9. I/O FORMATTING/CONTROL 0 Input Format 0 = Two’s complement input format, 1 = Offset binary input format. 1 Input Mode 0 = Input Controller operates in Interpolated Input Mode. 1 = Input Controller operates in Gated Input Mode. (See Input Controller Section).

2 Serial/Parallel Output

1 = Serial Output, 0 = Parallel Output. (See Output Formatter Section). 3 Test Enable 0 = Test Mode Disabled, 1 = Test Mode Enabled. (See Test Mode Section). (See Output Formatter Section).

7 Serial Output Word 

1 = MSB First, 0 = LSB First. 8 Output Data Format 1 = Offset Binary, 0 = Two’s Complement. 9 DATARDY Polarity 1 = Active Low, 0 = Active High. This applies to both serial and parallel output modes. (See Output Formatter Section). 10 Output Clock Polarity 1 = High to Low clock transition at midsample. 0 = Low to High clock transition at midsample. TABLE 10. DECIMATING FILTER CONFIGURATION REGISTER range of the filter. (See Gain Distribution Section).

18 Programmable 

1 = Divider clocked at sample rate of data input to the Low Pass Filter. 0 = Divider clocked by Re-Sampler NCO. 0 1 1 stage CIC (Integrate and dump) filter. to set the output sampling rate. (See Re-Sampler Section and Low Pass Filtering Section). 1 X bypass compensation filter. (See Low Pass Filtering Section).

TABLE 11. CHIP CONFIGURATION REGISTER 0 HI/LO Output Sense 1 = HI/LO output of 1 means input > threshold. 0 = HI/LO output of 1 means input  threshold. (See Input Level Detector Section). 1 AGC Disable 1 = AGC disabled, gain forced to 1.0 (0dB), 0 = Normal operation.

2 AGC Level Detector

1 = Error signal is 1 when output > threshold, -1 otherwise. 0 = Error signal is -1 when output > threshold, 1 otherwise. Set to 0 for normal operation. (See AGC Section). (See Synthesizer/Mixer Section).

7 Carrier Offset

1 = Enable Offset Frequency, 0 = Zero Offset Frequency. (See Synthesizer/Mixer Section).

8 Sample Rate Offset

1 = Enable Offset Frequency, 0 = Zero Offset Frequency. 9 Load Synthesizer NCO 1 = Accumulation enabled. 0 = Feedback in accumulator is zeroed. (See Synthesizer/Mixer Section) Set to 1 for normal operation. 10 Load Re-Sampler NCO 1 = Accumulation enabled. 0 = Feedback in accumulator is zeroed. (See Re-Sampler Section) Set to 1 for normal operation.

13 Sample Phase 

DATARDY is active. (See Re-Sampler Section). remain at 0 until a 0 is written to this bit. The following accumulators are affected by this bit.

• Carrier NCO Accumulator
• Cascode CIC Filter Accumulator
• AGC Loop Filter Accumulator
• Serial Output Shifter Counter
• Serial Output Clock Logic
• ReSampler NCO Carry Output Programmable Divider 31-15 Reserved.

TABLE 10. DECIMATING FILTER CONFIGURATION REGISTER (Continued)

Processing, Vol. ASSP-29 No. 2, April 1981. TABLE 12. PHASE OFFSET REGISTER TABLE 13. TEST REGISTER 4 maps to SPH4. (See Test Mode Section). 5 Force SSTRB When Test Mode enabled*, SSTRB is forced to state of this bit. 6 Force HI/LO When Test Mode enabled*, HI/LO is forced to state of this bit. 17 Force DATARDY When Test Mode enabled*, DATARDY is forced to state of this bit. 18 Force LOTP When Test Mode enabled*, LOTP is forced to state of this bit.

• Test Mode Enable is Destination Address = 4, bit-3.

TABLE 14. AGC SAMPLE STROBE REGISTER processor Interface Section).

FN3651 Rev 6.00 Page 22 of 25 March 2001 Absolute Maximum Ratings Thermal Information (Typical) Operating Conditions Temperature Range Thermal Resistance (Typical, Note 3) JA (oC/W) (PLCC - Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Power Supply Current ICCOP VCC = Max, CLK = 52.6MHz Notes 4, 5 - 350 mA Standby Power Supply Current ICCSB VCC = Max, Outputs Not Loaded - 500 A Input Leakage Current II VCC = Max, Input = 0V or VCC -10 10 A Output Leakage Current IO VCC = Max, Input = 0V or VCC -10 10 V Clock Input High VIHC VCC = Max, CLK 3.0 - V Clock Input Low VILC VCC = Min, CLK - 0.8 V Logical One Input Voltage VIH VCC = Max 2.0 - V Logical Zero Input Voltage VIL VCC = Min - 0.8 V Logical One Output Voltage VOH IOH = -400A, VCC = Min 2.6 - V Logical Zero Output Voltage VOL IOL = 2mA, VCC = Min - 0.4 V Input Capacitance CIN CLK = 1MHz All measurements referenced to GND. TA = 25oC, Note 6 - 10 pF Output Capacitance COUT - 10 pF NOTES: 4. Power supply current is proportional to frequency. Typical rating is 7mA/MHz. 5. Output load per test circuit and CL = 40pF. 6. Not tested, but characterized at initial design and at major process/design changes. PARAMETER SYMBOL NOTES -52 (52.6MHz) UNITSMIN MAX CLK Period TCP 19 - ns CLK High TCH 7 - ns CLK Low TCL 7 - ns Setup Time IIN9-0, QIN9-0, ENI, PH1-0, CFLD, COF, SOF, COFSYNC, and SOFSYNC to CLK TDS 7 - ns Hold Time IIN9-0, QIN9-0, ENI, PH1-0, CFLD, COF, SOF, COFSYNC, and SOFSYNC from CLK TDH 1 - ns Setup Time A0-2, C0-7 to Rising Edge of WR TWS 15 - ns Hold Time A0-2, C0-7 from Rising Edge of WR TWH 0 - ns

FN3651 Rev 6.00 Page 23 of 25 March 2001 AC Test Load Circuit CLK to IOUT9-0, QOUT9-0, DATARDY, LOTP, SSTRB, SPH4-0, HI/LO TDO - 8 ns WR High TWRH 16 - ns WR Low TWRL 16 - ns RD Low TRDL 16 - ns RD LOW to Data Valid TRDO - 15 ns RD HIGH to Output Disable TROD Note 8 - 8 ns Output Enable TOE - 8 ns WR to CLK TWC Note 9 8 - ns Output Disable Time TOD Note 8 - 8 ns Output Rise, Fall Time TRF Note 8 - 3 ns NOTES: Test VIH = 3.0V, VIHC = 4.0V, VIL = 0V. 8. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes. 9. Set time to ensure action initiated by WR or SERCLK will be seen by a particular clock. PARAMETER SYMBOL NOTES -52 (52.6MHz) UNITSMIN MAX EQUIVALENT CIRCUIT CL † IOH 1.5V IOL DUT SWITCH S1 OPEN FOR ICCSB AND ICCOP † Test head capacitance.

FN3651 Rev 6.00 Page 25 of 25 March 2001 HSP50110 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2001. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Plastic Leaded Chip Carrier Packages (PLCC) NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane contact point. 5. Centerline to be determined w here center leads exit plastic body. 6. “N” is the number of terminal positions. -C- A SEATING PLANE 0.020 (0.51) MIN VIEW “A” D2/E2 0.025 (0.64) 0.045 (1.14) R 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP EE1 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER CL D 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. 0.004 (0.10) C -C- D2/E2 CL N84.1.15 (JEDEC MS-018AF ISSUE A)

84 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 1.185 1.195 30.10 30.35 - D1 1.150 1.158 29.21 29.41 3 D2 0.541 0.569 13.75 14.45 4, 5 E 1.185 1.195 30.10 30.35 - E1 1.150 1.158 29.21 29.41 3 E2 0.541 0.569 13.75 14.45 4, 5 N8 4 8 4 6 Rev. 2 11/97