HSP50016

HSP50016 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

• 75 MSPS Input Data Rate
• 16-Bit Data Input; Offset Binary or 2’s Complement Format
• Spurious Free Dynamic Range Through Modulator >102dB
• Frequency Selectivity: <0.006Hz
• Identical Lowpass Filters for I and Q
• Passband Ripple: <0.04dB
• Stopband Attenuation: >104dB
• Filter -3dB to -102dB Shape Factor: <1.5
• Decimation Factors from 32 to 131,072
• IEEE 1149.1 Test Access Port
• HSP50016-EV Evaluation Board Available

Applications

• Cellular Base Stations
• Smart Antennas
• Channelized Receivers
• Spectrum Analysis
• Related Products: HI5703, HI5746, HI5766 A/Ds Block Diagram

Ordering Information

TEMP. RANGE (oC) PACKAGE PKG. NO. HSP50016JC-52 0 to 70 44 Ld PLCC N44.65 HSP50016JC-75 0 to 70 44 Ld PLCC N44.65 HSP50016GC-52 0 to 70 48 Ld CPGA G48.A COMPLEX SINUSOID GENERATOR DATA HIGH DECIMATION FILTER HIGH DECIMATION FILTER LOW PASS FIR FILTER LOW PASS FIR FILTER COS SIN I Q CONTROL TEST ACCESS PORT/CTRL OUTPUT FORMATTER OUTPUT I Q CLK TEST ACCESS PORT CLK CLK R CLK OR CLK 2R CLK SER IQSTRB IQCLK Data Sheet February 1999 File Number 3288.6 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

48 PIN CPGA

44 LEAD PLCC

Q DATA6 DATA5 DATA4 DATA3 VCC CLK GND DATA2 DATA1DATA0 VCC GND TDI TDO TRST CDATACS CSTB CCLK VCC GND DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 VCC GND RESETTCK TMS VCC VCC VCC GND VCC GND VCC GND 1 23 678 A B C D E F G H IQSTB IQSTR T IQCLK Q DATA6 DATA5 DATA4 DATA3 VCC CLK GND DATA2 DATA1DATA0 VCC GND TDI TDO TRST CDATACS CSTB CCLK VCC GND DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 VCC GND RESETTCK TMS VCC VCC VCC GND VCC GND VCC GND 1 23 678 A B C D E F G H I 44 43 42 41 40 2827 123456 20 21 22 23 24 25 261918 VCC GND TDI TRST TDO VCC TMS TCK RESET GND VCC GND DATA15 DATA14 DATA13 DATA12 GND DATA11 DATA10 DATA9 DATA8 DATA7 V CC DATA6 DATA5 DATA4 DATA3 V CC GND CLK DATA2 DATA1 DATA0 GND Q I IQCLK IQSTR T IQSTB CDATA CS CSTB CCLK V CC HSP50016

VCC - +5V Power. GND - Ground. DATA0-15 I Input Data Bus. Selectable between two's complement and offset binary. DATA0 is the LSB. CLK I Clock for input data bus. f S is the frequency of CLK, which is also the input sample rate. RESET I RESET initializes the internal state of the DDC. DuringRESET, all internal processing stops.RESET facilitates the synchronization of multiple chips for Auto Three-State operation. If the Force bits in Control Word 7 are inactive and the IEEE Test Access Port is in an Idle state, RESET causes the IQCLK, IQSTB, I and Q outputs to go to a high impedance state. All Control Registers are updated from their respective Control Buffer Registers on the third rising edge of CLK after the deassertion ofRE SET. IfRESET is deasserted tRS nanoseconds prior to the rising edge of CLK, the internal reset will deassert synchronously. If tRS is violated, then the circuit contains a syn- chronizer which will cause reset to be deasserted internally one or more clocks later. An initial reset is required to guarantee proper operation of the DDC. Active low. I O The I output has three modes: I data; I data followed by Q data; real data. Q O The Q output has two modes: Q data and the carry out of the Phase Adder. IQCLK O IQ Clock: Bit or word clock for the I and Q outputs. IQSTB O IQ Strobe: Beginning or end of word indicator for I and Q. IQSTR T I IQ Start: Initiates output data sequence. Active low. CDATA I Control Data: Port for control data input. CCLK I Control Data Clock: Control data input bit clock. CSTB I Control Data Strobe: Beginning of word indicator for control data. CS I Chip Select: Enables control data loading of DDC. Active low. TCK I Test Clock: Bit Clock for IEEE 1149.1 Data. This signal should be either tied low or pulled high when the TAP is not used. TMS I Test Port Mode Select: This signal should be either left unconnected or pulled high when the TAP is not used. TDI I Test Data Input for IEEE Test Port: This signal should be either left unconnected or pulled high when the TAP is not used. TDO O Test Data Output for IEEE Test Port: This output will be in the high impedance state when the TAP is not used. TRST I Test Port Reset. Active Low. This signal should be tied low when the TAP is not used. HSP50016

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM † Indicates parameters from control registers.

output to provide the data in a variety of serial data formats. FIGURE 2. PHASE GENERATOR BLOCK DIAGRAM † Indicates parameters set in Control Registers.

Phase Increment Register is added to the 24 LSBs of the output of the Phase Increment Register. On the next CLK, that sum is stored back in the Phase Increment Register, the new phase is stored in the Phase Register and the process is repeated. The phase increment is allowed to grow until the next phase increment would equal or exceed the maximum phase increment value. When this happens, the Phase Increment Register is reset to the minimum phase increment and the cycle starts over again. NOTE: The phase increment is never equal to the maximum phase increment, since the Phase Increment Register is reloaded if the next phase increment value would be greater than the maximum phase increment. From the time the Phase Generator starts at the minimum phase increment until it reaches the maximum phase increment, the phase word on clock n is given by: An example of the outputs of the Phase Increment Register, Phase Register, and the I output of the SIN/COS Generator are shown in Figure 4B. In Down Chirp Mode the local oscillator generates a signal with a linearly decreasing frequency (Figure 5A). The maximum phase increment is loaded into the Phase Increment Register and the phase offset value goes into the Phase Register. The delta phase increment is subtracted from the 24 LSBs of the phase increment to form a new phase increment at each clock. The phase increment is allowed to diminish until it reaches the minimum phase increment value, then it is reset to the maximum phase increment value and the cycle is repeated. Note that the value of the phase increment can be equal to, but never less than the minimum phase increment, since the Phase Increment Register is reloaded if the next phase increment value would be less than the minimum phase increment. This feature protects the DDC from exceeding the Nyquist frequency. In this case, from the time the Phase Generator starts at the maximum phase increment until it reaches the minimum phase increment, the phase word on clock n is given by: See Figure 5B for a graphical representation of this process. Phase Word Phase Offset - Minimum Phase Increment n (Delta Phase Increment)+ = (EQ. 2) Phase Word Phase Offset -[Minimum Phase Increment n (Delta Phase Increment)]– = (EQ. 3) FIGURE 4A. PHASE WORD DURING UP CHIRP FIGURE 4B. UP CHIRP STARTING PHASE +90o ±180o -90o θINCR θINCR +θΔ (0) (1) (2) (3) (4)(5) θOFFSET θINCR +2θΔ θINCR +3θΔ θINCR +4θΔ θINCR (6) θINCR +θΔ (7) θINCR +2θΔ START NEW RAMP θINCR +5θΔ >θMAX INCR (8) IF THEN MAXIMUM MINIMUM PHASE INCREMENT TIME PHASE PHASE WORD TIME COSINE OUTPUT OF SIN/COS GENERATOR TIME OFFSET HSP50016

number with 37 fractional bits. where FS = CLK; R = HDF Decimation Factor. where FS = CLK; R = HDF Decimation Factor. FIGURE 9. FIR COMPENSATION FOR HDF ROLL OFF (FOR R = 16) TABLE 1. FIR OUTPUT RATE AND DECIMATION

Note that Equation 15 is useful in all modes for calculating the number of IQCLKs necessary to complete one output data cycle. For a given decimation rate and output word length, the maximum value in the IQCLK Rate field is: where Floor(X) represents the integer part of X, R is the HDF decimation factor, 4 is the FIR decimation factor. Example Clock Calculations Clarification of the use of Equations 14-16, the calculation of the HDF and FIR clocks and the calculation of the IQCLK is best done by example: The HDF Decimation Factor, R, is 100 (which makes the The desired number of output bits is 32. 1. We begin by identifying the HDF Input Rate: 2. Next we calculate the HDF Output Rate: HDF Output Rate = CLK/R = 10MHz/(100) = 100kHz 3. Next we calculate the FIR output Rate: FIR Output Rate = CLK/4R = 25kHz. 4. Next we calculate the minimum time slot length: Equation 15: Length MIN = [(Number of Output Bits + 2) x Mode] +1 where the number of output bits = 32 and the Mode is 2 because of the I followed by Q output selection. Length MIN = [(32 + 2) x 2] +1 = 69 IQCLKs 5. Next we calculate the IQCLK frequency: IQCLK frequency = [( FS )(LengthMIN )/(R)(4)] - 1 IQCLK frequency = [(10MHz)(69)/(100)(4)] - 1 = 1.725MHz The IQCLK frequency can be no slower than 1.725MHz if all of the bits are to be output of the DDC in a time slot. 6. The Programmed value for the maximum IQCLK Rate, from Equation 16, is: IQCLKRATE MAX = Floor[(R) x 4/ LengthMIN ] -1 IQCLKRATE MAX = Floor[(100 x 4)/69] - 1 = 4 The IQCLKRATE can be not greater than 4 if all of the bits are to be output of the DDC in a time slot. [00004]H; 0 0000 0000 0100 LSB 7. Let’s sanity check with Equation 14. IQCLK Rate = [(CLK/IQCLKfreq)-1] = [10E6/1.725E6] -1 = 4. This checks! Control Word Input The DDC has eight 40-bit control words which are loaded through the four pin control interface. The format and timing of this interface is compatible with the serial interface timing of most common DSP microprocessors (see Figure 14). The words are shifted MSB first, where bit 39 of the control word is the MSB. Bits 39 through 37 are the control word address, i.e., the target control buffer. CS must go low before bit 35 is clocked in. All 40 bits of the control word must be loaded. The formats of the control words are shown in Tables 3 through 10. The control words are double buffered: each control word is initially loaded into one of eight control buffers for subsequent down loading into the corresponding Control Register. The internal circuitry of the DDC uses the Control Registers to regulate its operation. Control buffers can be downloaded in one of two ways. Loading a Buffer Register with bit 36 = 1 causes all Control Registers to be updated from their respective control buffers when the current word is finished loading. If bit 36 = 0, then only that control buffer is updated and the operation of the DDC is not affected. All Control Registers are updated from their respective buffers on the third rising edge of CLK following the deassertion of RESET. NOTE: Control Word 0 is unique in that it is only used to update the seven Control Registers, and it is recognized by the DDC regardless of the state of CS. In systems with multiple DDCs, this allows the user to update the configuration of all chips simultaneously without using RESET. To ensure that the control information is properly loaded, the frequency of CLK must be greater than the frequency of CCLK. In addition, RESET must remain inactive during the loading of a control word. IQCLKRate MAX Floor R() 4× Length MIN HSP50016

TABLE 3. DESTINATION ADDRESS = 0

36 Update 0 = Update Only This Control Register

TABLE 4. PHASE GENERATOR/TEST ENABLE/OUTPUT REGISTER is the control word value in hexidecimal. In the CHIRP modes, this is the smallest allowable phase increment. In the Filter Only mode, this parameter should be set to 0.

3 Test Enable 0 = Test Features Disabled

TABLE 5. PHASE GENERATOR REGISTER to 0 in the Filter Only and CW modes. TABLE 6. PHASE GENERATOR/OUTPUT TIME SLOT REGISTER

TABLE 7. PHASE GENERATION/HDF.OUTPUT REGISTER 16-Bit HDF Gain Compensation Number - the shift portion.

0 Spectral Reverse 0 = Normal Output

TABLE 8. HDF/OUTPUT REGISTER HDF DCP = R - 1;where R is the HDF decimation (rate change) factor.

16-Bit HDF Gain Compensation Number - the multiplier portion. ING(x) is equal to x for integer values, otherwise is equal to the next higher integer. Note that the Scale Factor is 1 (8000hex) for power of 2 decimation factors. increases towards 2 again as the Decimation Factor increases. TABLE 8. HDF/OUTPUT REGISTER (Continued)

0 Output Sense 0 = LSB First

TABLE 8. HDF/OUTPUT REGISTER (Continued) TABLE 9. INPUT AND OUTPUT FORMAT REGISTER

35 I followed by Q 0 = I and Q Output Separately

This implies that 64 different channels may be mutliplexed, assigning one time slot per channel.

28 IQCLK

27 IQCLK Duty Cycle 0 = IQCLK Active Time = CLK Period.

26 IQCLK

23 IQSTB

22 IQSTB

0 = IQSTB Prior to the Beginning of the Data Word. 1 = IQSTB During the Data Word.

19 I Polarity 0 = True Data

16 Q Polarity 0 = True Data

13 Input Format 0 = Offset Binary

Range: 2≤ IQCLK Rate Counter Preload≤ 1701. represents the integer part of x, and TSL is the decimal value of Control Word 3, bit 31-18. TABLE 9. INPUT AND OUTPUT FORMAT REGISTER (Continued) TABLE 10. PHASE OFFSET REGISTER

13 Data 0 = Normal Data Input

1 = Force Input Data to 8000 Hex. 00 = Normal Accumulation - The accumulator is reset on every FIR cycle. 01 = No Accumulation -The accumulator is disabled. is not functioning properly.

10 Q Strobe on Roll Over 0 = Q carries Normal Data

9 Force Outputs 0 = Normal Output Response

8 IQCLK Forced Data If Bit 9 = 1, Force IQCLK = Bit 8; Else Normal

7 IQSTB Forced Data If Bit 9 = 1, Force IQSTB = Bit 7; Else Normal. 6 I Forced Data If Bit 9 = 1, Force I = Bit 6; Else Normal. 5 Q Forced Data If Bit 9 = 1, Force Q = Bit 5; Else Normal.

4 Sin/Cos Generator

3 Scaling Multiplier

2 Reserved Must be Zero for Proper Operation while Test Features are Enabled. RAMs. If Bit = 1, No Chip Output will Occur until Sufficient Data RAM Locations are Written.

0 Disable Overflow Pro-

TABLE 11. SAMPLE FORMAT FOR CONTROL WORD 1 - 39-37 Address 001 = Control Word 1. 36 Update 1 = Control Register Update. 3 Test Enable 0 = Test Features Disabled.

0011 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0001

TABLE 12. SAMPLE FORMAT FOR CONTROL WORD 2 - 39-37 Address 010 = Control Word 2. 36 Update 1 = Control Register Update. FIGURE 16. CIRCUIT FOR SINGLE CHANNEL OPERATION TABLE 13. SAMPLE FORMAT FOR CONTROL WORD 3 - 39-37 Address 011 = Control Word 3. 36 Update 1 = Control Register Update. 31-18 Time Slot Length All Zeroes. 17-0 Phase Offset All Zeroes. TABLE 14. SAMPLE FORMAT FOR CONTROL WORD 4 - 39-37 Address 100 = Control Word 4. 36 Update 1 = Control Register Update. 32 Up Convert 0 = Do Not Up convert. 31 Real Mode 0 = Complex Mode.

0 Spectral Reverse 0 = No Spectral Reversal

TABLE 15. SAMPLE FORMAT FOR CONTROL WORD 5 39-37 Address 101 = Control Word 5. 36 Update 1 = Control Register Update. F = Decimation by 16 in HDF. 4-3 Output Format 00 = Two’s Complement. 0 Output Sense 1 = MSB First.

part of the output signal is taken. trivial operations, this up conversion is done in the Formatter. Figure 17B shows the signal spectrum after up conversion. Figure 17C shows the spectrum of the real output signal. the real and imaginary parts of the filter output. TABLE 16. SAMPLE FORMAT FOR CONTROL WORD 6 - 39-37 Address 110 = Control Word 6. 36 Update 1 = Control Register Update. 35 I followed by Q 1 = I and Q Data Output on I Pin. 34-29 Time Slot Time Slot Number = 0.

28 IQCLK Polarity 0 = Data Stable on Rising Edge

27 IQCLK Duty Cycle 1 = IQCLK Duty Cycle is 50%. 26 IQCLK Duration 1 = Active Continuously. 23 IQSTB Polarity 0 = IQSTB Active High.

22 IQSTB Location 0 = IQSTB Active Prior to the

19 I Polarity 0 = I Output Active High. 16 Q Polarity 0 = Q Output Active High. 13 Input Format 1 = Two’s complement. TABLE 17. SUMMARY OF CONTROL WORDS FOR THE EXAMPLE

5 B001F00000

6 D80D12XXXX

1. Now lets consider the multichannel timing. Each channel

the part is outputting data 1.7MHz in every time slot. omitted for the sake of clarity. Architecture, IEEE Std 1149.1 - 1990. FIGURE 23. CIRCUIT FOR MULTIPLE CHANNEL OPERATION

Absolute Maximum Ratings Thermal Information Operating Conditions oC to 70oC Thermal Resistance (Typical, Note 1)θJA (oC/W) θJC (oC/W) Maximum Junction Temperature Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Power Supply Current I CCOP VCC = Max, CLK Frequency 52.6MHz Notes 2, 3 - 394 mA VCC = Max, CLK Frequency 76.9MHz Notes 2, 3 - 577 mA Standby Power Supply Current I CCSB VCC = Max, Outputs Not Loaded - 500 µA Input Leakage Current I I VCC = Max, Input = 0V or VCC TMS, TDI,TRST -500 10 µA VCC = Max, Input = 0V or VCC All other inputs -10 10 µA Output Leakage Current I O VCC = Max, Input = 0V or VCC -10 10 µA Logical One Input Voltage V IH VCC = Max 2.0 - V Logical Zero Input Voltage V IL VCC = Min - 0.8 V Logical One Input Voltage: CLK,TRST V IHC VCC = Max 3.0 - V Logical One Output Voltage V OH IOH = -5mA, VCC = Min 2.6 - V Logical Zero Output Voltage V OL IOL = 5mA, VCC = Min - 0.4 V Input Capacitance C IN CLK Frequency 1MHz All measurements referenced to GND. T A = 25oC, Note 4 -1 0 p F Output Capacitance C OUT -1 0 p F NOTES: 2. Power supply current is proportional to frequency. Typical rating is 7.5mA/MHz. Note that operation at maximum clock frequency will exceed maximum junction temperature of device. Use of a heat sink and/or air flow is required under these conditions: Recommended heat sink is EG&G Wakefield D10650-40. 3. Output load per test circuit and CL = 40pF. 4. Not tested, but characterized at initial design and at major process/design changes. PARAMETER SYMBOL NOTES UNITSMIN MAX MIN MAX CLK Period t CP 19 - 13 - ns CLK High t CH 7-5- n s CLK Low t CL 7-5- n s Setup Time DATA0-15 to CLK t DS 10 - 7 - ns Hold Time DATA0-15 from CLK t DH 1-1- n s RESET Pulse Width t RL tCP +11 - t CP +8 - ns HSP50016

RESET, IQSTR T Setup Time from CLK t RS Note 6 10 - 7 - ns RESET, IQSTR T Hold Time to CLK t RH Note 6 1-1- n s CLK to I, Q, IQSTB, IQCLK Delay t DO -1 5-1 2 n s CCLK Period t CCP 100 - 100 - ns CCLK High t CCH 40 - 40 - ns CCLK Low t CCL 40 - 40 - ns CDATA, CSTB, CS Setup to CCLK t CDS 30 - 30 - ns CDATA, CSTB, CS Hold from CCLK t CDH 30 - 30 - ns CCLK Low Setup to CLK t CLS Notes 6, 7 30 - 30 - ns CCLK High Hold from CLK t CHH Notes 6, 7, 10 30 - 30 - ns TCK Period t TCP Note 8 100 - 100 - ns TCK High t TH 40 - 40 - ns TCK Low t TL 40 - 40 - ns TRST Pulse Width t TRL 100 - 100 - ns TCK to TDO, Data Delay t TDO -3 0-3 0 n s Setup Time On All Inputs to TCK t ATS Note 9 30 - 30 - ns Hold Time On All Inputs from TCK t ATH Note 9 30 - 30 - ns TCK Setup Time to CLK t TCS Note 8 30 - 30 - ns TCK Hold Time from CLK t TCH Note 8 30 - 30 - ns Output Enable Time from CLK t OE Note 10 - 18 - 12 ns Output Disable Time from CLK t OD Note 10 - 18 - 12 ns Output Enable Time from TCK t TOE Note 10 - 32 - 32 ns Output Disable Time from TCK t TOD Note 10 - 32 - 32 ns Output Rise, Fall Time t RF Note 10 -5-5 n s NOTES: 3.0V, VIHC = 4.0V, VIL= 0V; VOH = VOL = 2.5V. 6. These are asynchronous inputs; setup and hold times must only be maintained in order to predict which clock cycle they take effect internally. 7. Timing must only be maintained when Update bit is active in control word data being loaded. 8. Special Timing relationship between TCK and CLK is required for Test Instructions RUNBIST, EXTEST and INTEST. 9. All inputs except TRST, and only when TCK is driving internal clock. 10. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. PARAMETER SYMBOL NOTES UNITSMIN MAX MIN MAX AC Test Load Circuit NOTE: Test head capacitance. EQUIVALENT CIRCUIT C L (NOTE) IOH 2.5V I OL DUT SWITCH S1 OPEN FOR I CCSB AND ICCOP HSP50016

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FIGURE 26. TIMING RELATIVE TO TCK FIGURE 27. OUTPUT RISE AND FALL TIMES