HSP45240_04 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- Block Oriented 24-Bit Sequencer
- Configurable as Two Independent 12-Bit Sequencers
- 24 x 24 Crosspoint Switch
- Programmable Delay on 12 Outputs
- Multi-Chip Synchronization Signals
- S t a n d a r d µP Interface
- 100pF Drive on Outputs
- DC to 50MHz Clock Rate
Applications
- 1-D, 2-D Filtering
- Pan/Zoom Addressing
- FFT Processing
- Matrix Math Operations
Description
The Intersil HSP45240 is a high speed Address Sequencer which provides specialized addressing for functions like FFTs, 1-D and 2-D filtering, matrix operations, and image manipulation. The sequencer supports block oriented addressing of large data sets up to 24-bits at clock speeds up to 50MHz. Specialized addressing requirements are met by using the onboard 24 x 24 crosspoint switch. This feature allows the map- ping of the 24 address bits at the output of the address genera- tor to the 24 address outputs of the chip. As a result, bit reverse addressing, such as that used in FFTs, is made possible. A single chip solution to read/write addressing is also made possible by configuring the HSP45240 as two 12-bit sequencers. To co mpensate for system pipeline delay, a programmable delay is provided on 12 of the address out- puts. The HSP45240 is manufactured using an advanced CMOS process, and is a low power fu lly static design. The configu- ration of the device is controlled through a standard micro- processor interface and all inputs/outputs, with the exception of clock, are TTL compatible. Block Diagram
Ordering Information
TEMP. RANGE (°C) PACKAGE PKG. DWG. # HSP45240JC-33 0 to 70 68 Ld PLCC N68.95 HSP45240JC-50 0 to 70 68 Ld PLCC N68.95 DLYBLK OUT12-23 OUT0-11 STARTIN STARTOUT ADDVAL DONE BLOCKDONE OEH OEL BUSY START CIRCUITRY SEQUENCE GENERATOR SWITCH CROSSPOINT REG DELAY 1-8 PROCESSOR INTERFACE D0-6, CS, A0, WR FN2489.4CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143| Intersil (and design) is a trademark of Intersil Americas Inc. Copyright Harris Corporation 1997, Copyright Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ADDRESS SEQUENCER HSP45240
68 PIN PLASTIC LEADED CHIP CARRIER (PLCC)
VCC I 6, 24, 34, 41 49, 55, 68 +5V power supply pin. GND I 3, 9, 18, 22, 38, 46, 52, 58, 65 GROUND. RST I 25 RESET: This active low input causes a chip reset which lasts for 26 clocks after RST has been deasserted. The reset initializes the Crosspoint Switch and some of the con- figuration registers as described in the Proc essor Interface Section. The chip must be clocked for reset to complete. CLK I 23 CLOCK: The “CLK” signal is a CMOS inpu t which provides the basic timing for address generation. WR I 19 WRITE: The rising edge of this input latches the data/address on D0-6 to be latched into the Processor Interface. CS I 21 CHIP SELECT: This active “low” input enables the configuration data/address on D0-6 to be latched into the Processor Interface. A0 I 20 ADDRESS 0: This input defines D0-6 as a configuration register address if “high”, and configuration data if “low”, (see Processor Interface text). D0-6 I 11-17 DATA BUS: Data bus for Processor Interface. OEH I 28 OUTPUT ENABLE HIGH: This asynchronous input is used to enable the output buffers for OUT 12-23. 9876543216 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 4327 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 NC OUT12 GND OUT11 OUT10 V CC OUT9 OUT8 GND OUT7 OUT6 V CC OUT5 OUT4 GND OUT3 NC NC GND WR CS GND CLK VCC RST NC GND OUT23 OUT22 V CC OUT21 OUT20 GND OUT19 OUT18 V CC OUT17 OUT16 GND OUT15 OUT14 OUT13 NC NC OEH OEL DLYBLK STARTIN STARTOUT ADDVAL VCC BUSY BLOCKDONE DONE GND OUT0 OUT1 VCC OUT2 NC HSP45240
OEL I 29 OUTPUT ENABLE LOW: This asynchronous input is used to enable the output buffers for OUT0-11. STARTIN I 31 START-IN: This active low input in itiates an addressing sequence. May be tied to STARTOUT of another H5P45240 for multichip synchronization. STARTIN should only be asserted for one CLK because address sequencing begins after STARTIN is deas- serted. DLYBLK I 30 DELAY BLOCK: This active “high” i nput may be used to halt address generation on ad- dress block boundaries (see Sequence Generator text). The required timing relation- ship of this signal to the end of an address block is shown in Application Note 9205. OUT0-23 O 39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56, 57, 59, 62-64, 66, 67, 1, 2, 4, 5, 7, 8 OUTPUT BUS: TTL compatible 24-bit Address Sequencer output. BLOCK DONE O 36 BLOCK DONE: This active low output signals when the last address in an address block is on OUT0-23. DONE O 37 DONE: This active low output signals when the last address of an address sequence is on OUT0-23. ADDVAL O 33 ADDRESS VALID: This active low output si gnals when the first address of an address sequence is on 0UT0-23. START-OUT O 32 START-OUT: This active low out put is generated when an address sequence is initiat- ed by a mechanism other than STARTIN . May be tied to the STARTIN of other H5P45240’s for multichip synchronization. BUSY O 35 BUSY: This active low output is asserted one CLK after RST is deasserted and will re- main asserted for 25 CLK’s. While BUSY is asserted, all writes to the Processor Inter- face are disabled. NOTE: #Denotes active low. Pin Descriptions NAME TYPE PLCC PIN NUMBER DESCRIPTION HSP45240
The Address Sequencer is a 24-bit programmable address generator. As shown in the Block Diagram, the sequencer consists of 4 functional blo cks: the start circuitry, the sequence generator, the crosspoi nt switch, and the proces- sor interface. The addresses produced by the sequence generator are input into the crosspoint switch. The cross- point switch maps 24 bits of address input to a 24-bit output. This allows for addressing schemes like “bit-reverse” addressing for FFT’s. A programmable delay block is pro- vided to allow the MSW of the output to be skewed from the LSW. This feature may be used to compensate for proces- sor pipeline delay when the sequence generator is config- ured as two independent 12-bit sequencers. Address Sequencer operation is controlled by values loaded into con- figuration registers associated with the sequence generator, crosspoint switch, and start circuitry. The configuration regis- ters are loaded through the processor interface. Start Circuitry The Start Circuitry generates the internal START signal which causes the Sequence Generator to initiate an addressing sequence. The START signal is produced by writing the Processor Interfac e’s “Sequencer Start” address (see Processor Interface text), by asserting the STARTlN input, or by the terminal address of a sequence generated under “One-Shot Mode with Restart” (see Sequence Gener- ator Section). Care should be taken to assert STARTlN for only one clock cycle to ensure proper operation. A program- mable delay from 1 to 31 clocks is provided to delay the initi- ation of an addressing sequence by delaying the internal START signal (see Processor Interface text). The Start Circuitry generates the output signal ADDVAL which is asserted when the first valid output address is at the pads. In addition, the Start Circuitry generates the “STARTOUT ” signal for multichip synchronization. Note: STARTOUT is only generated when an addressing sequence is started by writing the “Sequencer Start” address of the Processor Interface, or an internal START is gener- ated by reaching the end of an addressing sequence pro- duced by “One-Shot Mode with Restart”. Sequence Generator The Sequence Generator is a block oriented address gener- ator. This means that the des ired address sequence is sub- divided into one or more a ddress blocks, each containing a user defined number of addresses. User supplied configura- tion data determines the number of address blocks and the characteristics of the address sequence to be generated. As shown in Figure 1, the Sequence Generator is subdivided into the address generation and control sections. The address generation section performs an accumulation based on the output of MUX1 and MUX2. The control section gov- erns the operation of the multiplexers, enables loading of the Block Start Address register, and signals completion of an address sequence. An address sequence is started when the control section of the Sequence Generator receives the internal START signal from the Start Circuitry. When the START signal is received, the control section multiplexe s the contents of the Start Address Register and a “0” to the adder. The result of this summation is the first address in the first block of the address sequence. This value is stored in the Block Start Address register by an enabl e generated from the control section, and the multiplexers are switched to feed the output of the Holding and Address Increment registers to the adder. Address generation will continue with the Address Increment added to the contents of the Holding Register until the first address block has been completed. An address block is completed when the number of addresses generated since th e beginning of the address block equals the value stored in the Block Size register. When the last address of the block is generated, BLOCK- DONE is asserted to signal the end of the address block (see Application Note 9205). On the following CLK, the mul- tiplexers are configured to pa ss the contents of the Block Start Address and Block Increment registers to the adder which generates the first address of the next address block. An enable from the control section allows this value to update the Block Start Address register, and the multiplexers are switched to feed the Holding and Address Increment registers to the adder for generation of the remaining addresses in the block. The address sequence is completed when the number of address blocks generated equals the value loaded into the Number of Blocks register. When the final address in the last address block has been generated, DONE and BLOCK- DONE are asserted to signal the completion of the address sequence. The parameters governing address generation are loaded into five 24-bit configuration registers via the Processor Interface. These parameters include the Start Address, the beginning address of the sequence; the Block Size, the number of addresses in the address block; the Address Increment, the increment between addresses in a block; the Number of Blocks, the num ber of address blocks in a sequence (minimum 1); the Block Increment, the increment between starting addresses of each block. The loading and structure of these registers is detailed in the Processor Inter- face text. HSP45240
- One-Shot Mode without Restart Address generation halts
after completion of the user specified address sequence.
- One-Shot Mode with Restart: This mode is identical to
- Continuous Mode: Address generation never terminates.
dual sequencer mode to generate read/write addressing. the address block required to halt address sequencing. a particular output bit, that output will be “low”. isters are contained in the Processor Interface text.
12 MSB
12 LSB
FIGURE 1. SEQUENCE GENERATOR BLOCK
interface and a register bank which holds configuration data. either data or address as shown by the bit map in Table 1. using previous configuration data. relative mapping of the 6-bit re gister to the 24-bit register. mapped to the MSB of the sequence generator output. output delay between the MS W and the LSW of OUTO-23.
- Table 1 “x” means “don’t care”, and “n” denotes bits which are de-
coded as an address in address registers and data in data registers. (1x111111), it must remain high until after a rising edge of clock. Otherwise, the sequencer “start” signal will not be generated. TABLE 2. MODE CONTROL REGISTER FORMAT
the following number of clocks. bit sequences to be generated. start circuitry for delayed starts from 1 to 31 clock cycles. Start Delay Control Register is shown in Table 3. minimum of “1” is required for the programmed delay. bring the chip up in a mode with Start Delay disabled. Test Control Register is shown in Table 4. Bits “D5” and “D6” are currently not used. by shifting Start Address Register one bit per clock. 0 A 24-bit sequence is generated. 1 Two 12-bit sequences are generated. 0 0 One-Shot Mode without Restart. 0 1 One-Shot Mode with Restart. 1 x Continuous Mode (x = don’t care). TABLE 3. START DELAY CONTROL REGISTER FORMAT TABLE 4. TEST CONTROL REGISTER FORMAT FIGURE 2. SEQUENCE GENERATOR CONTROL
tation is referred to as an “in place” FFT algorithm. grams comprised of many butterflies as shown in Figure 7. Table 5. The specialized addressing required here is pro- from the sequence generator to the chip output.
- Start Address = 0 4. Step Size = 1
- Block Size = 8 5. Block Step Size = 0
corresponds to the Block Size, in this case 8. switch output register 1, and a 0 to switch output register 2. are generated by reconfiguring the above three registers. provide read/write addressing for FFT’s up to 4096 points. delay associated with the arithmetic processor. TABLE 5. FFT ADDRESSING BY COMPUTATIONAL STAGE
Absolute Maximum Ratings TA = 25°C Thermal Information Operating Conditions Thermal Resistance (Typical, Note 3) θJA (°C/W) θJC (°C/W) Maximum Package Power Dissipation at 70°C Maximum Junction Temperature Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θJA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Logical One Input Voltage V IH VCC = 5.25V 2.0 - V Logical Zero Input Voltage V IL VCC = 4.75V - 0.8 V High Level Clock Input V IHC VCC = 5.25V 3.0 - V Low Level Clock Input V ILC VCC = 4.75V - 0.8 V Output HIGH Voltage V OH IOH = 400µA, VCC = 4.75V 2.6 - V Output LOW Voltage V OL IOL = +2.0mA, VCC = 4.75V - 0.4 V Input Leakage Current I I VIN = VCC or GND, VCC = 5.25V -10 10 µA I/O Leakage Current I O VOUT = VCC or GND, VCC = 5.25V -10 10 µA Standby Power Supply Current I CCSB VIN = VCC or GND, VCC = 5.25V, Outputs Open - 500 µA Operating Power Supply Current I CCOP f = 33MHz, VIN = VCC or GND, VCC = 5.25V, Outputs Open, (Note 4) -9 9 m A Input Capacitance C IN f = 1MHz, VCC = Open, All Measurements are referenced to device GND. (Note 5). -1 0 p F Output Capacitance C O -1 0 p F NOTES: 4. Power supply current is proportional to operating frequency. Typical rating for I CCOP is 3mA/MHz. 5. Not tested, but characterized at initial design and at major process/design changes. HSP45240
-33 (33MHz) -40 (40MHz) -50 (50MHz) UNITSMIN MIN MIN MAX MIN MAX Clock Period t CP 30 - 25 - 20 - ns Clock Pulse Width High t CH 12 - 10 - 9 - ns Clock Pulse Width Low t CL 12 - 10 - 9 - ns Setup Time D0-6 to WR High t DS 14 - 13 - 12 - ns Hold Time D0-6 from WR High t DH 0-0-0-n s Setup Time A0, CS, to WR Low t AS 5-5-5-n s Hold Time A0, CS, from WR High t AH 0-0-0-n s Pulse Width for WR Low t WRL 13 - 12 - 10 - ns Pulse Width for WR High t WRH 13 - 12 - 10 - ns WR Cycle Time t WP 30 - 25 - 20 - ns Setup Time STARTIN, DLYBLK to Clock High t IS 12 - 10 - 8 - ns Hold Time STARTIN, DLYBLK to Clock High t IH 0-0-0-n s Clock to Output Prop., Delay on OUT0-23 t PDO -1 5-1 3-1 2n s Clock to Output Prop. Delay on STARTOUT, BLKDONE, DONE, ADDVAL and BUSY tPDS -1 5-1 3-1 2n s Output Enable Time t EN -2 0-1 5-1 3n s Output Disable Time t OD Note 6 - 20 - 15 - 13 ns Output Rise/Fall Time t ORF N o t e 6 -5-3-3n s RST Low Time t RST 2 Clock Cycles ns NOTES: 6. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or de- sign changes. 7. AC Testing is performed as follows: Input levels (CLK input) = 4.0V and 0V; input levels (all other inputs) = 0V and 3.0V; input timing DUT EQUIVALENT CIRCUIT 1.5V I OLIOH (NOTE 8) CL NOTES: 8. Includes stray and jig capacitance. 9. Switch S 1 Open for ICCSB and ICCOP Tests. OUTPUT PIN C L BLOCKDONE DONE ADDVAL STARTOUT BUSY 40pF OUTTO-23 100pF HSP45240