HSP45116VC-25

HSP45116 RENESAS | Alldatasheet

Document overview

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• PDF pages: 16

Technical content

Features

• NCO and CMAC on One Chip
• 15MHz, 25.6MHz, 33MHz Versions
• 32-Bit Frequency Control
• 16-Bit Phase Modulation
• 16-Bit CMAC
• 0.008Hz Tuning Resolution at 33MHz
• Spurious Frequency Components < -90dBc
• Fully Static CMOS

Applications

• Frequency Synthesis
• Modulation - AM, FM, PSK, FSK, QAM
• Demodulation, PLL
• Phase Shifter
• Polar to Cartesian Conversions Block Diagram

Ordering Information

TEMP. RANGE (°C) PACKAGE PKG. DWG. # HSP45116VC-25 0 to 70 160 Ld MQFP Q160.28x28 PHASE/ FREQUENCY CONTROL SECTION SINE/ COSINE SECTION CMAC SINE/ COSINE ARGUMENT SIN COS VECTOR INPUT VECTOR OUTPUT RI RI MICROPROCESSOR INTERFACE INDIVIDUAL CONTROL SIGNALS NOT RECOMMENDED FOR NEW DESIGNS POSSIBLE SUBSTITUTE PRODUCTHSP45116A

FN2485 Rev 8.00 Page 2 of 16 Jul 2004 Pinout

160 LEAD MQFP

V CC RO13 RO12 RO11 GND RO14 GND IO6 IO5 IO4 IO3 IO2 IO1 V CC IO0 RO19 GND GND RO2 RO1 RO0 DET1 DET0 GND V CC RO4 RO3 NC CLROFR ENCFREG ENPHAC ENTIREG ENI MODPI/2PI CS GND CLK VCC AD1 AD0 WR C15 C14 C13 C12 C11 C10 GND NC OUTMUX1 OUTMUX0 GND OER VCC OEREXT OEIEXT OEI PACO MOD1 VCC TICO GND RBYTILD MOD0 PACI LOAD PMSEL NC PEAK RIN0 VCC SH1 SH0 ACC ENPHREG ENOFREG BINFMT RIN6 RIN7 RIN8 RIN9 RIN11 RIN5 RIN4 RIN3 RIN2 GND RIN12 RIN17 RIN18 IMIN0 RIN16 RIN15 RIN14 GND RIN13 RIN10 IO7 IO8 IO9 V CC GND IO10 IO11 IO12 IO13 IO14 GND V CC IO15 IO16 IO17 IO18 IO19 IMIN18 IMIN17 IMIN16 IMIN15 IMIN14 GND IMIN13 V CC IMIN12 IMIN11 IMIN10 IMIN9 NC IMIN8 IMIN7 IMIN6 IMIN5 IMIN4 IMIN3 IMIN2 GND IMIN1 V CC RIN1

FN2485 Rev 8.00 Page 3 of 16 Jul 2004 Pin Description NAME NUMBER TYPE DESCRIPTION VCC A1, A9, A15, G1, J15, Q1, Q7, Q15 - +5V Power supply input. GND A8, A14, B1, H1, H15, P15, Q2, Q8 - Power supply ground input. Q9-14 I Control input bus for loading phase and frequency data into th e PFCS. C15 is the MSB. AD0-1 N7, P7 I Address pins for selecting destination of C0-15 dat a. CS P6 I Chip Select (active low). WR Q6 I Write Enable. Data is clocked into the register selected by AD0-1 on the rising edge of WR when the CS line is low. CLK Q5 I Clock. All registers, exc ept the control registers clocke d with WR, are clocked (when enabled) by the rising edge of CLK. ENPHREG M1 I Phase Register Enable (active low). Registered on chip by CL K. When active, after being clocked onto chip, ENPHREG enables the clocking of data into the phase register. ENOFREG N1 I Frequency Offset Register E nable (active Low). Registered on chip by CLK. When active, after being clocked onto chip, ENOFREG enables clocking of data into the frequency offset register. ENCFREG N5 I Center Frequency Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto chip, ENCFREG enables clocking of data into the center frequency register. ENPHAC Q3 I Phase Accumulator Register Enable (active low). Registered o n chip by CLK. When active, after being clocked onto chip, ENPHAC enables clocking of the phase accumulator register. ENTIREG P5 I Time Interval Control Register Enable (active low). Register ed on chip by CLK. When active, after being clocked onto chip, ENTIREG enables clocking of data into the time accumulator register. ENI Q4 I Real and Imaginary Data Input Register (RIR, IIR) Enable (ac tive low). Registered on chip by CLK. When active, after being clocked onto chip, ENI enables clocking of data into the real and imaginary input data register. MODPI/2PI N6 I Modulo /2 Select. When low, the Sine and Cosine ROMs are addressed modul o 2 (360 degrees). When high, the most significant address bit is held l ow so that the ROMs are addressed modulo  (180 degrees). This input is registered on chip by clock. CLROFR P4 I Frequency Offset Register Output Zero (active low). Register ed on chip by CLK. When active, after being clocked onto chip, CLROFR zeros the data path from the frequency offset register to the frequency adder. New data can still be clocked into the fre quency offset register; CLROFR does not affect the contents of the register. LOAD N4 I Phase Accumulator Load Control (active low). Registered on c hip by CLK. Zeroes feedback path in the phase accumulator without clearing the phase accumulator register. MOD0-1 M3, N3 I External Modulation Control Bits. When selected wi th the PMSEL line, these bits add a 0, 90, 180, or 270 degree offset to the current phase in the phase acc umulator. The lower 14 bits of the phase control path are set to zero. These bits are loaded into the phase register when ENPHREG is low. PMSEL P3 I Phase Modulation Select L ine. This line determines the source of the data clocked into the phase register. When high, the phase control register is selected. When low, the external modulation pins (MOD0-1) are selected for the most significant two bits and the least significant two bits and the least significant 14 bits are set to zero. This control is registered by CLK. RBYTILD L3 I ROM Bypass, Timer Load. Active low, registered by CLK. This input bypasses the sine/ cosine ROM so that the 16-bit phase adder output and lower 16 bits of the phase accumulator go directly to the CMAC’s sine and cosine inputs, respectively. It also enables loading of the timer accumulator register by zeroing the feedback in the accumulator. PACI P2 I Phase Accumulator Carry Input (active low). A low on this pi n causes the phase accumulator to increment by one, in addition to the values in the phase accumu lator register and frequency adder.

FN2485 Rev 8.00 Page 4 of 16 Jul 2004 PACO L13 O Phase Accumulator Carry Output. Active low and registered b y CLK. A low on this output indicates that the phase accumulator has overflowed, i.e., the end of one sine/cosine cycle has been reached. TICO P1 O Time Interval Accumulator Carry Output. Active low, register ed by CLK. This output goes low when a carry is generated by the time interval accumulator. This function is provided to time out control events such as synchronizing register clocking to data timing. RIN0-18 C1, C2, D1, D2, E1- 3, F1-3, G2, G3, H2, H3, J1-3, K1, I Real Input Data Bus. This is the external real component into the complex multiplier. The bus is clocked into the real input data register by CLK when ENI is asserted; two’s complement. IMIN0-18 A2-7, B2-7, C3-8, I Imaginary Input Data Bus. This is the external imaginary compo nent into the complex multiplier. The bus is clocked into the real input data register by CLK whe n ENI is asserted; two’s complement. SH0-1 K3, L1 I Shift Control Inputs. These lines control the input shifters of the RIN and IIN inputs of the complex multiplier. The shift controls are common to the shifters on both of the busses. ACC L2 I Accumulate/Dump Control. This input controls the complex accumulators and their holding registers. When high, the accumulators accumulate and the holdi ng registers are disabled. When low, the feedback in the accumulators is zeroed to cause the accumulators to load. The holding registers are enabled to clock in the results of th e accumulation. This input is registered by CLK. BINFMT N2 I This input is used to convert the two’s complement output to offset binary (unsigned) for applications using D/A converters. When low, bits RO19 and IO19 are inverted from the internal two’s complement representation. This input is registered by CLK. PEAK M2 I This input enables the peak det ect feature of the block floa ting point detector. When high, the maximum bit growth in the output holding registers is encoded and output on the DET0-1 pins. When the PEAK input is asserted, the block floating point detector output will track the maximum growth in the holding registers, including the data in the holding registers at the time that PEAK is activated. OUTMUX0-1 N12, N13 I These inputs select the data to be output on RO0-19 and IO0-19. RO0-19 C15, D14, D15, E14, E15, F13-15, G13-15, H13, H14, J13, J14, K13-15, L15, M15 O Real Output Data Bus. These Three-state outputs are controlled b y O E R and OEREXT . OUTMUX0-1 select the data output on the bus. IO0-19 A10-13, B8-15, C9- 14, D13, E13 O Imaginary Output Data Bus. These Three-state outputs are contr olled by OEI and OEIEXT . OUTMUX0-1 select the data output on the bus. DET0-1 N15, L14 O These output pins indicate the number of bits of growth in the accumulators. While PEAK is low, these pins indicate the peak growth. The detector examines bits 15-18, real and imaginary accumulator holding registers and bits 30-33 of the real and imaginary CMAC holding registers. The bits indicate the largest growth of the four registers. OER P14 I Three-state control for bits RO0-15. Outputs are enabled wh en the line is low. OEREXT M13 I Three-state control for bits RO16-19. Outputs are enabled w hen the line is low. OEI M14 I Three-state control for bits IO0-15. Outputs are enabled wh en the line is low. OEIEXT N14 I Three-state control for bits IO16-19. Outputs are enabled w hen the line is low. Pin Description (Continued) NAME NUMBER TYPE DESCRIPTION

FN2485 Rev 8.00 Page 5 of 16 Jul 2004 HSP45116 Functional Block Diagram COS SIN R.RBYTILD R.PMSEL R.ENPHREG R E G >CLK PACI PHASE INPUT REGISTER MS INPUT REGISTER PHEN 0 16 R.ENPHREG LS INPUT REGISTER LSEN OFFSET REGISTER CENTER FREQUENCY REGISTER R.PMSEL FREQUENCY ADDER A D D E R PHASE REGISTER R.CLROFR 32MSEN CLK R.ENCFREG R.LOAD R.ENOFREG MOD(1:0) ENCODE C(15:0) PHASE ACCUMULATOR ADDER PHASE ADDER SIN/COS ARGUMENT A D D E R

16 MSBs

16 LSBs

R.MODPI/2PI MSB R.ENPHAC A D D E R PHASE ACCUMULATOR REGISTER PHASE ACCUMULATOR DECODER R.ENCFREG R.ENOFREG R.CLROFR R.LOAD R.ENPHAC R.MODPI/2PI PMSEL ENCFREG CLROFR LOAD ENPHREG ENPHAC MODPI/2PI ENOFREG CLK TIME INCREMENT32 R.ENTIREG 32 32 32 CARRY OUTTIME ACCUMULATOR REGISTER R.RBYTILD TICO ADDER AD(1:0) CS WR ENTIREG RBYTILD R.ENTIREG ACC R.ENIENI R.BINFMTBINFMT R.SH(1:0)SH(1:0) PEAK R.PEAK SINE/COSINE GENERATOR TIME ACCUMULATOR OUTMUX(1:0) OEREXT OER OEIEXT OEI TICO PACO RIN(18:0) IMIN(18:0) CLK PHASE R.ACC R.ENI R.BINFMT R.SH(1:0) R.PEAK R.ACC FREQUENCY R E R E R E R E R E CLK R E CLK R E CLK R E G>CLK CLK R E R E G>CLK CLK R E R E G>CLK R E G>CLK PACI R E G 0 1 MUX 1 0 MUX 0 1 MUX 0 1 MUX 1 0 MUX RIN(18:0) IMIN(18:0)

FN2485 Rev 8.00 Page 6 of 16 Jul 2004 HSP45116 Functional Block Diagram (Continued) ADDER R1.ACC 0 0 16 16 SHIFTERSHIFTER R.SH(1:0) R.ENI 1919 SIN COS COMPLEX MULTIPLIER 33 33 ADDER ADDER ADDER COMPLEX ACCUMULATOR CMAC ACCUMULATOR R.PEAK GROWTH DETECT DET(1:0) 163FMT 164OUTMUX(1:0) RO(19-16) RO(15:0) R.BINFMT OEREXT OER 16FMT 164 OUTMUX(1:0) IO(19-16) IO(15:0) R.BINFMT OEIEXT OEI 35 35 20 R1.ACC R2.ACC ROUND ROUND RIN0-18 IMIN0-18 R.RBYTILD R.ENI R.SH(1:0) SIN COS R.ACC R.PEAK R.SH(1:0) R.ENI OUTMUX(1:0) See Table 4 CLK R E CLK R E REG>CLK REG>CLKREG>CLK REG> CLK R E G>CLK R E G>CLK REG>CLK REG> CLK REG>CLK CLKREG < REG>CLKCLKREG < REG>CLK REG>CLK REG < CLK REG>CLK REG < CLK 0 1 MUX 1 0 MUX MUX 0 1 MUX 0 1 MUX MUX OUTMUX(1:0) See Table 4 1 0 MUX CLKREG < CLKREG < 1 0 MUX PHASE RIN(18:0) IMIN(18:0)

output for Direct Digital Synthesis (DDS) applications. them by the input vector to form the modulated output. at 0o and advancing around the unit circle counterclockwise. preprogrammed period of time. the 32 bits of the adder going into the accumulator register. Phase Accumulator Carry Out, PACO. Adder, which adds an offset to the top 16 bits of the phase. which is passed to the Sine/Cosine Generator. Register, Offset Frequency Register and Time Accumulator. MSB) and the least significant 14 bits are loaded with 0. TABLE 1. AD0-1 DECODING

internally generated sine and cosine. of the phase increment summer on the next clock. explained in greater detail in the Applications Section. added to the top 16 bits of the Phase Accumulator. to enable the periodic sampling of the output of the NCOM. generator is scaled by one so that it is symmetric about 0. computed value of the complex vector is less than -90.2dB. and the least significant bits come out on ROUT0-15. TABLE 2. MOD0-1 DECODE FIGURE 1. SINE/COSINE SECTION

used along with the complex multiplier/accumulator for FFTs. shifters is sent to the CMAC and the auxiliary accumulators. unsigned output, while BINFMT = 1 selects two’s complement. whether the accumulator output appears on ROUT and IOUT. TABLE 3. INPUT SHIFT SELECTION TABLE 4. OUTPUT MULTIPLEXER SELECTION

0 RO16-19 RO0-15 IO16-19 IO0-15

FIGURE 2. COMPLEX MULTIPLIER/ACCUMULATOR; ALL REGISTERS CLOCKED BY CLK

is latched in the Growth Detect Output Register. cascading NCOMs for FFT applications. FIGURE 3. BIT WEIGHTING TABLE 5. GROWTH ENCODING

FN2485 Rev 8.00 Page 13 of 16 Jul 2004 Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 1) JA (°C/W) Maximum Junction Temperature (MQFP - Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Logical One Input Voltage V IH VCC = 5.25V 2.0 - V Logical Zero Input Voltage V IL VCC = 4.75V - 0.8 V High Level Clock Input V IHC VCC = 5.25V 3.0 - V Low Level Clock Input V ILC VCC = 4.75V - 0.8 V Output HIGH Voltage V OH IOH = -400mA, VCC = 4.75V 2.6 - V Output LOW Voltage V OL IOL = 2.0mA, VCC = 4.75V - 0.4 V Input Leakage Current I I VIN = VCC or GND, VCC = 5.25V -10 10 A I/O Leakage Current I O VOUT = VCC or GND, VCC = 5.25V -10 10 A Standby Power Supply Current I CCSB VIN = VCC or GND VCC = 5.25V, Note 4 - 500 A Operating Power Supply Current I CCOP f = 15MHz, VIN = VCC or GND, VCC = 5.25V, Notes 2 and 4 - 182 mA Capacitance TA = 25°C, Note 3 PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Input Capacitance C IN FREQ = 1MHz, VCC = Open, All measurements are referenced to device ground -1 5 p F Output Capacitance C O -1 5 p F NOTES: 2. Power supply current is proportional to operating frequency. Typical rating for ICCOP is 10mA/MHz. 3. Not tested, but characterized at initial design and at major process/design changes. 4. Output load per test load circuit with switch open and CL = 40pF.

FN2485 Rev 8.00 Page 14 of 16 Jul 2004 PARAMETER SYMBOL NOTES UNITSMIN MAX MIN MAX MIN MAX CLK Period t CP 66 - 39 - 30 - ns CLK High t CH 26 - 15 - 12 - ns CLK Low t CL 26 - 15 - 12 - ns WR Low t WL 26 - 15 - 12 - ns WR High t WH 26 - 15 - 12 - ns Setup Time; AD0-1, CS to WR Going High t AWS 18 - 13 - 13 - ns Hold Time; AD0, AD1, CS from WR Going High t AWH 0-0-0- n s Setup Time C0-15 from WR Going High t CWS 20 - 15 - 15 - ns Hold Time C0-15 from WR Going High t CWH 0-0-0- n s Setup time WR High to CLK High t WC 7 2 0-1 6-1 2- n s Setup Time MOD0-1 to CLK Going High t MCS 20 - 15 - 15 - ns Hold Time MOD0-1 from CLK Going High t MCH 0-0-0- n s Setup Time PACI to CLK Going High t PCS 25 - 15 - 11 - ns Hold Time PACI from CLK Going High t PCH 0-0-0- n s Setup ENPHREG, ENCFREG, ENOFREG, ENPHAC, ENTIREG, CLROFR, PMSEL, LOAD, ENI, ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD from CLK Going High tECS 18 - 12 - 12 - ns Hold Time ENPHREG, ENCFREG, ENOFREG, ENPHAC, ENTIREG, CLROFR, PMSEL, LOAD, ENI, ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD from CLK Going High tECH 0-0-0- n s Setup Time RIN0-18, IMIN0-18 to CLK Going High tDS 18 - 12 - 12 - ns Hold Time RIN0-18, IMIN0-18 from CLK Going High tDH 0-0-0- n s CLK to Output Delay RO0-19, IO0-19 t DO -4 0-2 4-1 9n s CLK to Output Delay DET0-1 t DEO -4 0-2 7-2 0n s CLK to Output Delay PACO tPO -3 0-2 0-1 2n s CLK to Output Delay TICO tTO -3 0-2 0-1 2n s Output Enable Time OER, OEI, OEREXT, OEIEXT tOE -2 5-2 0-2 0n s OUTMUX0-1 to Output Delay t MD -4 0-2 8-2 6n s Output Disable Time t OD 6 - 20 - 15 - 15 ns Output Rise, Fall Time t RF 6 -8-8-6n s NOTES: 5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; input levels (all other inputs) 0V and 3.0V; timing reference levels (CLK) 1.5V. 6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 7. Applicable only when outputs are being monitored and ENCFREG, ENPHREG, or ENTIREG is active.

FIGURE 7. INPUT AND OUTPUT TIMING NOTE: Test head capacitance.