HSP45116AVC-52Z

HSP45116A_07 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 19

Technical content

Features

• NCO and CMAC on One Chip
• 52MHz Version
• 32-Bit Frequency Control
• 16-Bit Phase Modulation
• 16-Bit CMAC
• 0.013Hz Tuning Resolution at 52MHz
• Programmable Rounding Option
• Spurious Frequency Components < -90dBc
• Fully Static CMOS
• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Frequency Synthesis
• Modulation - AM, FM, PSK, FSK, QAM
• Demodulation, PLL
• Phase Shifter
• Polar to Cartesian Conversions

Ordering Information

PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # HSP45116AVC-52 HSP45116AVC-52 0 to +70 160 Ld MQFP (28mmx28mm) Q160.28x28 HSP45116AVC-52Z (Note) HSP45116AVC-52Z 0 to +70 160 Ld MQFP (28mmx28mm) (Pb-free) Q160.28x28 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Data Sheet May 7, 2007 FN4156.4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 FN4156.4 May 7, 2007 Block Diagram PHASE/ FREQUENCY CONTROL SECTION SINE/ COSINE SECTION CMAC SINE/ COSINE ARGUMENT SIN COS VECTOR INPUT VECTOR OUTPUT RI RI MICROPROCESSOR INTERFACE INDIVIDUAL CONTROL SIGNALS HSP45116A

(160 LD MQFP) TOP VIEW 119 120 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 126 127 128 129 130 131 121 122 123 124 125 137 138 139 140 132 133 134 135 136 146 147 148 149 150 151 141 142 143 144 145 157 158 159 160 152 153 154 155 156 RO9 VCC RO8 RO7 RO6 RO5 GND RO10 RO18 RO17 RO16 RO15 VCC RO13 RO12 RO11 GND RO14 GND IO6 IO5 IO4 IO3 IO2 IO1 V CC IO0 RO19 GND GND RO2 RO1 RO0 DET1 DET0 GND VCC RO4 RO3 NC CLROFR ENCFREG ENPHAC ENTIREG ENI MODPI/2PI CS GND CLK VCC AD1 AD0 WR C15 C14 C13 C12 C11 C10 GND NC OUTMUX1 OUTMUX0 GND OER RND OEREXT OEIEXT OEI PACO MOD1 VCC TICO GND RBYTILD MOD0 PACI LOAD PMSEL NC PEAK RIN0 VCC SH1 SH0 ACC ENPHREG ENOFREG BINFMT RIN6 RIN7 RIN8 RIN9 RIN11 RIN5 RIN4 RIN3 RIN2 GND RIN12 RIN17 RIN18 IMIN0 RIN16 RIN15 RIN14 GND RIN13 RIN10 IO7 IO8 IO9 VCC GND IO10 IO11 IO12 IO13 IO14 GND V CC IO15 IO16 IO17 IO18 IO19 IMIN18 IMIN17 IMIN16 IMIN15 IMIN14 GND IMIN13 V CC IMIN12 IMIN11 IMIN10 IMIN9 NC IMIN8 IMIN7 IMIN6 IMIN5 IMIN4 IMIN3 IMIN2 GND IMIN1 V CC RIN1 3 FN4156.4 May 7, 2007 HSP45116A

4 FN4156.4 May 7, 2007 Pin Descriptions NAME NUMBER TYPE DESCRIPTION VCC 22, 34, 50, 87, 95, 102, 111, 124, 132, 145, 159 - +5V Power supply input. GND 7, 20, 32, 48, 62, 73, 83, 92, 98, 108, 114, 119, 125, 131, 143, 157 - Power supply ground input. C0-15 54-61, 63-70 I Control input bus for loading phase and frequency data into the PFCS. C15 is the MSB. AD0-1 51, 52 I Address pins for selecting destination of C0-15 data. AD1 is the MSB. CS 47 I Chip select (active low). WR 53 I Write Enable. Data is clocked into the input register selected by AD0-1 on the rising edge of WR when the CS line is low. CLK 49 I Clock. All registers, except t he Control Registers clocked with WR, are clocked (when enabled) by the rising edge of CLK. ENPHREG 27 I Phase Register Enable (active low). Registered on chip by CLK. When active low, after being clocked onto chip, ENPHREG enables the clocking of data into the Phase Register. ENOFREG 28 I Frequency Offset Register Enable (active low). R egistered on chip by CLK. When active, after being clocked onto chip, ENOFREG enables clocking of frequency offset data into the frequency offset register. ENCFREG 42 I Center Frequency Register Enable (active low). R egistered on chip by CLK. When active, after being clocked onto chip, ENCFREG enables clocking of data into the Center Frequency Register. ENPHAC 43 I Phase Accumulator Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto chip, ENPHAC enables clocking of the Phase Accumulator Register. ENTIREG 44 I Time Interval Control Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto chip, ENTIREG enables clocking of data into the Time Accumulator Register. ENI 45 I Real and Imaginary Data Input Register (RIR, IIR) Enable (active low). Registered on chip by CLK. When active, after being clocked onto chip, ENI enables clocking of data into the real and imaginary input data register. MODPI/2PI 46 I Modulo π/2π Select. When low, the Sine and Cosine ROMs are addressed modulo 2 π (360 degrees). When high, the most significant address bit is held low so that the ROMs are addressed modulo π (180 degrees). This input is registered on ch ip by clock. This control pin was included for FFT processing. CLROFR 41 I Frequency Offset Register Output Zero (active lo w). Registered on chip by CLK. When active, after being clocked onto chip, CLROFR zeros the data path from the Frequency Offset Register to the frequency adder. New data can still be clocked into the Frequency Offset Register; CLROFR does not affect the contents of the register. LOAD 38 I Phase Accumulator Load Control (active low). Registered on chip by CLK. Zeroes feedback path in the phase accumulator without clearing the Phase Accumulator Register. MOD0-1 35, 36 I External Modulation Control Bits. When selected with the PMSEL line, these bits add a 0, 90, 180, or 270 degree offset to the current phase in the phase accumulator. The lower 14 bits of the phase control path are set to zero. These bits are loaded into the Phase Register when ENPHREG is low. MOD1 MOD0 PHASE SHIFT (DEGREES) 00 0 01 9 0 1 0 270 1 1 180 HSP45116A

5 FN4156.4 May 7, 2007 PMSEL 39 I Phase Modulation Select Line. This line determines the source of the data clocked into the Phase Register. When high, the Phase Control Register is selected. When low, the external modulation pins (MOD0-1) are selected for the most significant two bits and the least significant two bits and the least significant 14 bits are set to zero. This control is registered by CLK. RBYTILD 30 I ROM Bypass, Timer Load (active low). Registered by CLK. This input bypasses the sine/ cosine ROM so that the 16 bit phase adder output and lower 16 bits of the phase accumulator go directly to the CMAC’s sine and cosine inputs, respecti vely. It also enables loading of the Timer Accumulator Register by zeroing the feedback in the accumulator. PACI 37 I Phase Accumulator Carry Input (active low). A low on this pin causes the phase accumulator to increment by one in addition to the values in the Phase Accumulator Register and frequency adder. PACO 79 O Phase Accumulator Carry Output. Active low and registered by CLK. A low on this output indicates that the phase accumulator has overfl owed, i.e., the end of one sine/cosine cycle has been reached. TICO 33 O Time Interval Accumulator Carry Output. Active low, registered by CLK. This output goes low when a carry is generated by the time interval accu mulator. This function is provided to time out control events such as synchronizing register clocking to data timing. RIN0-18 2-6, 8-19, 21, 23 I Real Input Data Bus. RIN18 is the MSB. This is the external real component into the complex multiplier. The bus is clocked into the real Input Data Register by CLK when ENI is asserted. Two’s complement. IMIN0-18 1, 138-142, 144, 146-156, 158 I Imaginary Input Data Bus. IMIN18 is the MSB. This is the external imaginary component into the complex multiplier. The bus is clocked into the real Input Data Register by CLK when ENI is asserted. Two’s complement. SH0-1 24, 25 I Shift Control Inputs. These lines control the input shifters of the RIN and IIN inputs of the complex multiplier. The shift controls are common to the shifters on both of the busses. SH1 SH0 SELECTED BITS 0 0 RIN0-15, IMIN0-15 0 1 RIN1-16, IMIN1-16 1 0 RIN2-17, IMIN2-17 1 1 RIN3-18, IMIN3-18 ACC 26 I Accumulate/Dump Control. This input controls the complex accumulators and their holding registers. When high, the accumulators accumulate and the holding registers are disabled. When low, the feedback in the accumulators is zeroed to cause the accumulators to load. The holding registers are enabled to clock in the results of the accumulation. This input is registered by CLK. BINFMT 31 I This input is used to convert the two’s comple ment output to offset binary (unsigned) for applications using D/A converters. When low, bits RO19 and IO19 are inverted from the internal two’s complement representation. This input is registered by CLK. PEAK 29 I This input enables the peak detect feature of t he block floating point detector. When high, the maximum bit growth in the Output Holding Registers is encoded and output on the DET0-1 pins. When the PEAK input is asserted, the block floating point detector output will track the maximum growth in the holding registers, including the data in the Holding Registers at the time that PEAK is activated. Pin Descriptions (Continued) NAME NUMBER TYPE DESCRIPTION HSP45116A

6 FN4156.4 May 7, 2007 OUTMUX0-1 71, 72 I These inputs select the data to be output on RO0-19 and IO0-19. OUT MUX OUT MUX

0 RO16-19 RO0-15 IO16-19 IO0-15

00 R e a l C M A C

01 R e a l C M A C

0, Real CMAC 0-14 Imag CMAC 31-34 0, Imag CMAC 0-14

10 R e a l A C C

1 1 Reserved Reserved Reserved Reserved RO0-19 84-86, 88-91, 93, 103-107, 109 O Real Output Data Bus. R19 is the MSB. These three-state outputs are controlled by OER and OEREXT. OUTMUX0-1 select the data output on the bus. IO0-19 110, 112, 113, 115-118, 121-123, 126-130, 133-137 O Imaginary Output Data Bus. I19 is the MSB. These three-state outputs are controlled by OEI and OEIEXT. OUTMUX0-1 select the data output on the bus. DET0-1 81, 82 O These output pins indicate the number of bits of growth in the accumulators. While PEAK is low, these pins indicate the peak growth. The detect or examines bits 15-18, real and imaginary accumulator holding registers and bits 30-33 of the real and imaginary CMAC Holding Registers. The bits indicate the largest growth of the four registers. DET 1 DET 0 NUMBER OF BITS OF GROWTH ABOVE 2o 00 0 01 1 10 2 11 3 OER 74 I Three-state control for bits RO0-15. Outputs are enabled when the line is low. OEREXT 76 I Three-state control for bits RO16-19. Outputs are enabled when the line is low. OEI 78 I Three-state control for bits IO0-15. Outputs are enabled when the line is low. OEIEXT 77 I Three-state control for bits IO16-19. Outputs are enabled when the line is low. RND 75 I Round Enable. This input enables rounding of the output data precision from 9 to 20 bits. This input is active “low”. This input must be tied either high or low. Pin Descriptions (Continued) NAME NUMBER TYPE DESCRIPTION HSP45116A

Diagram), the NCOM calculates an FFT butterfly. them by the input vector to form the modulated output. (USB) or lower Sideband (LSB) applications. mark the passage of a preprogrammed period of time. Adder, which adds an offset to the top 16 bits of the phase. cosine, which is passed to the Sine/Cosine Generator.

1. MOD0-1 and are used to generate a Quad Phase Shift

TABLE 1. AD0-1 DECODING 1 0 0 ↑ Load phase register.

16 LSBs

FIGURE 1. HSP45116A BLOCK DIAGRAM

FIGURE 1. HSP45116A BLOCK DIAGRAM (Continued)

the internally generated sine and cosine. output of the PFCS will increment by one after every clock.

1. If the input to the Center

clearing the contents of the register. TABLE 2. MOD0-1 DECODE value of the phase increment summer on the next clock. digital synthesis, etc. Modulo π is used to calculate FFTs. This is explained in greater detail in the Applications Section. bits, it is added to the top 16 bits of the Phase Accumulator. 16-bit sine and cosine inputs to the CMAC. FIGURE 2. SINE/COSINE SECTION computed value of the complex vector is less than -90.2dB.

TABLE 3. INPUT SHIFT SELECTION stored in the CMAC Output Registers. TABLE 4. OUTPUT MULTIPLEXER SELECTION

1. If PEAK is low, the highest value of

DET0-1 is latched in the Growth Detect Output Register.

1. Note that the binary point of

facilitate cascading NCOMs for FFT applications. TABLE 5. GROWTH ENCODING

FIGURE 3. BIT WEIGHTING

bits loaded into the Control Register as shown in Table 6. TABLE 6. ROUNDING CONTROL

Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 1) θJA (°C/W) http://www.intersil.com/pbfree/Pb-FreeReflow.asp Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 15 FN4156.4 May 7, 2007 PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Power Supply Current ICCOP VCC = Max, CLK Frequency 52.6MHz Notes 2, 3 - 184 mA Standby Power Supply Current ICCSB VCC = Max, Outputs Not Loaded - 500 μA Input Leakage Current II VCC = Max, Input = 0V or VCC -10 10 μA Output Leakage Current IO VCC = Max, Input = 0V or VCC -10 10 μA Logical One Input Voltage VIH VCC = Max 2.0 - V Logical Zero Input Voltage VIL VCC = Min - 0.8 V Logical One Input Voltage: CLK VIHC VCC = Max 3.0 - V Logical One Output Voltage VOH IOH = -5mA, VCC = Min 2.6 - V Logical Zero Output Voltage VOL IOL = 5mA, VCC = Min - 0.4 V Input Capacitance CIN CLK Frequency 1MHz All measurements referenced to GND. TA = +25°C, Note 4 - 10 pF Output Capacitance COUT - 10 pF NOTES: 2. Power supply current is proportional to frequency. Typical rating is 3.5mA/MHz. 3. Output load per test circuit and CL = 40pF. 4. Not tested, but characterized at initial design and at major process/design changes. PARAMETER SYMBOL NOTES 52.6MHz (-52) UNITSMIN MAX CLK Period tCP 19 - ns CLK High tCH 7 - ns CLK Low tCL 7 - ns WR Low tWL 7 - ns WR High tWH 7 - ns Setup Time AD0-1, CS to WR tAWS 10 - ns Hold Time AD0-1, CS from WR tAWH 0 - ns Setup Time C0-15 to WR tCWS 10 - ns Hold Time C0-15 from WR tCWH 0 - ns HSP45116A

16 FN4156.4 May 7, 2007 AC Test Load Circuit EQUIVALENT CIRCUIT CL (NOTE) IOH 1.5V I OL DUT SWITCH S1 OPEN FOR ICCSB AND ICCOP NOTE: Test head capacitance. Setup Time WR to CLK tWC 7 10 - ns Setup Time MOD0-1 to CLK tMCS 10 - ns Hold Time MOD0-1 from CLK tMCH 0 - ns Setup Time PACI to CLK tPCS 10 - ns Hold Time PACI from CLK tPCH 0 - ns Setup Time ENPHREG, ENCFREG, ENOFREG, ENPHAC, ENTIREG, CLROFR, PMSEL, LOAD, ENI, ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD to CLK tECS 10 - ns Hold Time ENPHREG, ENCFREG, ENOFREG, ENPHAC, ENTIREG, CLROFR, PMSEL, LOAD, ENI, ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD from CLK tECH 0 - ns Setup Time RIN0-18, IMIN0-18 to CLK tDS 10 - ns Hold Time RIN0-18, IMIN0-18 from CLK tDH 0 - ns CLK to Output Delay RO0-19, IO0-19 tDO - 12 ns CLK to Output Delay DET0-1 tDEO - 12 ns CLK to Output Delay PACO tPO - 12 ns CLK to Output Delay TICO tTO - 12 ns Output Enable Time OER, OEI, OEREXT, OEIEXT tOE - 8 ns Output Enable Time OUTMUX0-1 tMD - 14 ns Output Disable Time tOD 6 - 8 ns Output Rise, Fall Time tRF 6 - 4 ns NOTES: 6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes. 7. Applicable only when outputs are being monitored and ENCFREG, ENPHREG or ENTIREG is active. WR is always asynchronous when RND is active. PARAMETER SYMBOL NOTES 52.6MHz (-52) UNITSMIN MAX HSP45116A

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN4156.4 May 7, 2007 HSP45116A Metric Plastic Quad Flatpack Packages (MQFP) D E E1 -A- PIN 1 A2 A1 A 12o-16o 12o-16o 0o-7o 0.40

0.016 MIN

L 0o MIN PLANE b 0.005/0.009 0.13/0.23WITH PLATING BASE METAL SEATING 0.005/0.007 0.13/0.17 -B- e 0.008

0.20 A-B SD SCM

0.076 0.003 -C- -D- -H- Q160.28x28 (JEDEC MS-022DD-1 ISSUE B)

160 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE

A - 0.161 - 4.10 - A2 0.126 0.142 3.20 3.60 - B 0.009 0.015 0.22 0.38 6 B1 0.009 0.013 0.22 0.33 - D 1.223 1.233 31.08 31.32 3 D1 1.097 1.107 27.88 28.12 4, 5 E 1.224 1.232 31.10 31.30 3 E1 1.098 1.106 27.90 28.10 4, 5 L 0.029 0.040 0.73 1.03 - N 160 160 7 e 0.026 BSC 0.65 BSC - Rev. 1 4/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and toler ances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane . 4. Dimensions D1 and E1 to be determined at datum plane 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. “N” is the number of terminal positions. -C- -H-