HSP45116AVC-52

HSP45116 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 18

Technical content

Features

• NCO and CMAC on One Chip
• 15MHz, 25.6MHz, 33MHz Versions
• 32-Bit Frequency Control
• 16-Bit Phase Modulation
• 16-Bit CMAC
• 0.008Hz Tuning Resolution at 33MHz
• Spurious Frequency Components < -90dBc
• Fully Static CMOS

Applications

• Frequency Synthesis
• Modulation - AM, FM, PSK, FSK, QAM
• Demodulation, PLL
• Phase Shifter
• Polar to Cartesian Conversions Block Diagram

Ordering Information

TEMP. RANGE ( oC) PACKAGE PKG. NO. HSP45116VC-15 0 to 70 160 Ld MQFP Q160.28x28 HSP45116VC-25 0 to 70 160 Ld MQFP Q160.28x28 HSP45116GC-15 0 to 70 145 Ld CPGA G145.A HSP45116GC-25 0 to 70 145 Ld CPGA G145.A HSP45116GC-33 0 to 70 145 Ld CPGA G145.A HSP45116GI-15 -40 to 85 145 Ld CPGA G145.A HSP45116GI-25 -40 to 85 145 Ld CPGA G145.A HSP45116GI-33 -40 to 85 145 Ld CPGA G145.A HSP45116GM-15/883 -55 to 125 145 Ld CPGA G145.A HSP45116GM-25/883 -55 to 125 145 Ld CPGA G145.A HSP45116AVC-52 0 to 70 160 Ld MQFP Q160.28x28 † This part has its own data sheet under HSP45116A, AnswerFAX document no. 4156. PHASE/ FREQUENCY CONTROL SECTION SINE/ COSINE SECTION CMAC SINE/ COSINE ARGUMENT SIN COS VECTOR INPUT VECTOR OUTPUT RI RI MICROPROCESSOR INTERFACE INDIVIDUAL CONTROL SIGNALS Data Sheet May 1999 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

145 PIN PGA

A B C D E F G H J K L M N P Q A B C D E F G H J K L M N P Q 123456789 1 0 1 1 1 2 1 3 1 4 1 5 123456789 1 0 1 1 1 2 1 3 1 4 1 5 GND VCC VCC VCC GND GND GND GND VCC VCC GND VCC GND IMINIMINIMIN IMIN IMINIMINIMINIMIN INDEX RIN RIN RIN RIN RIN RIN RIN RIN RIN RIN ACC CLK AD C C MOD ENOF REG AD C C C C 314 71 1 1 2 236 1 2 5 7 10 13 PACO RO RO RO RO RO IO IO RO IO IO IO IO RO RO RO RO RO RO RO RO RO RO RO RO DET RO OEREXT OEI RO OEIEXT DET C C OER C C C TICO PACI BINFMT PEAKENPH REG MOD LO AD CLR OFR ENI ENCF REG ENTIREG WR CS MODPI /2PI C C C C SH RBY TILD RIN RIN SH PMSEL ENPHA C C IMIN IMIN IO IO IO IO IO IO IO IO IO IO IO IMIN IO IO IO VCC GND V CCIMIN IMIN IMIN IMIN IMIN IMIN IMIN RIN RIN RIN RIN IMIN RIN RIN RIN OUT- MUX OUT- MUX HSP45116

Pinouts (Continued) A B C D E F G H J K L M N P Q A B C D E F G H J K L M N P Q 123456789101112131415 123456789101112131415 GND VCC VCC VCC GND GND GNDGND V CCVCC GND VCC GND IMIN IMIN IMINIMIN IMIN IMIN IMIN IMIN INDEX RINRINRIN RINRIN RINRIN RINRINRIN ACC CLK AD C C MOD ENOF REG AD C C C C 314 71112 23612 571013 PACO RO RO RO RO RO IO IO RO IO IO IO IO RO RO RO RO RO RO RO RO RO RO RO RO DET RO OEREXTOEIRO OEIEXTDET C C OER C C C TICOPACI BINFMT PEAK ENPH REG MOD LO AD CLR OFR ENI ENCF REG ENTIREG WR CS MODPI /2PI C C C C SH RBY TILD RIN RIN SH PMSEL ENPHA C C IMIN IMIN IO IO IO IO IO IO IO IO IO IO IO IMIN IO IO IO VCCGNDVCC IMIN IMIN IMIN IMIN IMIN IMIN IMIN RIN RIN RIN RIN IMIN RIN RIN RIN OUT- MUX OUT- MUX HSP45116

Pinouts (Continued) 119 120 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 126 127 128 129 130 131 121 122 123 124 125 137 138 139 140 132 133 134 135 136 146 147 148 149 150 151 141 142 143 144 145 157 158 159 160 152 153 154 155 156 RO9 VCC RO8 RO7 RO6 RO5 GND RO10 RO18 RO17 RO16 RO15 V CC RO13 RO12 RO11 GND RO14 GND IO6 IO5 IO4 IO3 IO2 IO1 V CC IO0 RO19 GND GND RO2 RO1 RO0 DET1 DET0 GND V CC RO4 RO3 NC CLR OFR ENCFREG ENPHA C ENTIREG ENI MODPI/2PI CS GND CLK VCC AD1 AD0 WR C15 C14 C13 C12 C11 C10 GND NC OUTMUX1 OUTMUX0 GND OER VCC OEREXT OEIEXT OEI PACO MOD1 VCC TICO GND RBYTILD MOD0 PACI LO AD PMSEL NC PEAK RIN0 VCC SH1 SH0 ACC ENPHREG ENOFREG BINFMT RIN6 RIN7 RIN8 RIN9 RIN11 RIN5 RIN4 RIN3 RIN2 GND RIN12 RIN17 RIN18 IMIN0 RIN16 RIN15 RIN14 GND RIN13 RIN10 IO7 IO8 IO9 V CC GND IO10 IO11 IO12 IO13 IO14 GND V CC IO15 IO16 IO17 IO18 IO19 IMIN18 IMIN17 IMIN16 IMIN15 IMIN14 GND IMIN13 V CC IMIN12 IMIN11 IMIN10 IMIN9 NC IMIN8 IMIN7 IMIN6 IMIN5 IMIN4 IMIN3 IMIN2 GND IMIN1 V CC RIN1 HSP45116

NAME NUMBER TYPE DESCRIPTION VCC A1, A9, A15, G1, J15, Q1, Q7, Q15 - +5V Power supply input. GND A8, A14, B1, H1, H15, P15, Q2, Q8 - Power supply ground input. Q9-14 I Control input bus for loading phase and frequency data into the PFCS. C15 is the MSB. AD0-1 N7, P7 I Address pins for selecting destination of C0-15 data. CS P6 I Chip Select (active low). WR Q6 I Write Enable. Data is clocked into the register selected by AD0-1 on the rising edge of WR when theCS line is low. CLK Q5 I Clock. All registers, except the control registers clocked with WR, are clocked (when enabled) by the rising edge of CLK. ENPHREG M1 I Phase Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto chip,ENPHREG enables the clocking of data into the phase register. ENOFREG N1 I Frequency Offset Register Enable (active Low). Registered on chip by CLK. When active, after being clocked onto chip,ENOFREG enables clocking of data into the frequency offset register. ENCFREG N5 I Center Frequency Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto chip,ENCFREG enables clocking of data into the center frequency register. ENPHA C Q3 I Phase Accumulator Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto chip,ENPHA C enables clocking of the phase accumulator register. ENTIREG P5 I Time Interval Control Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto chip,ENTIREG enables clocking of data into the time accumulator register. ENI Q4 I Real and Imaginary Data Input Register (RIR, IIR) Enable (active low). Registered on chip by CLK. When active, after being clocked onto chip,ENI enables clocking of data into the real and imaginary input data register. MODPI/ 2PI N6 I Modulo π/2π Select. When low, the Sine and Cosine ROMs are addressed modulo 2π (360 degrees). When high, the most significant address bit is held low so that the ROMs are addressed moduloπ (180 degrees). This input is registered on chip by clock. CLR OFR P4 I Frequency Offset Register Output Zero (active low). Registered on chip by CLK. When active, after being clocked onto chip,CLR OFR zeros the data path from the frequency offset register to the frequency adder. New data can still be clocked into the frequency offset register;CLR OFR does not affect the contents of the register. LO AD N4 I Phase Accumulator Load Control (active low). Registered on chip by CLK. Zeroes feedback path in the phase accumulator without clearing the phase accumulator register. MOD0-1 M3, N3 I External Modulation Control Bits. When selected with the PMSEL line, these bits add a 0, 90, 180, or 270 degree offset to the current phase in the phase accumulator. The lower 14 bits of the phase control path are set to zero. These bits are loaded into the phase register when ENPHREG is low. PMSEL P3 I Phase Modulation Select Line. This line determines the source of the data clocked into the phase register. When high, the phase control register is selected. When low, the external modulation pins (MOD0-1) are selected for the most significant two bits and the least significant two bits and the least significant 14 bits are set to zero. This control is registered by CLK. RBYTILD L3 I ROM Bypass, Timer Load. Active low, registered by CLK. This input bypasses the sine/ cosine ROM so that the 16-bit phase adder output and lower 16 bits of the phase accumulator go directly to the CMAC’s sine and cosine inputs, respectively. It also enables loading of the timer accumulator register by zeroing the feedback in the accumulator. PACI P2 I Phase Accumulator Carry Input (active low). A low on this pin causes the phase accumulator to increment by one, in addition to the values in the phase accumulator register and frequency adder. HSP45116

PACO L13 O Phase Accumulator Carry Output. Active low and registered by CLK. A low on this output indicates that the phase accumulator has overflowed, i.e., the end of one sine/cosine cycle has been reached. TICO P1 O Time Interval Accumulator Carry Output. Active low, registered by CLK. This output goes low when a carry is generated by the time interval accumulator. This function is provided to time out control events such as synchronizing register clocking to data timing. RIN0-18 C1, C2, D1, D2, E1- 3, F1-3, G2, G3, H2, H3, J1-3, K1, I Real Input Data Bus. This is the external real component into the complex multiplier. The bus is clocked into the real input data register by CLK when ENI is asserted; two’s complement. IMIN0-18 A2-7, B2-7, C3-8, I Imaginary Input Data Bus. This is the external imaginary component into the complex multiplier. The bus is clocked into the real input data register by CLK whenENI is asserted; two’s complement. SH0-1 K3, L1 I Shift Control Inputs. These lines control the input shifters of the RIN and IIN inputs of the complex multiplier. The shift controls are common to the shifters on both of the busses. ACC L2 I Accumulate/Dump Control. This input controls the complex accumulators and their holding registers. When high, the accumulators accumulate and the holding registers are disabled. When low, the feedback in the accumulators is zeroed to cause the accumulators to load. The holding registers are enabled to clock in the results of the accumulation. This input is registered by CLK. BINFMT N2 I This input is used to convert the two’s complement output to offset binary (unsigned) for applications using D/A converters. When low, bits RO19 and IO19 are inverted from the internal two’s complement representation. This input is registered by CLK. PEAK M2 I This input enables the peak detect feature of the block floating point detector. When high, the maximum bit growth in the output holding registers is encoded and output on the DET0-1 pins. When the PEAK input is asserted, the block floating point detector output will track the maximum growth in the holding registers, including the data in the holding registers at the time thatPEAK is activated. OUTMUX0-1 N12, N13 I These inputs select the data to be output on RO0-19 and IO0-19. RO0-19 C15, D14, D15, E14, E15, F13-15, G13-15, H13, H14, J13, J14, K13-15, L15, M15 O Real Output Data Bus. These Three-state outputs are controlled byOER and OEREXT. OUTMUX0-1 select the data output on the bus. IO0-19 A10-13, B8-15, C9- 14, D13, E13 O Imaginary Output Data Bus. These Three-state outputs are controlled byOEI and OEIEXT. OUTMUX0-1 select the data output on the bus. DET0-1 N15, L14 O These output pins indicate the number of bits of growth in the accumulators. While PEAK is low, these pins indicate the peak growth. The detector examines bits 15-18, real and imaginary accumulator holding registers and bits 30-33 of the real and imaginary CMAC holding registers. The bits indicate the largest growth of the four registers. OER P14 I Three-state control for bits RO0-15. Outputs are enabled when the line is low. OEREXT M13 I Three-state control for bits RO16-19. Outputs are enabled when the line is low. OEI M14 I Three-state control for bits IO0-15. Outputs are enabled when the line is low. OEIEXT N14 I Three-state control for bits IO16-19. Outputs are enabled when the line is low. Pin Description (Continued) NAME NUMBER TYPE DESCRIPTION HSP45116

R.RBYTILD R.PMSEL R.ENPHREG R E G >CLK PACI PHASE INPUT REGISTER MS INPUT REGISTER PHEN 0 16 R.ENPHREG LS INPUT REGISTER LSEN OFFSET REGISTER CENTER FREQUENCY REGISTER R.PMSEL FREQUENCY ADDER A D D E R PHASE REGISTER R.CLR OFR 32MSEN CLK R.ENCF REG R.LOAD R.ENOFREG MOD(1:0) ENCODE C(15:0) PHASE ACCUMULATOR ADDER PHASE ADDER SIN/COS ARGUMENT A D D E R

16 MSBs

16 LSBs

R.MODPI/2PI MSB R.ENPHA C A D D E R PHASE ACCUMULATOR REGISTER PHASE ACCUMULATOR DECODER R.ENCFREG R.ENOFREG R.CLR OFR R.LOAD R.ENPHA C R.MODPI/2PI PMSEL ENCFREG CLR OFR LO AD ENPHREG ENPHA C MODPI/2PI ENOFREG CLK TIME INCREMENT32 R.ENTIREG 32 32 32 CARRY OUTTIME ACCUMULATOR REGISTER R.RBYTILD TICO ADDER AD(1:0) CS WR ENTIREG RBYTILD R.ENTIREG ACC R.ENIENI R.BINFMTBINFMT R.SH(1:0)SH(1:0) PEAK R.PEAK SINE/COSINE GENERATOR TIME ACCUMULATOR OUTMUX(1:0) OEREXT OER OEIEXT OEI TICO PACO RIN(18:0) IMIN(18:0) CLK PHASE R.ACC R.ENI R.BINFMT R.SH(1:0) R.PEAK R.ACC FREQUENCY R E R E R E R E R E CLK R E CLK R E CLK R E G>CLK CLK R E R E G>CLK CLK R E R E G>CLK R E G>CLK PACI R E G 0 1 MUX 1 0 MUX 0 1 MUX 0 1 MUX 1 0 MUX RIN(18:0) IMIN(18:0) HSP45116

Functional Block Diagram (Continued) ADDER R1.ACC 0 0 16 16 SHIFTERSHIFTER R.SH(1:0) R.ENI 1919 SIN COS COMPLEX MULTIPLIER 33 33 ADDER ADDER ADDER COMPLEX ACCUMULATOR CMAC ACCUMULATOR R.PEAK GROWTH DETECT DET(1:0) 163FMT 164OUTMUX(1:0) RO(19-16) RO(15:0) R.BINFMT OEREXT OER 16FMT 164 OUTMUX(1:0) IO(19-16) IO(15:0) R.BINFMT OEIEXT OEI 35 35 20 R1.ACC R2.ACC ROUND ROUND RIN0-18 IMIN0-18 R.RBYTILD R.ENI R.SH(1:0) SIN COS R.ACC R.PEAK R.SH(1:0) R.ENI OUTMUX(1:0) See Table 4 CLK R E CLK R E REG>CLK REG>CLKREG>CLK REG> CLK R E G>CLK R E G>CLK REG>CLK REG> CLK REG>CLK CLKREG < REG>CLKCLKREG < REG>CLK REG>CLK REG <CLK REG>CLK REG <CLK 0 1 MUX 1 0 MUX MUX 0 1 MUX 0 1 MUX MUX OUTMUX(1:0) See Table 4 1 0 MUX CLKREG < CLKREG < 1 0 MUX PHASE RIN(18:0) IMIN(18:0) HSP45116

Diagram), the NCOM calculates an FFT butterfly. them by the input vector to form the modulated output. Adder, which adds an offset to the top 16 bits of the phase. cosine, which is passed to the Sine/Cosine Generator.

1. MOD0-1 are used to generate a Quad Phase Shift Keying

TABLE 1. AD0-1 DECODING

the internally generated sine and cosine. output of the PFCS will increment by one after every clock.

1. If the input to the Center

clearing the contents of the register. value of the phase increment summer on the next clock. digital synthesis, etc. Moduloπ is used to calculate FFTs. This is explained in greater detail in the Applications Section. bits, it is added to the top 16 bits of the Phase Accumulator. 16-bit sine and cosine inputs to the CMAC.

1. An address of zero corresponds to

computed value of the complex vector is less than -90.2dB. TABLE 2. MOD0-1 DECODE FIGURE 1. SINE/COSINE SECTION

stored in the CMAC Output Registers. TABLE 3. INPUT SHIFT SELECTION TABLE 4. OUTPUT MULTIPLEXER SELECTION

0 RO16-19 RO0-15 IO16-19 IO0-15

FIGURE 2. COMPLEX MULTIPLIER/ACCUMULATOR; ALL REGISTERS CLOCKED BY CLK

DET0-1 is latched in the Growth Detect Output Register. facilitate cascading NCOMs for FFT applications. FIGURE 3. BIT WEIGHTING TABLE 5. GROWTH ENCODING

Absolute Maximum Ratings Thermal Information Operating Conditions oC to 70oC Thermal Resistance (Typical, Note 1)θJA (oC/W) θJC (oC/W) Maximum Junction Temperature (MQFP - Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Logical One Input Voltage V IH VCC = 5.25V 2.0 - V Logical Zero Input Voltage V IL VCC = 4.75V - 0.8 V High Level Clock Input V IHC VCC = 5.25V 3.0 - V Low Level Clock Input V ILC VCC = 4.75V - 0.8 V Output HIGH Voltage V OH IOH = -400mA, VCC = 4.75V 2.6 - V Output LOW Voltage V OL IOL = 2.0mA, VCC = 4.75V - 0.4 V Input Leakage Current I I VIN = VCC or GND, VCC = 5.25V -10 10 µA I/O Leakage Current I O VOUT = VCC or GND, VCC = 5.25V -10 10 µA Standby Power Supply Current I CCSB VIN = VCC or GND VCC = 5.25V, Note 4 - 500 µA Operating Power Supply Current I CCOP f = 15MHz, VIN = VCC or GND, VCC = 5.25V, Notes 2 and 4 - 182 mA Capacitance TA = 25oC, Note 3 PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Input Capacitance C IN FREQ = 1MHz, VCC = Open, All measurements are referenced to device ground -1 5 p F Output Capacitance C O -1 5 p F NOTES: 2. Power supply current is proportional to operating frequency. Typical rating for ICCOP is 10mA/MHz. 3. Not tested, but characterized at initial design and at major process/design changes. 4. Output load per test load circuit with switch open and C L = 40pF. HSP45116

UNITSMIN MAX MIN MAX MIN MAX CLK Period t CP 6 6-3 9-3 0- n s CLK High t CH 2 6-1 5-1 2- n s CLK Low t CL 2 6-1 5-1 2- n s WR Low t WL 2 6-1 5-1 2- n s WR High t WH 2 6-1 5-1 2- n s Setup Time; AD0-1,CS toWR Going High t AWS 1 8-1 3-1 3- n s Hold Time; AD0, AD1,CS fromWR Going High t AWH 0-0-0- n s Setup Time C0-15 fromWR Going High t CWS 2 0-1 5-1 5- n s Hold Time C0-15 fromWR Going High t CWH 0-0-0- n s Setup timeWR High to CLK High t WC 7 2 0-1 6-1 2- n s Setup Time MOD0-1 to CLK Going High t MCS 2 0-1 5-1 5- n s Hold Time MOD0-1 from CLK Going High t MCH 0-0-0- n s Setup TimePACI to CLK Going High t PCS 2 5-1 5-1 1- n s Hold TimePACI from CLK Going High t PCH 0-0-0- n s SetupENPHREG, ENCFREG, ENOFREG, ENPHA C,ENTIREG, CLR OFR, PMSEL, LO AD, ENI, ACC, BINFMT, PEAK, MODPI/ 2PI, SH0-1,RBYTILD from CLK Going High tECS 1 8-1 2-1 2- n s Hold TimeENPHREG, ENCFREG, ENOFREG, EN- PHA C, ENTIREG, CLR OFR, PMSEL, LO AD, ENI, ACC, BINFMT, PEAK, MODPI/ 2PI, SH0-1,RBYTILD from CLK Going High tECH 0-0-0- n s Setup Time RIN0-18, IMIN0-18 to CLK Going High tDS 1 8-1 2-1 2- n s Hold Time RIN0-18, IMIN0-18 from CLK Going High tDH 0-0-0- n s CLK to Output Delay RO0-19, IO0-19 t DO -4 0-2 4-1 9n s CLK to Output Delay DET0-1 t DEO -4 0-2 7-2 0n s CLK to Output DelayPACO t PO -3 0-2 0-1 2n s CLK to Output DelayTICO t TO -3 0-2 0-1 2n s Output Enable TimeOER, OEI,OEREXT, OEIEXT t OE -2 5-2 0-2 0n s OUTMUX0-1 to Output Delay t MD -4 0-2 8-2 6n s Output Disable Time t OD 6 -2 0-1 5-1 5n s Output Rise, Fall Time t RF 6 -8-8-6n s NOTES: 5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; input levels (all other inputs) 0V and 3.0V; timing reference levels (CLK) ≤ 1.5V. 6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 7. Applicable only when outputs are being monitored andENCFREG, ENPHREG, or ENTIREG is active. HSP45116

FIGURE 7. INPUT AND OUTPUT TIMING NOTE: Test head capacitance.

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FIGURE 8. CONTROL BUS TIMING FIGURE 9. OUTPUT ENABLE, DISABLE TIMING FIGURE 10. MULTIPLEXER TIMING FIGURE 11. OUTPUT RISE AND FALL TIMES