HSP45106JC-25

HSP45106 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

• 25.6MHz, 33MHz Versions
• 32-Bit Center and Offset Frequency Control
• 16-Bit Phase Control
• 8 Level PSK Supported Through Three Pin Interface
• Simultaneous 16-Bit Sine and Cosine Outputs
• Output in Two’s Complement or Offset Binary
• <0.008Hz Tuning Resolution at 33MHz
• Serial or Parallel Outputs
• Spurious Frequency Components <-90dBc
• 16-Bit Microprocessor Compatible Control Interface

Applications

• Direct Digital Synthesis
• Quadrature Signal Generation
• Spread Spectrum Communications
• PSK Modems
• Modulation - FM, FSK, PSK (BPSK, QPSK, 8PSK)
• Frequency Hopping Communications
• Precision Signal Generation
• Related Products - Use with Data Acquisition Parts HI5731 or HI5741 Block Diagram

Ordering Information

TEMP. RANGE (oC) PACKAGE PKG. NO. HSP45106JC-25 0 to 70 84 Ld PLCC N84.1.15 HSP45106JI-25 -40 to 85 84 Ld PLCC N84.1.15 HSP45106JC-33 0 to 70 84 Ld PLCC N84.1.15 HSP45106GC-33 0 to 70 85 Ld CPGA G85.A PHASE/ FREQUENCY CONTROL SECTION SINE/ COSINE SECTION SINE COSINE CLOCK MICROPROCESSOR INTERFACE DISCRETE CONTROL SIGNALS SIN/COS ARGUMENT Data Sheet October 1999

85 PIN CPGA

V CC COS9 COS12 COS13 COS14 OEC COS2 COS4 COS8 COS10 GND COS15 TICO COS6 COS7 COS11 INDEX PIN C0C0C0C0C0C0GNDA0 MOD1 A2 A1 C15 C12 C13 V CC C4 C9 C6 INHOF ENOF WR INITT ENPO ENTI ENCF CS GND VCC TEST MOD2 MOD0 INITPAC PAR/ EN PACI A B C D E F G H J K L 11 10 9 8 7 6 5 4 3 2 1 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L PIN ‘A1’ ID C10 STRB SER PHAC REG REG REG REG C0PMSEL GNDSIN1 SIN0SIN3 BINFMTVCCCLKSIN2VCC SIN6 SIN5SIN4 SIN8 SIN7 SIN9 SIN10 SIN11 SIN12 GND SIN13 SIN15 SIN14 OES DAC COS0 COS1 COS3 COS5 VCC COS9 COS12 COS13 COS14 OEC COS2 COS4 COS8 COS10 GND COS15 TICO COS6 COS7 COS11 INDEX PIN C0 C0 C0 C0 C0 C0 GND A0 MOD1A2A1C15C12C13VCCC4 C9C6 INHOF ENOF WR INITT ENPO ENTI ENCF CSGND VCCTEST MOD2MOD0 INITPACPAR/ ENPACI A B C D E F G H J K L 1110987654321 1110987654321 A B C D E F G H J K L PIN ‘A1’ ID C10 STRB SER PHAC REG PMSEL REGREGREG HSP45106

84 LEAD PLCC

VCC +5 power supply pin. GND Ground. C(15:0) I Control input bus for loading phase, frequency, and timer data into the PFCS. C0 is LSB. A(2:0) I Address pins for selecting destination of C(15:0) data (Table 2). A0 is the LSB CS I Chip select (active low). Enables data to be written into Control Registers by WR. WR I Write enable (active low). Data is clocked into the register selected by A(2:0) on the rising edge of WR when CS is low. CLK I Clock. All registers, except the Control Registers clocked with WR, are clocked (when enabled) by the rising edge of CLK. ENPOREG I Phase Offset Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto chip, ENPOREG enables the clocking of data into the Phase Offset Register. Allows ROM address to be updated regardless of ENPHAC. ENOFREG I Offset Frequency Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto chip, ENOFREG enables the clocking of data into the Offset Frequency Register. ENCFREG I Center Frequency Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto chip, ENCFREG enables the clocking of data into the Center Frequency Register. ENPHAC I Phase Accumulator Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto chip, ENPHAC enables the clocking of data into the Phase Accumulator Register. ENTIREG I Timer Increment Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto chip, ENTIREG enables the clocking of data into the Timer Increment Register. INHOFR I Inhibit Offset Frequency Register Output (active low). Registered on chip by CLK. When active, after being clocked onto chip, INHOFR zeroes the data path from the Offset Frequency Register to the Frequency Adder. New data can be still clocked into the Offset Frequency Register. INHOFR does not affect the contents of the register. INITPAC I Initialize Phase Accumulator (active low). Registered on chip by CLK. Zeroes the feedback path in the Phase Accumulator. Does not clear the Phase Accumulator Register. MOD(2:0) I Modulation Control Inputs. When selected with the PMSEL line, these bits add an offset of 0, 45, 90, 135, 180, 225, 270, or 315 degrees to the current phase (i.e., modulate the output). The lower 13 bits of the phase control are set to zero. These bits are registered when the Phase Offset Register is enabled. Pinouts (Continued) GND CLK SIN0 SIN1 SIN2 SIN3 SIN4 V CC SIN5 SIN6 SIN7 SIN8 SIN9 SIN10 SIN11 SIN12 GND SIN13 SIN14 SIN15 OES 1 1 1 0 987654321 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 TICO COS15 COS14 COS13 GND COS12 COS11 COS10 COS9 COS8 COS7 COS6 COS5 COS4 V CC COS3 COS2 COS1 COS0 OEC DACSTRB PMSEL MOD0 MOD1 MOD2 TEST V CC WR GND CS ENCFREG ENOFREG INHOFR ENTIREG INITTAC ENPOREG INPHAC PACI INITPAC BINFMT PAR/SER VCC V CC C10 C11 C12 C13 C14 C15 GND HSP45106

The 16-bit Numerically Controlled Oscillator (NCO16) produces a digital complex sinusoid waveform whose frequency and phase are controlled through a standard microprocessor interface and discrete inputs. The NCO16 generates 16-bit sine and cosine vectors at a maximum sample rate of 33MHz. The NCO16 can be preprogrammed to produce a constant (CW) sine and cosine output for Direct Digital Synthesis (DDS) applications. Alternatively, the phase and frequency inputs can be updated in real time to produce a FM, PSK, FSK, or MSK modulated waveform. To simplify PSK generation, a 3 pin interface is provided to support modulation of up to 8 levels. As shown in Figure 1, the HSP45106 Block Diagram, the NCO16 is comprised of a Phase and Frequency Control Section (PFCS) and Sine/ Cosine Section. The PFCS stores the phase and frequency control inputs and uses them to calculate the phase angle of a rotating complex vector. The Sine/Cosine Section performs a lookup on this phase and generates the appropriate amplitude values for the sine and cosine. These quadrature outputs may be configured as serial or parallel with either two's complement or offset binary format. Phase/Frequency Control Section The phase and frequency of the quadrature outputs are controlled by the PFCS (Figure 1). The PFCS generates a 32-bit word which represents the instantaneous phase (Sin/Cos argument) of the sine and cosine waves being generated. This phase is incremented on the rising edge of each CLK by the preprogrammed amounts in the phase and Frequency Control Registers. As the instantaneous phase steps from 0 through full scale (2 32 - 1), the phase of the quadrature outputs proceeds from 0o around the unit circle counter clockwise. The PFCS is comprised of a Phase Accumulator Section, Phase Offset adder, Input Section, and a Timer Accumulator Section. The Phase Accumulator computes the instantaneous phase angle from user programmed values in the Center and Offset Frequency Registers. This angle is then fed into the Phase Offset adder where it is offset by the preprogrammed value in the Phase Offset Register. The Input Section routes data from a microprocessor compatible control bus and discrete input signals into the appropriate configuration registers. The Timer Accumulator supplies a pulse to mark the passage of a user programmed period of time. PMSEL I Phase Modulation Select input. Registered on chip by CLK. This input determines the source of the data clocked into the Phase Offset Register. When high, the Phase Input Register is selected. When low, the external modulation pins (MOD(2:1)) control the three most significant bits of the Phase Offset Register and the 13 least significant bits are set to zero. PACI I Phase Accumulator Carry Input (active low). Registered on chip by CLK. INITTAC I Initialize Timer Accumulator (active low). This input is registered on chip by CLK. When active, after being clocked onto chip, INITTAC enables the clocking of data into the Timer increment Register, and also zeroes the feedback path in the Timer Accumulator. TEST I Test Select Input. Registered on chip by CLK. This input is active high. When active, this input enables test busses to the outputs instead of the sine and cosine data. PAR/SER I Parallel/Serial Output Select. This input is registered on chip by CLK. When low, the sine and cosine outputs are in serial mode. The Output Shift Registers will load in new data after ENPHAC goes low and will start shifting the data out after ENPHAC goes high. When this input is high, the Output Registers are loaded every clock and no shifting takes place. BINFMT I Format. This input is registered on chip by CLK. When low, the MSB of the SIN and COS are inverted to form an offset binary (unsigned) number. OES I Three-state control for bits SIN(15:0). Outputs are enabled when OES is low. OEC I Three-state control for bits COS(15:0). Outputs are enabled when OEC is low. TICO O Timer Accumulator Carry Output. Active low, registered. This output goes low when a carry is generated by the Timer Accumulator. DACSTRB O DAC Strobe (active low). In serial mode, this output will go low when the first bit of a new output word is valid at the shift register output. This pin is active only in serial mode. SIN(15:0) O Sine Output Data. When parallel mode is enabled, data is output on SIN(15:0). When serial mode is enabled, output data bits are shifted out of SIN15 and SIN0. The bit stream on SIN15 is provided MSB first while the bit stream on SIN0 is provided LSB first. COS(15:0) O Cosine Output Data. When parallel mode is enabled, data is output on COS(15:0). When serial mode is enabled, output data bits are shifted out of COS15 and COS0. The bit stream on COS15 is provided MSB first while the bit stream in COS0 is provided LSB first. Index Pin Used to align chip in socket or on circuit board. Must be left as a no connect in circuit. (CPGA Package only). Pin Descriptions (Continued) NAME TYPE DESCRIPTION HSP45106

FIGURE 1. BLOCK DIAGRAM OF THE HSP45106

16 COS

16 SIN

CS and WR are low (Table 1). Registers are updated on the rising edge of the following CLK. the least significant 32 bits of the result. number of clock cycles required to step from 0 to full scale. the contents of the Offset Frequency Register. TABLE 1. ADDRESS DECODE MAPPING

instantaneous phase which is fed to the Sine/Cosine Section. the Phase Offset Register while the lower 13 bits are cleared. Table 2. The control input ENPOREG acts as a clock enable the Timer Accumulator is the accumulator carry out, TICO. values are computed to reduce the amount of ROM needed.

1. An address of zero corresponds to 0 radians and

16-1)/(216+1) for symmetry about zero. or 0001H to FFFFH (offset binary mode). SIN(15:0) and COS(15:0) should be left floating. hold times or the clock to output delays. TABLE 2. MODULATION CONTROL MAP

FIGURE 5. SINE/COSINE SECTION BLOCK DIAGRAM FIGURE 6. SERIAL OUTPUT I/O TIMING DIAGRAM FIGURE 7. FREQUENCY TO OUTPUT DELAY

16 COSINE

16 SINE

Absolute Maximum Ratings TA =2 5oC Thermal Information Operating Conditions oC to 70oC Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) Maximum Junction Temperature (PLCC - Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Logical One Input Voltage V IH VCC = 5.25V 2.0 - V Logical Zero Input Voltage V IL VCC = 4.75V - 0.8 V High Level Clock Input V IHC VCC = 5.25V 3.0 - V Low Level Clock Input V ILC VCC = 4.75V - 0.8 V Output HIGH Voltage V OH IOH = -400µA, VCC = 4.75V 2.6 - V Output LOW Voltage V OL IOL = +2.0mA, VCC = 4.75V - 0.4 V Input Leakage Current I I VIN = VCC or GND, VCC = 5.25V -10 10 µA I/O Leakage Current I O VOUT = VCC or GND, VCC = 5.25V -10 10 µA Standby Power Supply Current I CCSB VIN = VCC or GND, VCC = 5.25V, Note 4 - 500 µA Operating Power Supply Current I CCOP f = 25.6MHz, VIN = VCC or GND VCC = 5.25V, Notes 2 and 4 - 180 mA Capacitance TA = 25oC, Note 3 PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Input Capacitance C IN FREQ = 1MHz, VCC = Open. All measurements are referenced to device ground -1 0 p F Output Capacitance C O -1 0 p F NOTES: 2. Power supply current is proportional to operating frequency. Typical rating for I CCOP is 7mA/MHz. 3. Not tested, but characterized at initial design and at major process/design changes. 4. Output load per test load circuit with switch open and C L = 40pF. HSP45106

25.6MHz 33MHz UNITSMIN MAX MIN MAX CLK Period t CP 39 - 30 - ns CLK High t CH 15 - 12 - ns CLK Low t CL 15 - 12 - ns WR Period t WP 39 - 30 - ns WR High t WH 15 - 12 - ns WR Low t WL 15 - 12 - ns Setup Time A(2:0), CS to WR Going High t AWS 13 - 13 - ns Hold Time A(2:0), CS from WR Going High t AWH 1-1- n s Setup Time C(15:0) to WR Going High t CWS 15 - 15 - ns Hold Time C(15:0) from WR Going High t CWH 0-0- n s Setup Time WR High to CLK High t WC Note 6 16 - 12 - ns, Setup Time MOD(2:0) to CLK Going High t MCS 15 - 15 - ns Hold Time MOD(2:0) from CLK Going High t MCH 0-0- n s Setup Time ENPOREG, ENOFREG, ENCFREG, ENPHAC, ENTIREG, INHOFR, PMSEL, INITPAC, BINFMT, TEST, PAR/SER, PACI, INITTAC to CLK Going High tECS 12 - 12 - ns Hold Time ENPOREG, ENOFREG, ENCFREG, ENPHAC, ENTIREG, INHOFR, PMSEL, INITPAC, BINFMT, TEST, PAR/SER, PACI, INITTAC from CLK Going High tECH 0-0- n s CLK to Output Delay SIN(15:0), COS(15:0), TICO t DO - 18 - 15 ns CLK to Output Delay DACSTRB t DSO 2 18 2 15 ns Output Enable Time t OE - 12 - 12 ns Output Disable Time t OD Note 7 - 15 - 15 ns Output Rise, Fall Time t RF Note 7 - 8 - 8 ns NOTES: 5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; input levels (all other inputs) 0V and 3.0V; timing reference levels (CLK) < 1.5V. 6. If ENOFREG, ENCFREG, ENTIREG, or ENPOREG are active, care must be taken to not violate setup and hold times to these registers when writing data into the chip via the C(15:0) port. 7. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes. HSP45106

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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FIGURE 12. OUTPUT ENABLE, DISABLE TIMING FIGURE 13. OUTPUT RISE AND FALL TIMES