HSP45102 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • 33MHz, 40MHz Versions
  • 32-Bit Frequency Control
  • BFSK, QPSK Modulation
  • Serial Frequency Load
  • 12-Bit Sine Output
  • Offset Binary Output Format
  • 0.009Hz Tuning Resolution at 40MHz
  • Spurious Frequency Components <-69dBc
  • Fully Static CMOS
  • Low Cost

Applications

  • Direct Digital Synthesis
  • Modulation
  • PSK Communications
  • Related Products - HI5731 12-Bit, 100MHz D/A Converter Block Diagram

Ordering Information

TEMP. RANGE ( oC) PACKAGE PKG. NO. HSP45102PC-33 0 to 70 28 Ld PDIP E28.6 HSP45102PC-40 0 to 70 28 Ld PDIP E28.6 HSP45102SC-33 0 to 70 28 Ld SOIC M28.3 HSP45102SC-40 0 to 70 28 Ld SOIC M28.3 HSP45102SI-33 -40 to 85 28 Ld SOIC M28.3 PHASE ACCUMULATOR FREQUENCY CONTROL SECTION PHASE OFFSET ADDER SINE ROM CLK PO-1 OUT0-11 MSB/ LSB SFTEN SD SCLK LO AD TXFR SEL_L /M ENPHA C 13 12 Data Sheet January 1999 File Number 2810.6 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

28 LEAD PDIP, 28 LEAD SOIC

VCC +5V power supply pin. GND Ground P0-1 I Phase modulation inputs (become active after a pipeline delay of four clocks). A phase shift of 0, 90, 180, or 270 degrees can be selected as shown in Table 1. CLK I NCO clock. (CMOS level) SCLK I This pin clocks the frequency control shift register. SEL_L/M I A high on this input selects the least significant 32 bits of the 64-bit frequency register as the input to the phase accumulator; a low selects the most significant 32 bits. SFTEN I The active low input enables the shifting of the frequency register. MSB/ LSB I This input selects the shift direction of the frequency register. A low on this input shifts in the data LSB first; a high shifts in the data MSB first. ENPHA C I This pin, when low, enables the clocking of the Phase Accumulator. This input has a pipeline delay of four clocks. SD I Data on this pin is shifted into the frequency register by the rising edge of SCLK when SFTEN is low. TXFR I This active low input is clocked onto the chip by CLK and becomes active after a pipeline delay of four clocks. When low, the frequency control word selected bySEL_L/M is transferred from the frequency register to the phase accumulator’s input register. LO AD I This input becomes active after a pipeline delay of five clocks. When low, the feedback in the phase accumulator is zeroed. OUT0-11 O Output data. OUT0 is LSB. Unsigned. All inputs are TTL level, with the exception of CLK. Ov erline designates active low signals. OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 GND VCC SEL_L /M SFTEN MSB/ LSB ENPHA C SD SCLK OUT5 OUT3 OUT2 OUT1 OUT0 GND LO AD TXFR CLK GND OUT4 VCC HSP45102

Absolute Maximum Ratings TA =2 5oC Thermal Information Operating Conditions Operating Voltage Range (Commercial, Industrial) . . +4.75V to +5.25V oC to 70oC Thermal Resistance (Typical, Note 1) θJA (oC/W) (SOIC - Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Logical One Input Voltage V IH VCC = 5.25V 2.0 - V Logical Zero Input Voltage V IL VCC = 4.75V - 0.8 V High Level Clock Input V IHC VCC = 5.25V 3.0 - V Low Level Clock Input V ILC VCC = 4.75V - 0.8 V Output HIGH Voltage V OH IOH = -400µA, VCC = 4.75V 2.6 - V Output LOW Voltage V OL IOL = +2.0mA, VCC = 4.75V - 0.4 V Input Leakage Current I I VIN = VCC or GND, VCC = 5.25V -10 10 µA Standby Power Supply Current I CCSB VIN = VCC or GND, VCC = 5.25V, Note 4 - 500 µA Operating Power Supply Current I CCOP f = 33MHz, VIN = VCC or GND VCC = 5.25V, Notes 2 and 4 -9 9 m A Capacitance TA = 25oC, Note 3 PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Input Capacitance C IN FREQ = 1MHz, VCC = Open. All measure- ments are referenced to device ground -1 0 p F Output Capacitance C O -1 0 p F NOTES: 2. Power supply current is proportional to operating frequency. Typical rating for ICCOP is 3mA/MHz. 3. Not tested, but characterized at initial design and at major process/design changes. 4. Output load per test load circuit with switch open and C L = 40pF. HSP45102

-33 (33MHz) -40 (40MHz) UNITSMIN MAX MIN MAX Clock Period t CP 30 - 25 - ns Clock High t CH 12 - 10 - ns Clock Low t CL 12 - 10 - ns SCLK High/Low t SW 12 - 10 - ns Setup Time SD to SCLK Going High t DS 12 - 12 - ns Hold Time SD from SCLK Going High t DH 0-0- n s Setup TimeSFTEN, MSB/ LSB to SCLK Going High t MS 15 - 12 - ns Hold TimeSFTEN, MS B/LSB from SCLK Going High t MH 0-0- n s Setup Time SCLK High to CLK Going High t SS Note 6 16 - 15 - ns Setup Time P0-1 to CLK Going High t PS 15 - 12 - ns Hold Time P0-1 from CLK Going High t PH 1-1- n s Setup TimeLO AD, TXFR, ENPHA C, SEL_L/M to CLK Going High tES 15 - 13 - ns Hold TimeLO AD, TXFR, ENPHA C, SEL_L/M from CLK Going High tEH 1-1- n s CLK to Output Delay t OH 2 15 2 13 ns Output Rise, Fall Time t RF Note 7 8 - 8 - ns NOTES: 5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; Input levels (all other inputs) 0V and 3.0V; Timing reference levels and VOL < 1.5V. 6. IfTXFR is active, care must be taken to not violate setup and hold times as data from the shift registers may not have settled before CLK occurs. 7. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. EQUIVALENT CIRCUIT C L (NOTE) IOH 1.5V I OL DUT SWITCH S1 OPEN FOR I CCSB AND ICCOP NOTE: Test head capacitance. HSP45102

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Waveforms FIGURE 4. tCP tCLtCH tPS tPH tES tEH tOH tRF tSW tSS tDS tDH tMHtMS tSW CLK SCLK SD MSB/ LSB, P0-1 OUT0-11 ENPHA C, SEL_L /M LO AD, TXFR, SFTEN HSP45102