HSP45102_07 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • 33MHz, 40MHz Versions
  • 32-Bit Frequency Control
  • BFSK, QPSK Modulation
  • Serial Frequency Load
  • 12-Bit Sine Output
  • Offset Binary Output Format
  • 0.009Hz Tuning Resolution at 40MHz
  • Spurious Frequency Components <-69dBc
  • Fully Static CMOS
  • L o w C o s t
  • Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

  • Direct Digital Synthesis
  • Modulation
  • PSK Communications
  • Related Products - HI5731 12-Bit, 100MHz D/A Converter

Ordering Information

TEMP. RANGE (°C) PACKAGE PKG. DWG. # HSP45102SC-33 HSP45102SC-33 0 to +70 28 Ld SOIC (300 mil) M28.3 HSP45102SC-33Z (Note) HSP45102SC-33Z 0 to +70 28 Ld SOIC (300 mil) (Pb-free) M28.3 HSP45102SC-40 HSP45102SC -40 0 to +70 28 Ld SOIC (300 mil) M28.3 HSP45102SC-40Z (Note) HSP45102SC-40Z 0 to +70 28 Ld SOIC (300 mil)(Pb-free) M28.3 HSP45102SI-3396 HSP45102SI -33 0 to +70 28 Ld SOIC (300 mil) (Tape and Reel) M28.3 HSP45102SI-33Z (Note) HSP45102SI-33Z 0 to +70 28 Ld SOIC (300 mil) (Pb-free) M28.3 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Data Sheet April 25, 2007 FN2810.9 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1999, 2004, 2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 FN2810.9 April 25, 2007 Block Diagram Pinout HSP45102 (28 LEAD SOIC) TOP VIEW PHASE ACCUMULATOR FREQUENCY CONTROL SECTION PHASE OFFSET ADDER SINE ROM CLK PO-1 OUT0-11 MSB/LSB SFTEN SD SCLK LOAD TXFR SEL_L/M ENPHAC 13 12 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 GND VCC SEL_L/M SFTEN MSB/LSB ENPHAC SD SCLK OUT5 OUT3 OUT2 OUT1 OUT0 GND LOAD TXFR CLK GND OUT4 VCC HSP45102

3 FN2810.9 April 25, 2007 Pin Description NAME TYPE DESCRIPTION VCC +5V power supply pin. GND Ground P0-1 I Phase modulation inputs (become active after a pipel ine delay of four clocks). A phase shift of 0°, 90°, 180°, or 270° can be selected as shown in Table 1. CLK I NCO clock. (CMOS level) SCLK I This pin clocks the frequency control shift register. SEL_L/M I A high on this input selects the least significant 32 bits of the 64-bit frequency register as the input to the phase accumulator; a low selects the most significant 32 bits. SFTEN I The active low input enables the shifting of the frequency register. MSB/LSB I This input selects the shift direction of the frequency register. A low on this input shifts in the data LSB first; a high shifts in the data MSB first. ENPHAC I This pin, when low, enables the clocking of the Phas e Accumulator. This input has a pipeline delay of four clocks. SD I Data on this pin is shifted into the frequency register by the rising edge of SCLK when SFTEN is low. TXFR I This active low input is clocked onto the chip by CLK and becomes active after a pipeline delay of four clocks. When low, the frequency control word selected by SEL_L/M is transferred from the frequency register to the phase accumulator’s input register. LOAD I This input becomes active after a pipeline delay of five clocks. When low, the feedback in the phase accumulator is zeroed. OUT0-11 O Output data. OUT0 is LSB. Unsigned. All inputs are TTL level, with the exception of CLK. Overline designates active low signals. HSP45102

6 FN2810.9 April 25, 2007 Absolute Maximum Ratings TA = +25°C Thermal Information Operating Conditions Operating Voltage Range (Commercial, Industrial) . . +4.75V to +5.25V Thermal Resistance (Typical, Note 1) θ JA (°C/W) http://www.intersil.com/pbfree/Pb-FreeReflow.asp Die Characteristics CAUTION: Stresses above those listed in “Abs olute Maximum Ratings” may cause permanent dam age to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Logical One Input Voltage V IH VCC = 5.25V 2.0 - V Logical Zero Input Voltage V IL VCC = 4.75V - 0.8 V High Level Clock Input V IHC VCC = 5.25V 3.0 - V Low Level Clock Input V ILC VCC = 4.75V - 0.8 V Output HIGH Voltage V OH IOH = -400μA, VCC = 4.75V 2.6 - V Output LOW Voltage V OL IOL = +2.0mA, VCC = 4.75V - 0.4 V Input Leakage Current I I VIN = VCC or GND, VCC = 5.25V -10 10 μA Standby Power Supply Current I CCSB VIN = VCC or GND, VCC = 5.25V, Note 4 - 500 μA Operating Power Supply Current I CCOP f = 33MHz, VIN = VCC or GND VCC = 5.25V, Notes 2 and 4 -9 9 m A Capacitance TA = +25°C, Note 3 PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Input Capacitance C IN FREQ = 1MHz, VCC = Open. All measurements are referenced to device ground -1 0 p F Output Capacitance C O -1 0 p F NOTES: 2. Power supply current is proportional to operating frequency. Typical rating for I CCOP is 3mA/MHz. 3. Not tested, but characterized at initial design and at major process/design changes. 4. Output load per test load circuit with switch open and C L = 40pF. HSP45102

7 FN2810.9 April 25, 2007 AC Test Load Circuit PARAMETER SYMBOL NOTES -33 (33MHz) -40 (40MHz) UNITSMIN MAX MIN MAX Clock Period t CP 30 - 25 - ns Clock High t CH 12 - 10 - ns Clock Low t CL 12 - 10 - ns SCLK High/Low t SW 12 - 10 - ns Setup Time SD to SCLK Going High t DS 12 - 12 - ns Hold Time SD from SCLK Going High t DH 0-0- n s Setup Time SFTEN, MSB/LSB to SCLK Going High t MS 15 - 12 - ns Hold Time SFTEN, MSB/LSB from SCLK Going High t MH 0-0- n s Setup Time SCLK High to CLK Going High t SS Note 6 16 - 15 - ns Setup Time P0-1 to CLK Going High t PS 15 - 12 - ns Hold Time P0-1 from CLK Going High t PH 1-1- n s Setup Time LOAD, TXFR, ENPHAC, SEL_L/M to CLK Going High tES 15 - 13 - ns Hold Time LOAD, TXFR, ENPHAC, SEL_L/M from CLK Going High tEH 1-1- n s CLK to Output Delay t OH 21 521 3 n s Output Rise, Fall Time t RF Note 7 8 - 8 - ns NOTES: 5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; Input levels (all other inputs) 0V and 3.0V; Timing reference levels VOL < 1.5V. 6. If TXFR is active, care must be taken to not violate setup and hold times as data from the shift registers may not have settled before CLK occurs. 7. Controlled via design or process parame ters and not directly tested. Characterized upon initial design and after major process and/or design changes. EQUIVALENT CIRCUIT CL (NOTE) IOH 1.5V I OL DUT SWITCH S1 OPEN FOR ICCSB AND ICCOP NOTE: Test head capacitance. HSP45102

8 FN2810.9 April 25, 2007 Waveforms FIGURE 4. tCP tCLtCH tPS tPH tES tEH tOH tRF tSW tSS tDS tDH tMHtMS tSW CLK SCLK SD MSB/LSB, P0-1 OUT0-11 ENPHAC, SEL_L/M LOAD, TXFR, SFTEN HSP45102

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2810.9 April 25, 2007 HSP45102 Small Outline Plastic Packages (SOIC) α NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. In- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional . If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimen- sions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45o C H 0.25(0.010) BM M M28.3 (JEDEC MS-013-AE ISSUE C)

28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4 e 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N2 8 2 8 7 α 0o 8o 0o 8o - Rev. 0 12/93