HSP43891JC-20

HSP43891 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 18

Technical content

Features

• Eight Filter Cells
• 0MHz to 30MHz Sample Rate
• 9-Bit Coefficients and Signal Data
• 26-Bit Accumulator per Stage
• Filter Lengths Over 1000 Taps
• Expandable Coefficient Size, Data Size and Filter Length
• Decimation by 2, 3 or 4

Applications

• 1-D and 2-D FIR Filters
• Radar/Sonar
• Digital Video
• Adaptive Filters
• Echo Cancellation
• Complex Multiply-Add - Sample Rate Converters Block Diagram

Ordering Information

TEMP. RANGE ( oC) PACKAGE PKG. NO. HSP43891VC-20 0 to 70 100 Lead MQFP Q100.14x20 HSP43891VC-25 0 to 70 100 Lead MQFP Q100.14x20 HSP43891VC-30 0 to 70 100 Lead MQFP Q100.14x20 HSP43891JC-20 0 to 70 84 Lead PLCC N84.1.15 HSP43891JC-25 0 to 70 84 Lead PLCC N84.1.15 HSP43891JC-30 0 to 70 84 Lead PLCC N84.1.15 HSP43891GC-20 0 to 70 85 Pin CPGA G85.A HSP43891GC-25 0 to 70 85 Pin CPGA G85.A HSP43891GC-30 0 to 70 85 Pin CPGA G85.A CIN0 - 8 DF FILTER CELL 7 COUT0 - 8 ERASE DCM0 - 1 DIENB CIENB COENB MUX RESET 26 ADR0, ADR1, ADR2 CLK RESET SHADD SENBH SENBL OUTPUT STAGE VCC VSS DIN0 - DIN8 SUM0 - 25 DF FILTER CELL 6 DF FILTER CELL 5 DF FILTER CELL 4 DF FILTER CELL 3 DF FILTER CELL 2 DF FILTER CELL 1 DF FILTER CELL 0 5CLK ADRO - 2 Data Sheet May 1999

85 PIN GRID ARRAY (PGA)

84 LEAD PLASTIC LEADED CHIP CARRIER (PLCC)

A B C D E F G H J K L COENB RESET DIN7VCC DIN6 DIN3 DIN0 CIN8 VCC VCC COUT7 ERASE DIN1 DIN2 CIENB CIN7 CIN6 CIN4 COUT5 COUT6 ALIGN PIN DIENB DIN5 DIN4 CIN5 CIN3 CIN2 VCC CIN1 CIN0 SENBL COUT3 COUT4 COUT1 VSS COUT2 VSS COUT0 SHADD ADR2 DCM0 CLK SUM0 VCC VSS SUM1 SUM3 SUM2 SUM5 SUM4ADR0 SUM25VCC SUM7 VSSSUM16SUM17SUM20 SENBH SUM24 VSS VCC SUM19 VSS SUM15 SUM12 SUM10 SUM8 SUM6 SUM9SUM11VSSSUM13VCCSUM14SUM18SUM21SUM22SUM23DCM1 217 3 4 5 6 8 9 10 11 VSS COUT8 DIN8 ADR1 HSP43891 BOTTOM VIEW PINS UP DCM1 SUM23 SUM22 SUM21 SUM18 SUM14 SUM13 SUM11 SUM9VSSVCC SUM20 SUM17 SUM16 SUM7 ADR0 SUM5 SUM4 ADR2 DCM0 CLK VSS COUT0 SHADD SUM1 SUM3 SUM2 SUM0 VCC VSS CIN2 VCCCOUT3 COUT4 ALIGN PIN A B C D E F G H J K L 123 45678 9 1 0 1 1 ADR1 SUM25VCC VSS VSS VCC VSSSENBH SUM24 SUM19 SUM15 SUM12 SUM10 SUM8 SUM6 CIN1 CIN0 SENBLCOUT1 VSS COUT2 COUT5COUT6 DIENB DIN5 DIN4 CIN5 CIN3 VCC VSSDIN0DIN3DIN6DIN7VSS COENB VCC RESET CIN8 VCC CIN4CIN6CIN7CIENBDIN2DIN1ERASECOUT7 DIN8COUT8 TOP VIEW PINS DOWN HSP43891 VSS 1 1 1 0 987654321 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 HSP43891 TOP VIEW SUM22 SUM18 SUM16 SUM15 SUM14 SUM13 SUM12 SUM11 SUM23 SUM21 SUM20 SUM19 SUM17 COUT6 COUT7 COUT8 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 VCC VSS VCC VSS SUM10 SUM9 SUM8 SUM7 SUM1 SUM2 SUM3 SUM4 SUM5 SUM6 VSS VCC CIN4 CIN3 CIN2 CIN0 SUM0 V SS CIN1 VCC CIN5 VSS CIN7 CIN6 SENBL DIN1 DIN0 CIN8 VCC VCC VSS DIENB RESET COENB ERASE ADDR2 DCM0 ADDR1 SUM25 CLK COUT0 SHADD COUT2 DCM1 SUM24 COUT1 VSS VCC ADDR0 VSS VSS COUT3 COUT4 COUT5 VCC CIENB SENBH HSP43891

100 LEAD MQFP

Pinout (Continued) 99 98 97 96 95 94 93 91 89 87 85 84 83 818286889092100 CIENB CIN8 VCC CIN6 VSS CIN7 DIN0 RESET DIENB DIN8 DIN7 DIN5 DIN4 DIN3 DIN2 DIN1 DIN6 ERASE COUT5 VCC VCC COUT6 VSS VSS COENB VCC VCC COUT7 COUT4 COUT8 VCC VSS VSS SUM17 SUM16 VCC SUM15 SUM14 SUM13 SUM12 SUM18 SUM11 V SS SUM24 VSS VSS SUM23 SUM22 V CC VCC SUM21 SUM20 SUM19 DCM1 SUM10 SUM9 NC SUM8 SUM7 SUM6 32 33 34 35 36 37 38 40 42 44 46 47 48 50494543413931 VCC VSS VSS SUM5 SUM4 SUM3 SUM2 SUM1 SUM0 V SS VSS SENBL CIN0 CIN1 VCC CIN2 CIN3 CIN4 CIN5 V SS VCC VCC SUM25 VSS VSS COUT3 COUT2 COUT1 COUT0 SHADD CLK ADDR2 DCM0 V SS VSS ADDR1 ADDR0 V CC VCC SENBH HSP43891

NUMBER TYPE NAME AND FUNCTION VCC B1, J1, A3, K4, L7, A10, F10, D11 +5 power supply input. VSS A1, F1, E2, K3, K6, L9, A11, F11, J11 Power supply ground input. CLK G3 I The CLK input provides the DF system sample clock. The maximum clock frequency is 30MHz. DIN0-8 A5-8, B5-7, C6, I These nine inputs are the data sample input bus. Nine-bit data samples are synchronously loaded through these pins to the X register of each filter cell of the DF simultaneously. TheDIENB signal en- ables loading, which is synchronous on the rising edge of the clock signal. The data samples can be either 9-bit two’s complement or 8-bit unsigned values. For 9-bit two’s com- plement values, DIN8 is the sign bit. For 8-bit unsigned values, DIN8 must be held at logical zero. DIENB C5 I A low on this input enables the data sample input bus (DIN0-8) to all the filter cells. A rising edge of the CLK signal occurring whileDIENB is low will load the X register of every filter cell with the 9-bit value present on DIN0-8. A high on this input forces all the bits of the data sample input bus to zero; a rising CLK edge when DIENB is high will load the X register of every filter cell with all zeros. This signal is latched inside the device, delaying its effect by one clock internal to the device. Therefore it must be low during the clock cycle immediately preceding presentation of the desired data on the DIN0-8 inputs. De- tailed operation is shown in later timing diagrams. CIN0-8 A9, B9-11, C10, C11, D10, E9, E10 I These nine inputs are used to input the 9-bit coefficients. The coefficients are synchronously loaded into the C register of filter CELL0 if a rising edge of CLK occurs while CIENB is low. TheCIENB signal is delayed by one clock as discussed below. The coefficients can be either 9-bit two’s complement or 8-bit unsigned values. For 9-bit two’s comple- ment values, CIN8 is the sign bit. For 8-bit unsigned values, CIN8 must be held at logical zero. ALIGN PIN C3 Used for aligning chip on socket or printed circuit board. This pin must be left as a no connect in circuit. CIENB B8 I A low on this input enables the C register of every filter cell and the D (decimation) registers of every filter cell according to the state of the DCM0-1 inputs. A rising edge of the CLK signal occurring while CIENB is low will load the C register and appropriate D registers with the coefficient data present at their inputs. This provides the mechanism for shifting coefficients from cell to cell through the device. A high on this input freezes the contents of the C register and the D registers, ignoring the CLK signal. This signal is latched and delayed by one clock internal to the DF . Therefore it must be low during the clock cycle immediately preceding presentation of the desired coefficient on the CIN0-8 inputs. Detailed operation is shown in later timing diagrams. COUT0-8 B2, B3, C1, D1, E1, C2, D2, F2, O These nine three-state outputs are used to output the 9-bit coefficients from filter CELL7. These outputs are enabled by the COENB signal low. These outputs may be tied to the CIN0-8 inputs of the same DF to recirculate to coefficients, or they may be tied to the CIN0-8 inputs of another DF to cascade DFs for longer filter lengths. COENB A2 I A low on the COENB input enables the COUT0-8 outputs. A high on this input places all these outputs in their high impedance state. DCM0-1 L1, G2 I These two inputs determine the use of the internal decimation registers as follows: DCM1 DCM0 DECIMATION FUNCTION 0 0 Decimation registers not used 0 1 One decimation register is used 1 0 Two decimation registers are used 1 1 Three decimation registers are used The coefficients pass from cell to cell at a rate determined by the number of decimation registers used. When no decimation registers are used, coefficients move from cell to cell on each clock. When one decimation register is used, coefficients move from cell to cell on every other clock, etc. These signals are latched and delayed by one clock internal to the device. HSP43891

The Digital Filter Processor (DF) is composed of eight filter cells cascaded together and an output stage for combining or selecting filter cell outputs (See Block Diagram). Each filter cell contains a multiplier-accumulator and several registers (Figure 1). Each 9-bit coefficient is multiplied by a 9-bit data sample, with the result added to the 26-bit accumulator contents. The coefficient output of each cell is cascaded to the coefficient input of the next cell to its right. DF Filter Cell A 9-bit coefficient (CIN0-8) enters each cell through the C register on the left and exits the cell on the right as signals COUT0-8. With no decimation, the coefficient moves directly from the C register to the output, and is valid on the clock following its entrance. When decimation is selected the coefficient exit is delayed by 1, 2 or 3 clocks by passing through one or more decimation registers (D1, D2 or D3). The combination of D registers through which the coefficient passes is determined by the state of DCM0 and DCM1. The output signals (COUT0-8) are connected to the CIN0-8 inputs of the next cell to its right. The COENB input signal enables the COUT0-8 outputs of the right most cell to the COUT0-8 pins of the device. The C and D registers are enabled for loading by CIENB. Loading is synchronous with CLK whenCIENB is low. Note thatCIENB is latched internally. It enables the register for loading after the next CLK following the onset ofCIENB low. Actual loading occurs on the second CLK following the onset of CIENB low. ThereforeCIENB must be low during the clock cycle immediately preceding presentation of the coefficient on the CIN0-8 inputs. In most basic FIR operations, CIENB will be low throughout the process, so this latching and delay sequence is only important during the initialization phase. When CIENB is high, the coefficients are frozen. The C and D registers are cleared synchronously under control ofRESET, which is latched and delayed exactly likeCIENB. The output of the C register (C0-8) is one input to 9 x 9 multiplier. The other input to the 9 x 9 multiplier comes from the output of the X register. This register is loaded with a data sample from the device input signals DIN0-8 discussed above. The X register is enabled for loading by DIENB. Loading is synchronous with CLK whenDIENB is low. Note thatDIENB is latched internally. It enables the register for loading after the next CLK following the onset of DIENB low. Actual loading occurs on the second CLK following the onset of DIENB low; therefore,DIENB must be low during the clock SUM0-25 F9, G9-G11, H10, H11, J2, J5-J7, J10, K2, K5, K7-K11, L2-L6, L8, L10, L11 O These 26 three-state outputs are used to output the results of the internal filter cell computations. Indi- vidual filter cell results or the result of the shift and add output stage can be output. If an individual filter cell result is to be output, the ADR0-2 signals select the filter cell result. The SHADD signal determines whether the selected filter cell result or the output stage adder result is output. The signals SENBH and SENBL enable the most significant and least significant bits of the SUM0-25 result respectively. Both SENBH and SENBL may be enabled simultaneously if the system has a 26-bit or larger bus. However individual enables are provided to facilitate use with a 16-bit bus. SENBH K1 I A low on this input enables result bits SUM16-25. A high on this input places these bits in their high impedance state. SENBL E11 I A low on this input enables result bits SUM0-15. A high on this input places these bits in their high im- pedance state. ADR0-2 G1, H1, H2 I These three inputs select the one cell whose accumulator will be read through the output bus (SUM0- 25) or added to the output stage accumulator. They also determine which accumulator will be cleared when ERASE is low. These inputs are latched in the DF and delayed by one clock internal to the device. If ADR0-2 remains at the same address for more than one clock, the output at SUM0-25 will not change to reflect any subsequent accumulator updates in the addressed cell. Only the result available during the first clock, when ADR0-2 selects the cell, will be output. This does not hinder normal operation since the ADR0-2 lines are changed sequentially. This feature facilitates the interface with slow memories where the output is required to be fixed for more than one clock. SHADD F3 I The SHADD input controls the activation of the shift and add operation in the output stage. This signal is latched on chip and delayed by one clock internal to the device. Detailed explanation is given in the DF Output Stage section. RESET A4 I A low on this input synchronously clears all the internal registers, except the cell accumulators It can be used withERASE to also clear all the accumulators simultaneously. This signal is latched in the DF and delayed by one clock internal to the device. ERASE B4 I A low on this input synchronously clears the cell accumulator selected by the ADR0-2 signals. IfRESET is also low simultaneously, all cell accumulators are cleared. Pin Description (Continued) SYMBOL PIN NUMBER TYPE NAME AND FUNCTION HSP43891

cycle immediately preceding presentation of the data sample on the DIN0-8 inputs. In most basic FIR operations,DIENB will be low throughout the process, so this latching and delay sequence is only important during the initialization phase. When DIENB is high, the X register is loaded with all zeros. The multiplier is pipelined and is modeled as a multiplier core followed by two pipeline registers, MREG0 and MREG1 (Figure 1). The multiplier output is sign extended and input as one operand of the 26-bit adder. The other adder operand is the output of the 26-bit accumulator. The adder output is loaded synchronously into both the accumulator and the TREG. The TREG loading is disabled by the cell select signal, CELLn, where n is the cell number. The cell select is decoded from the ADR0-2 signals to generate the TREG load enable. The cell select is inverted and applied as the load enable to the TREG. Operation is such that the TREG is loaded whenever the cell is not selected. Therefore, TREG is loaded every clock except the clock following cell selection. The purpose of the TREG is to hold the result of a sum-of- products calculation during the clock when the accumulator is cleared to prepare for the next sum-of-products calculation. This allows continuous accumulation without wasting clocks. The accumulator is loaded with the adder output every clock unless it is cleared. It is cleared synchronously in two ways. When RESET and ERASE are both low, the accumulator is cleared along with all other registers on the device. Since ERASE and RESET are latched and delayed one clock internally, clearing occurs on the second CLK following the onset of both ERASE and RESET low. The second accumulator clearing mechanism clears a single accumulator in a selected cell. The cell select signal, CELLn, decoded from ADR0-2 and the ERASE signal enable clearing of the accumulator on the next CLK. The ERASE and RESET signals clear the DF internal registers and states as follows: The DF Output Stage The output stage consists of a 26-bit adder, 26-bit register, feedback multiplexer from the register to the adder, an output multiplexer and a 26-bit three-state driver stage (Figure 2). The 26-bit output adder can add any filter cell accumulator result to the 18 most significant bits of the output buffer. This result is stored back in the output buffer. This operation takes place in one clock period. The eight LSBs of the output buffer are lost. The filter cell accumulator is selected by the ADR0-2 inputs. The 18 MSBs of the output buffer actually pass through the zero mux on their way to the output adder input. The zero mux is controlled by the SHADD input signal and selects either the output buffer 18 MSBs or all zeros for the adder input. A low on the SHADD input selects zero. A high on the SHADD input selects the output buffer MSBs, thus, activating the shift-and-add operation. The SHADD signal is latched and delayed by one clock internally. ERASE RESET CLEARING EFFECT 1 1 No clearing occurs, internal state remains same.

10 RESET only active, all registers except ac-

cumulators are cleared, including the inter- nal pipeline registers. ERASE only active, the accumulator whose address is given by the ADR0-2 in- puts is cleared. 0 0 Both RESET and ERASE active, all accu- mulators as well as all other registers are cleared. HSP43891

FIGURE 1. HSP43891 DF FILTER CELL

when ADR0-2 selects the cell will be output. be fixed for more than one clock. either 8-bit unsigned or 9-bit two’s complement numbers. available every system clock.

18 MSBs SHIFTED

8 BITS TO RIGHT

FIGURE 2. HSP43891 DFP OUTPUT STAGE

• Two Positive Vectors 2080 1032
• Negative Vectors 2047 1024
• One Positive and One Negative Vector 2064 1028 One Unsigned 8-Bit Vector and One Two’s Complement Vector
• Positive Two’s Complement Vector 1036 1032
• Negative Two’s Complement Vector 1028 1028 HSP43891

TABLE 1. HSP43891 30MHz, 8-TAP FIR FILTER SEQUENCE

26 SUM

FIGURE 3. HSP43891 30MHz, 8-TAP FIR FILTER APPLICATION SCHEMATIC

Extended FIR Filter Length Filter lengths greater that eight taps can be created by either cascading together multiple DF devices or “reusing” a single device. Using multiple devices, an FIR filter of over 1000 taps can be constructed to operate at a 30MHz sample rate. Using a single device clocked at 30MHz, an FIR filter of over 500 taps can be constructed to operate at less than a 30MHz sample rate. Combinations of these two techniques are also possible. Cascade Configuration To design a filter length L>8, L/8 DFs are cascaded by connecting the COUT0-8 outputs of the (i)th DF to the CIN0- 8 inputs of the (i+1)th DF . The DIN0-8fs inputs and SUM0-25 outputs of all the DFs are also tied together. A specific example of two cascaded DFs illustrates the technique (Figure 5). Timing (Figure 6) is similar to the simple 8-tap FIR, except the ERASE and SENBL/ SENBH signals must be enabled independently for the two DFs in order to clear the correct accumulators and enable the SUM0-25 output signals at the proper times. TABLE 2. CLK CELL 0 CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 CELL 7 SUM/CLR C 15 x X0 +C 14 x X1 +C 13 x X2 +C 12 x X3 +C 11 x X4 +C 10 x X5 +C 9 x X6 +C 8 x X7 +C 7 x X8 +C 6 x X9 +C 5 x X10 +C 4 x X11 +C 3 x X12 +C 2 x X13 +C 1 x X14 +C 0 x X15 C 15 x X8 +C 14 x X9 +C 13 x X10 +C 12 x X11 +C 11 x X12 +C 10 x X13 +C 9 x X14 +C 8 x X15 +C 7 x X16 +C 6 x X17 +C 5 x X18 +C 4 x X19 +C 3 x X20 +C 2 x X21 +C 1 x X22 +C 0 x X23 C 15 x X1 C 0 x X16 15 x X9 C 0 x X23 C 15 x X2 C 0 x X17 +C 15 x X10 C 0 x X25 C 15 x X3 +C 14 x X4 +C 13 x X5 +C 12 x X6 +C 11 x X7 +C 10 x X8 +C 9 x X9 +C 8 x X10 +C 7 x X11 +C 6 x X12 +C 5 x X13 +C 4 x X14 +C 3 x X15 +C 2 x X16 +C 1 x X17 +C 0 x X18 15 x X11 C 0 x X26 C 15 x X4 C 0 x X19 15 x X12 C 0 x X27 C 15 x X5 C 0 x X20 15 x X12 C 15 x X6 C 0 x X21 15 x X14 C 15 x X7 +C 14 x X8 +C 13 x X9 +C 12 x X10 +C 11 x X11 +C 10 x X12 +C 9 x X13 +C 8 x X14 +C 7 x X15 +C 6 x X16 +C 5 x X17 +C 4 x X18 +C 3 x X19 +C 2 x X20 +C 1 x X21 +C 0 x X22 C 15 x X15 +C 14 x X16 +C 13 x X17 +C 12 x X18 +C 11 x X19 +C 10 x X20 +C 9 x X21 +C 8 x X22 +C 7 x X23 +C 6 x X24 +C 5 x X25 +C 4 x X26 +C 3 x X27 Cell 0 (Y 15) Cell 1 (Y16) Cell 2 (Y17) Cell 3 (Y18) Cell 4 (Y19) Cell 5 (Y20) Cell 6 (Y21) Cell 7 (Y22) Cell 0 (Y 23) Cell 1 (Y24) Cell 2 (Y25) Cell 3 (Y26) Cell 4 (Y27) HSP43891

Single DF Configuration Using a single DF , a filter of length L>8 can be constructed by processing in L/8 passes, as illustrated in Table 2, for a 16-tap FIR. Each pass is composed of Tp = 7 + L cycles and computes eight output samples. In pass i, the sample with indices i*8 to i*8 +(L-1) enter the DIN0-8 inputs. The coefficients C 0 - CL - 1 enter the CIN0-8 inputs, followed by seven zeros. As these zeros are entered, the result samples are output and the accumulators reset. Initial filing of the pipeline is not shown in this sequence table. Filter outputs can be put through a FIFO to even out the sample rate. Extended Coefficient and Data Sample Word Size The sample and coefficient word size can be extended by utilizing several DFs in parallel to get the maximum sample rate or a single DF with resulting lower sample rates. The technique is to compute partial products of 9 x 9 and combine these partial products by shifting and adding to obtain the final result. The shifting and adding can be accomplished with external adders (at full speed) or with the DF’s shift-and-add mechanism contained in its output stage (at reduced speed). Decimation/Resampling The HSP43891 DF provides a mechanism for decimating by factors of 2, 3, or 4. From the DF filter cell block diagram (Figure 1), note the three D registers and two multiplexers in the coefficient path through the cell. These allow the coefficients to be delayed by 1, 2, or 3 clocks through the cell. The sequence table (Table 3) for a decimate-by-two filter illustrates the technique (internal cell pipelining ignored for simplicity). Detailed timing for a 30MHz input sample rate, 15MHz output sample rate (i.e., decimate-by-two), 16-tap FIR filter, including pipelining, is shown in Figure 7. This filter requires only a single HSP43891 DF . HSP43891

FIGURE 6. HSP43891 16-TAP 30MHz FILTER TIMING USING TWO CASCADED HSP43891s

TABLE 3. HSP43891 16-TAP DECIMATE-BY-TWO FIR FILTER SEQUENCE; 30MHz IN, 15MHz OUT

22 C 15 x X16 +C 1 x X16 +C 3 x X16 +C 5 x X16 +C 7 x X16 +C 9 x X16 +C 11 x X16 +C 13 x X16 -

FIGURE 7. HSP43891 16-TAP DECIMATE-BY-TWO FIR FILTER TIMING; 30MHz IN, 15MHz OUT

Absolute Maximum Ratings Thermal Information Junction Temperature oC Operating Conditions Thermal Resistance (Typical, Note 1)θJA (oC/W)θJC (oC/W) Typical Package Power Dissipation at 70 oC (PLCC MQFP Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Power Supply Current I CCOP VCC = Max, CLK Frequency 20MHz (Notes 2, 4) - 140 mA Standby Power Supply Current I CCSB VCC = Max (Note 4) - 500 µA Input Leakage Current I I VCC = Max, Input = 0V or VCC -10 10 µA Output Leakage Current I O VCC = Max, Input = 0V or VCC -10 10 µA Logical One Input Voltage V IH VCC = Max 2.0 - V Logical Zero Input Voltage V IL VCC = Min - 0.8 V Logical One Output Voltage V OH IOH = -400µA, VCC = Min 2.6 - V Logical Zero Output Voltage V OL IOL = 2mA, VCC = Min - 0.4 V Clock Input High V IHC VCC = Max 3.0 - V Clock Input Low V ILC VCC = Min - 0.8 V Input Capacitance PLCC C IN CLK Frequency 1MHz All measurements referenced to GND, TA = 25oC (Note 3) -1 0 p F CPGA -1 5 p F Output Capacitance PLCC C OUT -1 0 p F CPGA -1 5 p F NOTES: 2. Operating supply current is proportional to frequency. Typical rating is 7mA/MHz. 3. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 4. Output load per test load circuit and C L = 40pF. HSP43891

UNITSMIN MAX MIN MAX MIN MAX Clock Period t CP 5 0-3 9-3 3-n s Clock Low t CL 2 0-1 6-1 3-n s Clock High t CH 2 0-1 6-1 3-n s Input Setup t IS 1 6-1 4-1 3-n s Input Hold t IH 0-0-0- n s CLK to Coefficient Output Delay tODC -2 4-2 0-1 8 n s Output Enable Delay t OED -2 0-1 5-1 5 n s Output Disable Delay t ODD Note 5 - 20 - 15 - 15 ns CLK to SUM Output Delay t ODS -2 7-2 5-2 1 n s Output Rise t OR Note 5 - 6-6-6 n s Output Fall t OF Note 5 - 6-6-6 n s NOTE: 5. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. DUT EQUIVALENT CIRCUIT 1.5V I OLIOH † CL (NOTE) INCLUDES STRAY AND JIG CAPACITANCE NOTE: Switch S1 Open for ICCSB and ICCOP Tests. HSP43891

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

1130 Brussels, Belgium

FIGURE 8. CLOCK AC PARAMETERS FIGURE 9. INPUT SETUP AND HOLD FIGURE 10. SUM0-25, COUT0-8, OUTPUT DELAYS FIGURE 11. RISE AND FALL TIMES FIGURE 12. OUTPUT ENABLE, DISABLE TIMING FIGURE 13. AC TESTING INPUT, OUTPUT WAVEFORM